Multicore Salsa: Parallel Programming 2 0

1

Multicore Sals

Parallel Programming 2.0

SC07 Reno Nevada November 14 2007

Geoffrey Fox, Huapeng Yuan, Seung-Hee Bae

Community Grids Laboratory, Indiana University Bloomington IN 47404

Xiaohong Qiu

Research Computing UITS

,

George Chrysanthakopoulos, Henrik Frystyk Nielsen

2

Abstract of Multicore Sals

Parallel Programming 2.0

• Multicore or manycore systems are probably not architecturally that

different from parallel machines with which we are familiar. However in next 5-8 years the basic commodity (PC) chips will have 64-256 cores and currently there is little understanding of how to use them. It is

clearly essential (at least for major US technology companies) that we effectively use such cores on broadly deployed machines.

• This constraint makes multicore chips an exciting and different

problem

We describe general issues in context of the SALSA project at

http://www.infomall.org/multicore. This is using Service Aggregated Linked Sequential Activities where we are looking at a suite of parallel datamining applications as one important broadly useful capability for future multicore-based systems that will offer users navigation and advice based on the ever increasing data from sensors and the

Internet. A key idea is using services not libraries as the basic building block so that we can offer productive user interfaces (Parallel

Programming 2.0) by adapting workflow and mashups for composing parallel services. We still imagine that services will be constructed by experts using extensions of current threading and MPI models.

Some links

n

See

http://www.connotea.org/user/crmc

for

references

-- select tag

oldies

for venerable links; tags like

MPI

Applications Compiler

have obvious significance

n

h

ttp://www.infomall.org/salsa fo

r recent work

including publications

n

My tutorial on parallel computing

Too much Computing?

• Historically both grids and parallel computing have tried to

increase computing capabilities by

− Optimizing performance of codes at cost of re-usability

− Exploiting all possible CPU’s such as Graphics

co-processors and “idle cycles” (across administrative domains)

− Linking central computers together such as NSF/DoE/DoD

supercomputer networks without clear user requirements

• Next Crisis in technology area will be the opposite problem –

commodity chips will be 32-128way parallel in 5 years time and we currently have no idea how to use them – especially on

clients

− Only 2 releases of standard software (e.g. Office) in this time

span so need solutions that can be implemented in next 3-5 years

• Note that even cell phones will be multicore

• There is “Too much data” as well as “Too much computing” and

maybe processing the data deluge will “solve” the “Too much

computing” problem

− Quite plausible on servers where we naturally will have lots of

data

− Less clear on clients but short of other ideas

− Intel RMS analysis: Gaming and Generalized decision support

Tomorrow What

is …? it …?Is Whatif …?

Recognition Mining Synthesis

Create a model instance

RMS: Recognition Mining Synthesis

Model-based multimodal recognition Find a model instance Model

Real-time analytics on dynamic, unstructured, multimodal datasets Photo-realism and physics-based animation Today

Model-less Real-time streaming andtransactions on static – structured

datasets

Too much Data to the Rescue?

Multicore servers

have clear “universal parallelism” as many

users can access and use machines simultaneously

n

Maybe also need

application parallelism

(e.g. datamining) as

needed on client machines

n

Over next years, we will be submerged of course in

data

deluge

•

Scientific observations for e-Science

Local (video, environmental) sensors

•

Data fetched from Internet defining users interests

n

Maybe

data-mining

of this

“too much data”

will use up the

“too much computing”

both for science and commodity PC’s

•

PC will use this data(-mining) to be

intelligent user

assistant

?

Parallel Programming Model

• If multicore technology is to succeed, mere mortals must be able

to build effective parallel programs

• There are interesting new developments – especially the new

Darpa HPCS Languages X10, Chapel and Fortress

• However if mortals are to program the 64-256 core chips

expected in 5-7 years, then we must use near term technology and we must make it easy

− This rules out radical new approaches such as new languages • Remember that the important applications are not scientific

computing but most of the algorithms needed are similar to those explored in scientific parallel computing

• We can divide problem into two parts:

− Micro-parallelism: High Performance scalable (in number of

cores) parallel kernels or libraries

− Macro-parallelism: Composition of kernels into complete

applications

• We currently assume that the kernels of the scalable parallel

algorithms/applications/libraries will be built by experts with a

• Broader group of programmers (mere mortals) composing library

Multicore SALSA at CGL

•

S

ervice

A

ggregated

L

inked

S

equential

A

ctivities

•

Aims to

link parallel and distributed

(Grid) computing by

developing

parallel applications as services and not as

programs or

libraries

−

Improve traditionally poor parallel programming

development environments

•

Developing set of

services (library)

of

multicore parallel

data mining algorithms

•

Looking at Intel list of algorithms (and all previous

experience), we find there are two styles of “micro”

parallelism

− Dynamic search as in integer programming, Hidden Markov

Methods (and computer chess); irregular synchronization with dynamic threads

− “MPI Style” i.e. several threads running typically in SPMD (Single

Program Multiple Data); collective synchronization of all threads together

•

Most Intel RMS

are “MPI Style” and very close to

scientific

Scalable Parallel Components

•

There are

no agreed high-level programming

environments

for building library members that are broadly applicable.

•

However lower level approaches where

experts define

parallelism explicitly

are available and have clear

performance models.

•

These include

MPI

for messaging or just

locks

within a

single shared memory.

•

There are

several patterns

to support here including the

collective synchronization of MPI, dynamic irregular thread

parallelism needed in search algorithms, and more

specialized cases like

discrete event simulation

.

•

We use Microsoft CC

There is MPI style messaging and ..

•

OpenMP

annotation or

Automatic Parallelism

of

existing

software

is practical way to use those pesky cores with

existing code

− As parallelism is typically not expressed precisely, one needs luck to

get good performance

− Remember writing in Fortran, C, C#, Java … throws away information

about parallelism

•

HPCS

Languages should be able to properly express

parallelism but we do not know how efficient and reliable

compilers will be

− High Performance Fortran failed as language expressed a subset of

parallelism and compilers did not give predictable performance

•

PGAS

(Partitioned Global Address Space) like UPC,

Co-array Fortran, Titanium, HPJava

− One decomposes application into parts and writes the code for each

component but use some form of global index

− Compiler generates synchronization and messaging

− PGAS approach should work but has never been widely used –

Summary of micro-parallelism

•

On

new applications

, use MPI/locks with

explicit user decomposition

•

A subset of applications can use “

data

parallel

” compilers which follow in HPF

footsteps

−

Graphics Chips and Cell processor motivate

such special compilers but not clear how many

applications can be done this way

•

OpenMP and/or Compiler-based Automatic

Parallelism for

existing codes

in

Composition of Parallel Components

• The composition (macro-parallelism) step has many excellent

solutions as this does not have the same drastic

synchronization and correctness constraints as one has for scalable kernels

− Unlike micro-parallelism step which has no very good

solutions

• Task parallelism in languages such as C++, C#, Java and

Fortran90;

• General scripting languages like PHP Perl Python

• Domain specific environments like Matlab and Mathematica

• Functional Languages like MapReduce, F#

• HeNCE, AVS and Khoros from the past and CCA from DoE

• Web Service/Grid Workflow like Taverna, Kepler, InforSense

KDE, Pipeline Pilot (from SciTegic) and the LEAD environment built at Indiana University.

• Web solutions like Mash-ups and DSS

• Many scientific applications use MPI for the coarse grain

composition as well as fine grain parallelism but this doesn’t seem elegant

• The new languages from Darpa’s HPCS program support task

15

Mashups v Workflow?

•

Mashup Tools are reviewed at

http://blogs.zdnet.com/Hinchcliffe/?p=63

•

Workflow Tools are reviewed by Gannon and Fox

h ttp://grids.ucs.indiana.edu/ptliupages/publications/Workflow-overview.pdf

•

Both include

scripting

in PHP,

Python, sh etc. as

both implement

distributed

programming at level

of services

•

Mashups

use all

types of service

interfaces and

perhaps do not have

the potential

robustness

(security)

of Grid service

approach

•

Mashups typically

“Service Aggregation” in

SALSA

•

Kernels and Composition must be supported both

inside chips

(the multicore problem) and

between

machines

in clusters (the traditional parallel computing

problem) or Grids.

•

The scalable parallelism (kernel) problem is typically

only interesting on true parallel computers as the

algorithms require low communication latency.

•

However

composition is similar in both parallel and

distributed scenarios

and it seems useful to allow the

use of Grid and Web composition tools for the parallel

problem.

−

This should allow parallel computing to exploit large

investment in service programming environments

•

Thus in SALSA we express parallel kernels not as

traditional libraries but as (some variant of) services so

they can be used by non expert programmers

•

For

parallelism expressed in CCR

,

DSS

represents the

Parallel Programming 2.0

•

Web 2.0 Mashups

will (by definition the largest

market) drive

composition tools

for Grid, web and

parallel programming

•

Parallel Programming 2.0

will build on Mashup

tools like Yahoo Pipes and Microsoft Popfly

CICC Chemical Informatics and Cyberinfrastructure

Collaboratory Web Service Infrastructure

Portal Services

RSS Feeds User Profiles

Collaboration as in Sakai

Core Grid Services

Service Registry

Job Submission and Management

Local Clusters

IU Big Red, TeraGrid, Open Science Grid

Varuna.net

Quantum Chemistry

OSCAR Document Analysis InChI Generation/Search

Computational Chemistry (Gamess, Jaguar etc.)

Clustering Data

n

Cheminformatics

was tested successfully with small datasets and

compared to commercial tools

n

Cluster on properties of chemicals from high throughput

screening results to chemical properties (structure, molecular

weight etc.)

n

Applying to

PubChem

(and commercial databases) that have

6-20 million compounds

• Comparing traditional fingerprint (binary properties) with real-valued

properties

n

GIS

uses publicly available Census data; in particular the 2000

Census aggregated in 200,000 Census Blocks covering Indiana

• 100MB of data

n

Initial clustering done on simple attributes given in this data

n

Working with POLIS Center at Indianapolis on clustering of

SAVI (

Social Assets and Vulnerabilities Indicators

) attributes at

http://www.savi.org) for community and decision makers

Where are we?

n

We have deterministically annealed

clustering running well

on

8-core (2-processor quad 8-core) Intel systems using C# and

Microsoft Robotics Studio

CCR/DSS

n

Could also run on

multicore-based parallel machines

but didn’t

do this (is there a large Windows quad core cluster on

TeraGrid?)

• This would also be efficient on large problems

n

Applied to

Geographical Information Systems

(GIS) and census

data

• Could be an interesting application on future broadly deployed PC’s • Visualize nicely on Google Maps (and presumably Microsoft Virtual Earth)

n

Applied to several

Cheminformatics problems

and have parallel

efficiency but

visualization harder

as in 150-1024 (or more)

dimensions

n

Will develop a family of such

parallel annealing data-mining

tools

where basic approach known for

• Clustering

21

Microsoft CCR

•

Supports exchange of messages between threads using

named

ports

•

FromHandler:

Spawn threads without reading ports

•

Receive:

Each handler reads one item from a single port

•

MultipleItemReceive:

Each handler reads a prescribed number of

items of a given type from a given port. Note items in a port can

be general structures but all must have same type.

•

MultiplePortReceive:

Each handler reads a one item of a given

type from multiple ports.

•

JoinedReceive:

Each handler reads one item from each of two

ports. The items can be of different type.

•

Choice:

Execute a choice of two or more port-handler pairings

•

Interleave:

Consists of a set of arbiters (port -- handler pairs) of 3

types that are Concurrent, Exclusive or Teardown (called at end

for clean up). Concurrent arbiters are run concurrently but

exclusive handlers are

Preliminary Results

•

Parallel Deterministic Annealing Clustering

in

C# with

speed-up of 7

on Intel 2 quadcore

systems

•

Analysis of performance of

Java, C, C# in

MPI

and dynamic threading with XP, Vista,

Windows Server, Fedora, Redhat

on

Intel/AMD systems

•

Study of

cache effects

coming with MPI

thread-based parallelism

Parallel Multicor

Deterministic Annealing

Clustering

Parallel Overhea on 8 Threads Intel 8b

Speedup = 8/(1+Overhead)

10000/(Grain Size n = points per core) Overhead = Constant1 + Constant2/n

Constant1 = 0.05 to 0.1 (Client Windows) due to threa runtime fluctuations

10 Clusters

Renters Total

Asian

Hispanic

Renters

IUB Purdue

10 Clusters

Total

Asian

Hispanic

Renters

Parallel Multicore

Deterministic Annealing

Clustering

“Constant1”

Increasing number of clusters decreases communication/memory bandwidth overheads

Parallel Overhead for large (2M points) Indiana Census clusterin on 8 Threads Intel 8

Parallel Multicore

Deterministic Annealing

Clustering

“Constant1”

Increasing number of clusters decreases communication/memory bandwidth overheads

Parallel Overhead for subset of PubChem clustering on 8 Threads (Intel 8b

The fluctuating overhead is reduced to 2% (as bits not doubles

Intel 8-core C# with 80 Clusters: Vista Run

Time Fluctuations for Clustering Kernel

• 2 Quadcore Processors

• This is average of standard deviation of run time of the 8 threads between messaging synchronization points

Intel 8 core with 80 Clusters: Redhat Run

Time Fluctuations for Clustering Kernel

•

This is average of standard deviation of run time

of the 8 threads between messaging

synchronization points

25.8

4 Thread

CCR

XP Intel4(4 core 2.8 Ghz)

16.3 4 Thread CCR XP 39.3 4 Process MPICH2 99.4 4 Process mpiJava 152 4 Process MPJE Redhat 185 4 Process MPJE XP AMD4

(4 core 2.19 Ghz)

20.2 8 Thread CCR (C#) Vista 100 8 Process mpiJava Fedora 142 8 Process MPJE Fedora 170 8 Process MPJE Vista Intel8b

(8 core 2.66 Ghz)

64.2 8 Process MPICH2 111 8 Process mpiJava 157 8 Process MPJE Fedora Intel8c:gf20

(8 core 2.33 Ghz)

4.21 8 Process Nemesis 39.3 8 Process MPICH2: Fast 40.0 8 Process MPICH2 (C) 181 8 Process MPJE (Java) Redhat Intel8c:gf12

(8 core 2.33 Ghz) (in 2 chips)

MPI Exchange Latency Parallelism

Grains Runtime

OS Machine

CCR Overhead for a computation of

23.76 µs between messaging

Rende

vous

20.16

18.78

13.3

11.22

6.94

Exchange

35.62

31.86

14.16

11.64

7.4

Exchange As

Two Shifts

11.74

10.86

5.86

6.42

4.46

Shift

7.18

6.82

5.78

4.52

3.96

2.48

Pipeline

MPI

19.44

14.32

6.84

5.9

4.94

Two Shifts

5.14

5.26

3.38

3.2

2.42

Shift

5.06

4.5

2.94

3

2.44

1.58

Pipeline

Spawned

8

7

4

3

2

1

(μs)

Cache Line Interference

•

Early implementations of our clustering algorithm

showed large fluctuations due to the cache line

interference effect discussed here and on next slide

in a simple case

•

We have one thread on each core each calculating a

sum of same complexity storing result in a common

array A with different cores using different array

locations

•

Thread i stores sum in A(i) is separation 1 – no

variable access interference but cache line

interference

•

Thread i stores sum in A(X*i) is separation X

•

Serious degradation if X < 8 (64 bytes) with Windows

– Note A is a double (8 bytes)

Cache Line Interference

• Note measurements at a separation X of 8 (and values between 8 and 1024 not shown)

are essentially identical

• Measurements at 7 (not shown) are higher than that at 8 (except for Red Hat which shows essentially no enhancement at X<8)

• If effects due to co-location of thread variables in a 64 byte cache line, the array must be aligned with cache boundaries

DSS Section

•

We view system as a collection of

services – in this case

–

One to supply data

–

One to run parallel clustering

–

One to visualize results – in this by

spawning a Google maps browser

–

Note we are clustering Indiana census data

37

Timing of HP Opteron Multicore as a function of number of simultaneous two-way service messages processed (November 2006 DSS Release)

Inter-Service Communication

n

Note that we are

not

assuming a

uniform

implementation of service composition

even if user sees

same interface for multicore and a Grid

•

Good service composition inside a multicore chip can require

highly optimized communication mechanisms between the

services that

minimize memory bandwidth

use.

•

Between systems interoperability could motivate very

different mechanisms to integrate services.

•

Need both

MPI/CCR level

and

Service/DSS level

communication optimization

n

Note bandwidth and latency requirements reduce as

one increases the grain size of services

•

Suggests the

smaller services inside closely coupled cores

and

Inside the SALSA Services

n We generalize the well known CSP (Communicating Sequential

Processes) of Hoare to describe the low level approaches to fine grain

parallelism as “Linked Sequential Activities” in SALSA.

n We use term “activities” in SALSA to allow one to build services from

either threads, processes (usual MPI choice) or even just other

services.

n We choose term “linkage” in SALSA to denote the different ways of

synchronizing the parallel activities that may involve shared memory rather than some form of messaging or communication.

n There are several engineering and research issues for SALSA

• There is the critical communication optimization problem area for

communication inside chips, clusters and Grids.

• We need to discuss what we mean by services

• The requirements of multi-language support

n Further it seems useful to re-examine MPI and define a simpler model

that naturally supports threads or processes and the full set of communication patterns needed in SALSA (including dynamic threads).