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The 2018 GaN Power Electronics Roadmap

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Academic year: 2019

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Figure 3. (a) Large-area (100 mm wafer) epitaxial lift-off of GaN-release of a GaN-based device using dry etching of Nbbased epitaxial device layers achieved using band-gap selective photoelectrochemical wet etching of an InGaN [17]; (b) single-die 2N with
Figure 4. (a) Measured currentGaN vertical PN junction diodes on prime bulk GaN substrate and on a reclaimed substrate (i.e
Figure 5. Power systems roadmap at LETI. An SOC (system on chip) route towards monolithic solutions is important for miniaturization for low and mid power solutions
Figure 7. (a) Schematic cross-section of the typical epitaxial layer structure used for the manufacture of GaN-on-Si HEMTs
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Outline

Potential of polarisation super junction technology in gallium nitride Technological challenges in next-generation GaN-based power integrated circuits GaN CMOS: fact or iction? Assessing the limits of performance of p-type devices in GaN Potential of GaN integrated cascode transistors Converter topologies in GaN Fast switching with GaN and dynamic on-resist ance from application view-point

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