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Fault-tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs

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Academic year: 2019

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Figure

Fig. 1: Basic unit for fault-tolerant learning mediated byan astrocyte: Neurons N1, N2 and N3 resides in layer 1 andN4 resides in layer 2 of the SANN
Fig. 2: (A) Firing rate of N4 under fault free condition:All synapses between neurons in layer 1 and layer 2 arefault free enabling 8 parallel delayed paths between eachconnected neuron
Fig. 3: (A) Firing rate ofdifferent percentagefiring rate of N4 under different faulty conditions: Synapses between neurons in layer 1 and layer 2 are inducedfaults gradually (1-7 under neuron N1 specifies the point in which each synapses between N1 and N4 i
TABLE I: Hardware Overhead for the basic unit(Figure 1)implemented on the FPGA
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