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Compressively strained, buried channel $Si {0 7}$Ge$ {0 3}$ p MOSFETs fabricated on SiGe virtual substrates using a 0 25 µm CMOS process

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Figure

Fig. 1.The drain-current as a function of source-drain voltage for gateoverdrive voltages of 0.5, 1.5 and 2.5 V
Fig. 2.The subthreshold plots for the Si control, strained-Si on Si0.8Geand buried channel devices
Fig. 4.The drain-current as a function of source-drain voltage for gateoverdrive voltages of 0.5, 1.5 and 2.5 V
Fig. 6.The drain induced barrier lowering (DIBL) as a function of effectivechannel length for 5 µm wide devices.

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