1.2.4 Post_SequentialLogicDesign (1).pptx

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Sequential Logic

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Sequential Logic

2

This presentation will

• Introduce the basics of combinational and sequential logic.

• Present the logic symbol and function table for the “D” flip-flop.

• Review the design for a simple sequential logic circuit.

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Combinational & Sequential Logic

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Combinational Logic Gates

Inputs .. Outputs

.

. . .

Combinational Logic Gates

. .

Inputs Outputs

Memory Elements (Flip-Flops)

. .

Clock

Combinational Logic

Sequential Logic

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The “D” Flip-Flop

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Inputs Outputs

Preset Clear Clock Data-In

1 1  1 1 0 : Rising Edge of Clock 1 1  0 0 1 : Rising Edge of Clock

1 1 0 1 The output will stay the same.

0 1 X X 1 0

1 0 X X 0 1

0 0 X X 1 1 ILLEGAL CONDITION Q

Preset

Data-In Clock

Clear

Q Q

0

Q

0

Q

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Sequential Logic

• _{The “D” flip-flop is just one of several types of}

flip-flops that can be used to implement sequential logic designs.

• _{This presentation will look at the}_{Divide-by-Two}

circuit.

• _{This sample flip-flop application can be}

implemented with “D” flip-flops. Unit 3 of this course will spend a significant amount of time exploring other flip-flops and their applications.

• _{The purpose of this introduction is to provide a}

basis of understanding for the sequential logic

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Divide-by-Two Circuit: 1

st

Clock

6 Pulse-In

Pulse-Out

Pulse-In Pulse-Out Preset = 1

Clear = 1

Preset = 1 Clear = 1

Logic ‘0’ Logic ‘1’

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Divide-by-Two Circuit: 2

nd

Clock

7 Pulse-In

Pulse-Out

Clear = 1

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Divide-by-Two Circuit: 3

rd

Clock

8 Pulse-In

Pulse-Out

Clear = 1

The 3rd_{pulse is a}

repeat of the 1st_{, the}

4th_{will be a repeat of}

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Divide-by-Two Circuit

Period & Frequency - Overview

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Preset Pulse-In

Clear Pulse-Out

Preset

Pulse-In

Clear

Pulse-Out

The period of Pulse-Out is twice the period of Pulse-In.

Since the period is twice, the frequency is divided in half.

Thus, this is a

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Divide-by-Two Circuit

Period & Frequency – The Numbers

10 Preset Pulse-In Clear Pulse-Out Pulse-Out Pulse-In T₁ T₂ frequency) the (half : ƒ ƒ Out -Pulse of Frequency : T ƒ In -Pulse of Frequency : T ƒ period) the (twice : T T Out -Pulse of Period : T In -Pulse of Period : T 2 2 2 1 1 2 1 2 2 1 1 1 2 1     

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Divide-by-Two Circuit

Preset & Clear

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Preset Pulse-In

Clear Pulse-Out

Preset

Pulse-In

Clear

Pulse-Out

CLEAR HOLDS THE OUTPUT

PRESET HOLDS THE OUTPUT HIGH

Preset & Clear are active low signals.

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Sequential Logic Design Example

The following is a review of the design and operation of a sequential logic circuit using “D” flip-flops. This design is a simple two-bit binary counter that counts from zero

(0₁₀=00₂) to three (3₁₀=11₂) and then repeats.

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Design Example: Circuit Design

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Design Example: Functional Test

(1 of 3)

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Clock-In B

A B IS HALF THE

FREQUENCY OF

CLOCK-IN.

THE FIRST FLIP-FLOP IS CLOCKED BY CLOCK-IN.

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Design Example: Functional Test

(2 of 3)

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Clock-In B A

A is half the frequency

of B.

Note: A toggles on the

falling edge of B,

which is the rising edge of .

The second flip-flop is clocked by the of the first flip-flop.

Q

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Design Example: Functional Test

(3 of 3)

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Clock-In B A

“0” 0 0

“1” 0 1

“2” 1 0

“3” 1 1

“0” 0 0

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Design Example: IC Component View

17 3

2

1 4

5

6 11 12

13 10

9 8