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A Thyristor Only Input ESD Protection Scheme for CMOS RF ICs

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Figure

Figure 7. Protection scheme (1) utilizing a thyristor device.
Figure 10. Main discharge paths for each test mode in the protection scheme (2).
Figure 11. Equivalent circuit of an input-pin HBM test situation.
Figure 14. Variations of the voltages developed on Cngate(2).and Cpgate in a PS mode when using the protection circuit
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