Differential Amplifier Offset. Causes of dc voltage and current offset Modeling dc offset R C

ESE319 Introduction to Microelectronics

Differential Amplifier Offset

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Causes of dc voltage and current offset

Modeling dc offset

R

mismatch

I

mismatch

β mismatch

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dc offsets in differential amplifiers due to component

mismatch can be modeled as

differential

phenomena

ESE319 Introduction to Microelectronics

1. Let the ac sources be zero, i.e. the bases of matched Q1 & Q2 are connected to ground.

2. To further simplify, let there be no external base R_B and emitter resistors R_E.

3. Let the mismatch be in R_C where R_C1 ≠ R_C2.

I I_C1=IC2=  1 I 2 = I 2 If V_Odm V_{Odm=0⇒ RC1} I_C1=RC2 I_C2 V _{Odm=V C2−V C1=RC1} I_C1−RC2 I_C2

Since Q1=Q2 and I is fixed, currents are matched i.e.

V_EE

I_C1=IC2= I

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Assume matched currents:

I_C1=IC2= I

2

R_C1≠RC2

Split the mismatch between both

collector resistors, and decompose into common and differential components:

R_C= RC2RC1

2

 R_C=R_C2−R_C1

(common)

(differential - mismatch)

Solving for R_C1 & R_C2:

R_C2=R_C RC 2 =RC1 1 2  R_C R_C  R_C1=R_C− RC 2 =RC1− 1 2  R_C R_C  Let: I 2 I 2 s.t. R_C2RC1 I V_Odm vid/2 −vid/2 V_EE v_ic

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2  RC output offset voltage

I 2 I 2 random variable (rv) I V_Odm R_C1≠RC2 V_EE

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V _Odm= I

2  RC

Collector-collector voltage due to resistor mismatch: V _OS≡V Odm A_vdm  R_C V_OS is highly variable, rv & can be + or -V_EE V_Odm I 2 I 2 I I 2 I 2 I -V_OS 0 V V_EE V_EE

Define the input offset voltage

as that input voltage that will cancel

V_Odm. If the amplifier differential gain is A_vdm:

Input offset voltage is the output offset voltage referred to the input due to

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Input referred offset due to ΔR_C mismatch: where A_vdm=gm R_C random variable V_EE V _Odm= I 2  RC I 2 I 2 I -V_OS 0 V

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Offset Voltage From Transistor Mismatch

V _{Odm=0⇒ RC1} I_C1=RC2 I_C2

Perfect balance requires:

Previous case considered R_C1 ≠ R_C2

& Q1 = Q2 => I_C1 = I_C2.

Consider now Q1 ≠ Q2 => I_C1 ≠ I_C2. ASSUME: 1. R_C1 = R_C2 = R_C

2. V_BE1 = V_BE2 3. V_T1=V_T2

Only difference is in the saturation currents of the transistors, i.e.

I _S1≠IS2 + -V_Odm I V_EE R_C R_C

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Again using common and differential

mode concepts:

I _S= IS2I S1

2

 I S=I S2−IS1

The two transistor saturation currents are: I _S2=I _S I S 2 I_S1=I _S− IS 2 + -I −vid/2 vid/2 v_ic V_EE V_Odm

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ESE319 Introduction to Microelectronics

The parallel current sources are illustrated in the schematic.

I_Cdm/2

I_Cdm/2

Large signal Model:

I_SeVBE/VT  I_S 2 e V_BE/VT I_SeVBE/VT − IS 2 e V_BE/ VT Vee I_C1 I_C2 I_C2≈

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ESE319 Introduction to Microelectronics

Note: differential I_C components

cause current flow in opposite directions through the R_C's

resulting in an offset voltage. The

common I_C components cause no offset voltage.

V _Odm=RC I_C2−RC I_C1≈ I

2

 IS

ESE319 Introduction to Microelectronics

ESE319 Introduction to Microelectronics

Offset Voltage Summary

1. We considered two sources of offset voltage: a. Unbalanced collector resistors

b. Unbalanced saturation currents

i. Due to mismatched transistor geometries 2. We ignored base or emitter circuit unbalance

3. Since the relationship between resistor and current unbalances are random and assumed independent, we combine their effect as an rms quantity: V _OSrms=

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ESE319 Introduction to Microelectronics

Average & Offset Base (input) Bias Currents

Consider the case where the base currents differ I_B1 ≠ I_B2.

Since I_B1 & I_B2 are related to bias current I, their mismatch may be due to β₁ ≠ β₂.

Let's represent β₁ & β₂ in terms of differential

& common components:

1=   2 2=−  2 I_B1 IB2 I_E1=I 2 IE2= I 2 vid/2 −vid/2 v_i−cm V_EE

ESE319 Introduction to Microelectronics

Using this notation, the two base currents are:

1

1_x =1−xx

2

−x3...≈1−x

For x << 1 we can expand the fraction as the series:

where x≈ ± _2 nonlinear f(Δβ) I _B2≈ I 2 1 2 = ₂I 1 −₂ = ₂I 1  1 1₋  2_ 

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I _B= I B1I B2 2 = I 2_ I_{OS ≡}

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The base or input offset current can also be written as:

(input offset current)

1≈

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DC Offset Voltage & Current Summary

1. DC offset voltage and current occur due to mismatches in the BJT differential amplifier external resistors and transistor parameters (I_s and β).

2. These mismatches are imperfections that are inherent to all differ-ential amplifiers and their applications (e.g. op amps).

3. DC offset voltage and current are statistical quantities, i.e. no two differential amplifiers will have the same offset voltage and current. 4. MOS differential amplifiers have zero input offset current.