EE 330 Lecture 8. Design Rules. IC Fabrication Technology Part 1

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EE 330 Lecture 8

Design Rules

IC Fabrication Technology Part 1

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Technology Files

• Provide Information About Process

– Process Flow (Fabrication Technology) – Model Parameters

– Design Rules

• Serve as Interface Between Design Engineer and Process Engineer

• Insist on getting information that is deemed important for a design

– Limited information available in academia

– Foundries often sensitive to who gets access to information – Customer success and satisfaction is critical to foundries

Review from Last Time

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Design Rules and Layout –

consider transistors

Drain

Gate

Source

Drain

Gate

Source Bulk

p-active n-active

Poly 1 Metal 1

n-well contact

D G S

L W

Layer Map

D G S

B

• Bulk connection needed

• Single bulk connection can often be used for several (many) transistors

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Design Rules and Layout – consider transistors

D G S

D G S B

Drain

Gate

Source

p-active n-active

Poly 1 Metal 1

n-well contact

Layer Map

• Bulk connection needed

• Single bulk connection can often be used for several (many) transistors is they share the same well

Drain

Gate

Source Bulk

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Design Rules

• Design rules can be given in absolute dimensions for every rule

• Design rules can be parameterized and given relative to a parameter

– Makes movement from one process to another more convenient

– Easier for designer to remember – Some penalty in area efficiency

– Often termed λ-based design rules

– Typically λ is ½ the minimum feature size in a process Review from Last Time

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Design Rules

• See www.MOSIS.org for design rules

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Design Rules

• See www.MOSIS.org for design rules

• Some of these files are on class WEB site

– SCMOS Rules Updated Sept 2005.pdf

– Mosis Rules Pictorial.pdf

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Technology Files

• Design Rules

• Process Flow (Fabrication Technology)

• Model Parameters

(will discuss in substantially more detail after device operation and more advanced models are introduced)

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IC Fabrication Technology

See Chapter 3 and a little of Chapter 1 of WH

or Chapter 2 GAS for details

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Mask Fabrication

Epitaxy

Photoresist

Etch

Strip

Planarization Deposit or Implant

Grow or Apply

W afer Probe

Die Attach Wafer Dicing

Wire Attach (bonding)

Package

Test Wafer Fabrication

Ship

Front EndBack End

Generic

Process

Flow

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IC Fabrication Technology

• Crystal Preparation

• Masking

• Photolithographic Process

• Deposition

• Etching

• Diffusion

• Oxidation

• Epitaxy

• Polysilicon

• Contacts, Interconnect and Metalization

• Planarization

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MOS Transistor

n-type n+-type

p-type p+-type

SiO2 (insulator)

POLY (conductor)

Drain

Gate

Source

Review

A’

A

Gate Drain

Source Bulk

n-channel MOSFET

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MOS Transistor

Drain

Gate

Source

n-type n+-type

p-type p+-type

SiO2 (insulator)

POLY (conductor)

Review

Gate Drain

Source Bulk

p-channel MOSFET A A’

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MOS Transistor

Gate Drain

Source Bulk

n-channel MOSFET

Gate Drain

Source Bulk

n-channel MOSFET

n-channel MOS transistor in Bulk CMOS n-well

process with bulk contact

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MOS Transistor

Gate Drain

Source Bulk

p-channel MOSFET

Gate Drain

Source Bulk

p-channel MOSFET

p-channel MOS transistor in Bulk CMOS n-well process with bulk contact and well (tub)

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MOS Transistor

Gate Drain

Source Bulk

n-channel MOSFET

• Single-crystalline silicon

− Serves as physical support member

− Lightly doped

− Vertical dimensions are not linearly depicted

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MOS Transistor

Gate Drain

Source Bulk

n-channel MOSFET

− Lightly doped

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MOS Transistor

Gate Drain

Source Bulk

n-channel MOSFET

− Lightly doped (p-doping in the 10¹⁵/cm³ range, silicon in the 2.2x10²²/cm³ range)

Thin insulator

(10A to 50A range)

Conductor (usually polysilicon)

More heavily doped (10¹⁷/cm³ range)

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MOS Transistor

Gate Drain

Source Bulk

p-channel MOSFET

Lightly-doped n-type (5x10¹⁶/cm³ range)

More heavily-doped p-type (10¹⁸/cm³ range)

Lightly doped p-type (10¹⁵/cm³ range)

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Crystal Preparation

• Large crystal is grown (pulled)

– 12 inches in diameter and 1 to 2 m long – Sliced to 250u to 500u thick

• Prefer to be much thinner but thickness needed for mechanical integrity

– 4 to 8 cm/hr pull rate – T=1430 ^oC

• Crystal is sliced to form wafers

• Cost for 12” wafer around $200

• 5 companies provide 90% of worlds wafers

• Somewhere around 400,000 12in wafers/month

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Crystal Preparation

12in

1 to 2 m

250u tp 500u

Lightly-doped silicon

Excellent crystalline structure

To go to 450mm (18in) by 2010 (ITRS 2007 FEP page 3)

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Crystal Preparation

From www.infras.com

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Crystal Preparation

Source: WEB

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Crystal Preparation

Source: WEB

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Crystal Preparation

Source: WEB

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Crystal Preparation

Source: WEB

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Crystal Preparation

Source: WEB

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IC Fabrication Technology

• Masking

• Deposition

• Etching

• Diffusion

• Oxidation

• Epitaxy

• Polysilicon

• Planarization

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Masking

• Use masks or reticles to define features on a wafer

– Masks same size as wafer – Reticles used for projection

– Reticle much smaller (but often termed mask) – Reticles often of quartz with chrome

– Quality of reticle throughout life of use is critical – Single IC may require 20 or more reticles

– Cost of “mask set” now exceeds $1million for state of the art processes – Average usage 500 to 1500 times

– Mask costs exceeding 50% of total fabrication costs in sub 100nm processes

– Serve same purpose as a negative (or positive) in a photographic process – Usually use 4X optical reduction - exposure area approx. 860mm²

(now through 2022 ITRS 2007 litho, Table LITH3a)

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Masking

Lens

Reticle

Wafer

Photosensitized Emulsion

Die Site

Step and Repeat (stepper) used to image across wafer

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Masking

Exposure through reticle

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Masking

Mask Features

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Masking

Mask Features Intentionally Distorted to Compensated For Wavelength Limitations in Small Features

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IC Fabrication Technology

• Masking

• Deposition

• Etching

• Diffusion

• Oxidation

• Epitaxy

• Polysilicon

• Planarization

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Photolithographic Process

• Photoresist

– Viscous Liquid

– Uniform Application Critical (spinner) – Baked to harden

– Approx 1u thick – Non-Selective – Types

• Negative – unexposed material removed when developed

• Positive-exposed material removed when developed

• Thickness about 450nm in 90nm process (ITRS 2007 Litho)

• Exposure

– Projection through reticle with stepper (scanners becoming popular)

– Alignment is critical !!

– E-Bean Exposures

• Eliminate need fro reticle

• Capacity very small

Stepper: Optics fixed, wafer steps in fixed increments

Scanner: Wafer steps in fixed increments and during exposure both optics and wafer are moved to increase effective reticle size

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Steppers

Stepper costs in the $10M range with thru-put of around 100 wafers/hour

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Steppers

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Mask Alignment

Correctly Aligned

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Mask Alignment

Alignment Errors

ΔX

ΔY

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Mask Alignment

Other alignment marks (http://www.mems-exchange.org/users/masks/intro-equipment.html)

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IC Fabrication Technology

• Masking

• Deposition

• Implantation

• Etching

• Diffusion

• Oxidation

• Epitaxy

• Polysilicon

• Planarization

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Deposition

• Application of something to the surface of the silicon wafer or substrate

– Layers 15A to 20u thick

• Methods

– Physical Vapor Deposition (nonselective)

• Evaporation/Condensation

• Sputtering (better host integrity)

– Chemical Vapor Deposition (nonselective)

• Reaction of 2 or more gases with solid precipitate

• Reduction by heating creates solid precipitate (pyrolytic)

– Screening (selective)

• For thick films

• Low Tech, not widely used today

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Deposition

Example: Chemical Vapor Deposition

Silane (SiH₄) is a gas (toxic and spontaneously combustible in air) at room temperature but breaks down into Si and H₂ above 400^oC so can be used to deposit Si.

i 4 i 2

SH  S + 2H

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IC Fabrication Technology

• Masking

• Deposition

• Implantation

• Etching

• Diffusion

• Oxidation

• Epitaxy

• Polysilicon

• Planarization

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Implantation

Application of impurities into the surface of the silicon wafer or substrate

- Individual atoms are first ionized (so they can be accelerated) - Impinge on the surface and burry themselves into the upper

layers

- Often very shallow but with high enough energy can go modestly deep

- Causes damage to target on impact - Annealing heals most of the damage

- Very precise control of impurity numbers is possible - Very high energy required

- High-end implanters considered key technology for national security

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From http://www.casetechnology.com/implanter

Ion Implantation Process

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Ion Implanter

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IC Fabrication Technology

• Masking

• Deposition

• Implantation

• Etching

• Diffusion

• Oxidation

• Epitaxy

• Polysilicon

• Planarization

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Implantation

Application of impurities into the surface of the silicon wafer or substrate

- Individual atoms are first ionized (so they can be accelerated) - Impinge on the surface and burry themselves into the upper

layers

- Often very shallow but with high enough energy can go modestly deep

- Causes damage to target on impact - Annealing heals most of the damage

- Very precise control of impurity numbers is possible - Very high energy required

- High-end implanters considered key technology for national security

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Ion Implanter

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IC Fabrication Technology

• Masking

• Deposition

• Implantation

• Etching

• Diffusion

• Oxidation

• Epitaxy

• Polysilicon

• Planarization

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Etching

Selective Removal of Unwanted Materials

• Wet Etch

– Inexpensive but under-cutting a problem

• Dry Etch

– Often termed ion etch or plasma etch

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Etching

Desired Physical Features

Photoresist

SiO

₂

p^-Silicon

Note: Vertical Dimensions Generally Orders of Magnitude Smaller Than Lateral Dimensions so Different Vertical and Lateral Scales Will be Used In This Discussion

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Etching

Desired Physical Features

Photoresist

SiO

₂

p^-Silicon

Dry Etch can provide very well-defined and nearly vertical edges (relative to photoresist paterning)

Dry etch (anisotropic)

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Etching (limited by photolitghographic process)

Photoresist

SiO

₂

p^-Silicon

Dry etch (anisotropic)

Consider neg photoresist

Over Exposed

Correctly Developed Over Developed Under Developed

Under Exposed

Correctly Developed Over Developed Under Developed

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Lateral Relative to Vertical Dimensions

Still Not to Scale

Photoresist

SiO

₂

p^-Silicon

For Example, the wafer thickness is around 250u and the gate oxide is around 50A (5E-3u) and diffusion depths are around λ/5

Gate

Drain Source

Bulk

n-channel MOSFET

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Etching

SiO

₂

Photoresist

Undercutting (wet etch)

Desired Edges of SiO₂ from Mask

Isotropic

Feature Degradation

Edge Movement Due to Over Etch, Over

Exposure, or Over- Development

p^-Silicon

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Etching

SiO

₂

Undercutting (wet etch)

Desired Edges of

SiO₂ from Mask Edge Movement Due to Over Etch, Over

Exposure, or Over- Development

SiO₂ after photoresist removal p^-Silicon

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IC Fabrication Technology

• Masking

• Deposition

• Ion Implantation

• Etching

• Diffusion

• Oxidation

• Epitaxy

• Polysilicon

• Planarization

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Diffusion

• Controlled Migration of Impurities

– Time and Temperature Dependent

– Both vertical and lateral diffusion occurs

– Crystal orientation affects diffusion rates in lateral and vertical dimensions – Materials Dependent

– Subsequent Movement

– Electrical Properties Highly Dependent upon Number and Distribution of Impurities

– Diffusion at 800^oC to 1200^oC

• Source of Impurities

– Deposition

– Ion Implantation

• Only a few A^odeep

• More accurate control of doping levels

• Fractures silicon crystaline structure during implant

• Annealing occurs during diffusion

• Types of Impurities

– n-type Arsenic, Antimony, Phosphorous – p-type Gallium, Aluminum, Boron

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Diffusion

Source of Impurities Deposited on Silicon Surface

Before Diffusion

After Diffusion

p^-Silicon p^-Silicon

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Diffusion

Source of Impurities Implanted in Silicon Surface

After Diffusion

p^-Silicon p^-Silicon

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Diffusion

Implant

After Diffusion Lateral Diffusion

p- Silicon

p- Silicon p^-Silicon p^-Silicon

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IC Fabrication Technology

• Masking

• Deposition

• Ion Implantation

• Etching

• Diffusion

• Oxidation

• Epitaxy

• Polysilicon

• Planarization

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Oxidation

• SiO₂ is widely used as an insulator

– Excellent insulator properties

• Used for gate dielectric

– Gate oxide layers very thin

• Used to separate devices by raising threshold voltage

– termed field oxide

– field oxide layers very thick

• Methods of Oxidation

– Thermal Growth (LOCOS)

• Consumes host silicon

• x units of SiO₂ consumes .47x units of Si

• Undercutting of photoresist

• Compromises planar surface for thick layers

• Excellent quality

– Chemical Vapor Deposition

• Needed to put SiO₂ on materials other than Si

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Oxidation

SiO

₂

Thermally Grown SiO

₂

- desired growth Photoresist

Patterned Edges X

0.47 X p^-Silicon

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Oxidation

SiO

₂

Thermally Grown SiO

₂

- actual growth Photoresist

Patterned Edges

Bird’s Beaking

p^-Silicon

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Oxidation

Thermally Grown SiO

₂

- actual growth

Patterned Edges Nonplanar

Surface

p^-Silicon

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