DESIGN OF SKALANSKY ADDER BASED HIGH PERFORMANCE SPEED EFFICIENT MULTIPLIERS

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DESIGN OF SKALANSKY ADDER BASED HIGH PERFORMANCE SPEED EFFICIENT MULTIPLIERS

P.Avinash

, J.Koteswara Rao

1

Pursuing M.tech,

Assistant Professor (ECE), Nalanda Institute of Engineering and Technology (NIET), Siddharth Nagar, Kantepudi Village, Sattenepalli Mandal, Guntur Dist.,A.P. (India)

ABSTRACT

Multipliers are used in RISC (Reduced instruction set computing), DSP(Digital signal Processors), graphics accelerators like so on. The total speed performance of any VLSI system can be depends on the speed performance of multiplier. In this paper we are designing two types of multipliers these are DADDA multiplier and WALLACE TREE multiplier. The proposed DADDA multiplier is designed with 24*24 bits and Wallace tree multiplier is designed for 64*64 bits. AT the final stage of addition we are using different adders to reduce the partial productsby using these proposed schemes the speed performance ofWallace tree multiplier can be increased by 33% and DADDA multiplier can be increased by 21% compare with the existed multiplier. The proposed multipliers can be designed with Verilog hardware description language and synthesisand simulation canbe implemented by XILINX ISE 13.2 software.

Keywords: Wallace Tree Multiplier, DADDA Multiplier, Carries Look Ahead Adder, Ripple Carry Adder, Half Adder, Full Adder.

I. INTRODUCTION

A huge number of different multiplier building designshave been proposed in the writing during recent decades.

The multiplier is one of key equipment hinders in the greater part of the advanced furthermore, superior frameworks, for example, computerizeddigital signal processors and microchips. With the late advances in innovation numerous researches have taken a shot at the configuration of progressively more sufficient multipliers. They go for advertising higher speed and low power utilization even while possessing reduced silicon area. This makes them good for different difficult and convenient VLSI circuit executions. However the certainty remains that the area and the speed are the two clashing execution imperatives. Consequently, advancing expanded speed dependably bring about bigger area. In this paper we arrive better exchange off between the two, by understanding an insignificantly expanded speed execution through a little ascent in the quantity of transistors. The new structural planning upgrades the speed execution of the generally recognized DADDA Tree Multiplier. The structural improvement is performed on the ordinary Wallace Tree Multiplier and DADDA Tree Multiplier in such a way the inactivity of the aggregate circuit decreases extensively. Both the Wallace tree multiplier also, DADDA tree multiplier fundamentally increases two unsignedwhole numbers. The routine Wallace tree multiplier and DADDA tree multiplier have comparable stages it includes an AND array

126 | P a g e for registering the fractional items, a carry save adder for including fractional items so got and a carry propagate adder in the last stage of expansion.

II. WALLCE TREE MULTIPLIER

The partial products are shaped by N² AND gates. For the arithmetic Wallace reduction technique, once the partial product cluster (N²bits) is collected, contiguous rows are gathered into non-covering gatherings of three.

Every gathering of threelines are diminished by (1) Applying a full adder to every segment that contains three bits. (2) Applying a half adder to every section that contains two bits. (3) Passing any single bit sections to the following stage without handling. This reduction strategy is connected to each progressive stage until just two rows remain. This procedure is outlined by the routine 8-bit by 8-bit Wallace multiplier as appeared in below figure. The reduction is performed in four stages. The third stage will require a (2N-1-S) wide adder, where s- number of stages in diminishment.

Fig:1Example 8 bit Wallace tree Multiplier

The reduction phase of the Wallace tree multiplier is finished by gathering the partial product item as full adder and half adder. The basic way of the Wallace tree multiplier is depicted in the fig. 2. In the routine 8 bit Wallace tree multiplier configuration more number of expansion operations is required. Utilizing carry save adder.Three fractional item terms can be a period to frame the carry and sum. The sum flag is utilized by the full adder of the following level. The carry signal is utilized by the adder included in the era of the following yield bit with a subsequent general delay corresponding to log 3/2 N, for N number of lines.

Partial Product Reduction

A Multiplier comprises of different phases of full adders, each higher stage signifies the aggregate deferral of the framework. In the to begin with and second phases of the Wallace structure the fractional item does not rely on some other qualities other than the inputs acquired from the AND array. Be that as it may, for the quick higher stages, the last value (PP3) relies on upon the complete estimation of past stage. This operation is rehashed for the continuous stages. Henceforth, the real reason for the delay is the spread of the complete from the past stage to the following stage. In below fig. arrow speak to the basic way of the circuit. In customary Wallace tree structure, the aggregate number of stages in the basic way sum up to 13 full adders. Every full

127 | P a g e adder represents an latency of 2. Hence the aggregate latency of the given structure is 26. The latency check gets included by one when considering AND exhibit and consequently the coming about latency is 27

Half Adder

Half adder is used for partial product reduction, which is used to add the two inputs a,b, and generates the two outputs sum and carry as shown in below.

Where S = A ^ B, C = A & B.

Fig:2 Half adder

FULL ADDER: FULL adder is used for partial product reduction, which is used to add the three inputs a,b,c and generates the two outputs sum and carry as shown in below.

Where S = A ^ B ^ Cin and Cout = A &B + B & C + C & A

Fig:3 Full adder

.

Fig:4 Partial product representation III. DADDA TREE MULTIPLIER

DADDA tree multiplier is comparative that the partial product generation stage, reduction stage and last addition stage as that of Wallace Multiplier just the propagation of sum and carry will be distinctive to get the parallel structure to increment the speed. While performing DADDA section compression procedure the fractional items are assembled considerably half adders and full adders. The created carry or sum by these adders is avoided to one on the other hand more stages not at all like in Wallace tree multiplier to get the parallel structure. This will enhance the speed of the multiplier. On the off chance that there is one and only incomplete

128 | P a g e item there is no need of denoting the carry as essential and making the full adder as active. Due to this parallel structure and utilization of half adders in the circuit(only full adders in Wallace tree multiplier) we are not just diminishing the quantity of exchanging squares we are getting plausibility of twin accuracy Multiplier in below Fig. clarifies the DADDA tree multiplier which is gathered by the half adders and full adders.

Fig:5 Example of 16 bit DADDA multiplier

In DADDA tree multiplier, the aggregate number of stages in the basic way sums to 11 full adders. Every full adder accounts for an latency of 2. In this manner the aggregate latency of the given structure is 22. The latency number gets included by one when considering AND exhibit and henceforth the subsequent latency is 23.

Proposed Implementation

The proposed multiplier will have the same number of decrease stages, for example, in Wallace tree multiplier and DADDA tree multiplier (creating fractional items by the utilization of AND cluster, Carry save adder for including incomplete items and just last expansion is supplanted in the proposed multiplier). At the last stage where an ordinary ripple adder is available in Wallace tree multiplier and DADDA tree multiplier. In our proposed multiplier which is supplanted by the Parallel prefix adder (sklansky tree viper) . Our proposed structural planning intends to decrease the general latency. This outcome in expanded in velocity by utilizing sklanskytree adder rather than ripple adder which diminishes latency extensively. The utilization of the sklansky adder in the last expansion in DADDA tree multiplier further results a lessened latency. There are six stages in the sklansky tree adder, for each stage expect it to be one latency. So the general latency for the sklansky adder is 6 rather than 14 (6 which is got from sklansky tree adder and 14 is really present in the multiplier because of ripple carry adder). Henceforth the proposed structure cuts down the total latency starts from 18 to 27. The proposed structure can be shown in below:

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Fig 6: Proposed structure

IV. SIMULATION RESULTS

This paper presents the design of two high speed multipliers those are DADDA and Wallace tree multipliers.

These are designed in Verilog hardware HDL. The design RTL diagram and verification can be synthesized by using XILINX ISE 13.2i software. The proposed system RTL diagram and synthesis results and simulation are shown in below figure.

1. RTL diagram of DADDA multiplier.

Fig:7 Top level RTL diagram

.

Fig: 8 Simulation Result for Dadda Multiplier

130 | P a g e 3. RTL diagram of Wallace tree multiplier

Fig:9 RTL diagram fortop Wallace tree diagram

Fig:10 Simulation result for Wallace tree V. CONCLUSION

In this paper we have designed the proposed 24*24 bit DADDA multiplier and 64*64 bit Wallace tree multipliers by using carry skip and sklansky adder are the basic modules. The proposed multipliers have high speed compare with the existed design. The proposed designs can be implemented by the Verilog hardware description language and design synthesis and simulation can be performed by XILINX ISE 13.2 simulator.The power increased in proposed architecture due to large number of gates compared to that the existing multiplier structures (Wallace tree multiplier and DADDA tree multiplier). Thus the result proved that the proposed architecture is more efficient in terms of the speed compared to the existing one with slight increase in power.

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AUTHOR DETAILS

P.AVINASH is pursuing M.tech from Nalanda Institute of Engineering and Technology.

He completed hisB.tech from Electronics and communication Engineering. His research of interest includes CMOS DIGITAL, Analog CMOS, VLSI design etc.

J.KOTESWARA RAO is working as assistant professor in Nalanda Institute of Engineering and Technology. He completed his post-graduation in VLSIand his area of interest includes Low power VLSI design, CMOS mixed, Digital system design