Logic Gates
Logic Gates
The term gate is used to describ
The term gate is used to describe a circuit that performe a circuit that performs a s a basic logibasic logic operatioc operation. n. All gatAll gateses hav
have e botboth h inpinputs and outputs and outputsuts. . ThThe e numnumber of ber of inpinputs can vary depenuts can vary dependinding on g on the gate inthe gate in question but there is generally only one output.
question but there is generally only one output. As
As didiscuscussessed d in in ununit it 1 1 ththerere e are are ththree ree prprimimary ary lologigic c gagatetes s frfrom om !h!hicich h by by vavaririououss combinations all other gates can be made.
combinations all other gates can be made. These are the "#T $ate %inverter& the These are the "#T $ate %inverter& the A"D $ateA"D $ate and the #'
and the #' $ate. $ate. This unit revisits these gThis unit revisits these gates and proceeds to inates and proceeds to introduce a number of troduce a number of other other gates.
gates.
NOT Gate (Inverter) NOT Gate (Inverter)
The "#T gate has a single inpu
The "#T gate has a single input and a single output. t and a single output. The gate very simply inverts the inpuThe gate very simply inverts the input.t. The symbol and truth table
The symbol and truth table for the "#T gate arfor the "#T gate are sho!n belo!.e sho!n belo!. Symbol Symbol #utput ( #utput ( nput A nput A
The circle on the symbol indicates that the output ( is the inverse %or complement& of the The circle on the symbol indicates that the output ( is the inverse %or complement& of the input A. input A. Truth Table Truth Table A A (( * * 11 1 1 ** The above table is +no!n
The above table is +no!n as a truth table. as a truth table. )n this table every possible combin)n this table every possible combination of inputation of input is !rit
is !ritten in ordten in order and the outer and the output is detput is determermined foined for each inpr each input. ut. ThThere areere are nn
,
, possible possible co
combmbininatiationons s in the in the cascase e of of an n-inan n-inpuput t gagatete. . )n othe)n other r !o!ordrds s ththerere e are t!o possare t!o possibiblele combinations in the case of a one-input gate four possible combinations of input in the case combinations in the case of a one-input gate four possible combinations of input in the case of a t!o-input gate etc..
of a t!o-input gate etc.. Boolean Expre
Boolean Expressionssion
A A ( ( == or verbally or verbally ( / A bar0 ( / A bar0 oole
oolean algebra is the mathematics of digital systean algebra is the mathematics of digital systems. ms. A lA letter designaetter designates a tes a variabvariable and ale and a bar over a letter designates the inverse %or complement& of the variable.
bar over a letter designates the inverse %or complement& of the variable. 2ore generally 2ore generally a bar a bar over a quantity designates the inverse %or complement& of that quantity.
over a quantity designates the inverse %or complement& of that quantity.
1 1
AND Gate AND Gate The A
The A"D gate has multiple inputs and a single output. "D gate has multiple inputs and a single output. The output of any The output of any A"D gate is 3)$3A"D gate is 3)$3 only !hen
only !hen all all of its inputs are 3)$3. of its inputs are 3)$3.
Symbol Symbol #utput ( #utput ( )nput A )nput A )nput 1 )nput 1
)n this case the output is 3)$3 %or logic level 1& only if the inputs A and are 3)$3 %or )n this case the output is 3)$3 %or logic level 1& only if the inputs A and are 3)$3 %or logic level 1&. Thus !e can
logic level 1&. Thus !e can !rite a table !rite a table defindefining all the ing all the possipossible states that might occur for ble states that might occur for this t!o input A"D gate.
this t!o input A"D gate. Truth Table Truth Table A A (( * * ** ** * * 11 ** 1 1 ** ** 1 1 11 11 Boolean Expre
Boolean Expressionssion
F = A F = A
..
B B or verbally or verbally ( / A and 0 ( / A and 0The A"D gate performs oolean 2ultiplication as illustrated in the timing diagram belo!. The A"D gate performs oolean 2ultiplication as illustrated in the timing diagram belo!. oolean multiplication follo!s the same rules as binary multiplication as discussed in unit ,. oolean multiplication follo!s the same rules as binary multiplication as discussed in unit ,. Timing Diagram
Timing Diagram
#UT4UT #UT4UT
Timing Diagram for an A"D Timing Diagram for an A"D gategate )"4UT A )"4UT A )"4UT 1 )"4UT 1 , ,
3-Input AND Gate 3-Input AND Gate
Symbol Symbol #utput ( #utput ( )nput A )nput A )nput 1 )nput 1 )nput 5 )nput 5 Truth Table Truth Table A 5 ( A 5 ( * * * * * * * * * * 1 * * * 1 * * 1 * * * 1 * * * 1 1 * * 1 1 * 1 * * * 1 * * * 1 * 1 * 1 * 1 * 1 1 * * 1 1 * * 1 1 1 1 1 1 1 1
As can be seen !hen !e have a three input A"D gate the same rule applies as did for the t!o As can be seen !hen !e have a three input A"D gate the same rule applies as did for the t!o input gate i.e. A66 the inputs must be 3)$3 if !e are to achieve a 3)$3 on the output. input gate i.e. A66 the inputs must be 3)$3 if !e are to achieve a 3)$3 on the output.
Boolean Expre Boolean Expressionssion
F = A
F = A
..
B B..
C C #r more commonly it is !ritten as#r more commonly it is !ritten as
F = ABC F = ABC
)n boolean e7pressions !hen variables are !ritten ne7t to each other !ith no symbol in )n boolean e7pressions !hen variables are !ritten ne7t to each other !ith no symbol in bet!een it is implicitly assumed that they are A
bet!een it is implicitly assumed that they are A"Ded."Ded.
8 8
O Gate O Gate
The #' gate can have t!o or m
The #' gate can have t!o or more inputs. ore inputs. The output of an #The output of an #' gate is 3)$3 !hen one or ' gate is 3)$3 !hen one or more of the inputs are 3)$3.
more of the inputs are 3)$3.
Symbol Symbol #utput ( #utput ( )nput A )nput A )nput 1 )nput 1 Truth Table Truth Table A A (( * * ** ** * * 11 11 1 1 ** 11 1 1 11 11 Boolean Expre
Boolean Expressionssion
F = A ! B F = A ! B #r verbally #r verbally ( / A or 0 ( / A or 0 The #'
The #' gatgate e perperforforms ms oooolean Adlean Additdition - ion - not to not to be be conconfusfused ed !it!ith h binbinary additary addition asion as discussed in unit ,. discussed in unit ,. Timing Diagram Timing Diagram #UT4UT #UT4UT )"4UT A )"4UT A )"4UT 1 )"4UT 1
Timing Diagram for an #' gate Timing Diagram for an #' gate
4 4
3-Input O Gate 3-Input O Gate
Symbol Symbol #utput ( #utput ( )nput 1 )nput 1 )nput 5 )nput 5 )nput A )nput A Truth Table Truth Table A 5 ( A 5 ( * * * * * * * * * * 1 1 * * 1 1 * 1 * 1 * 1 * 1 * 1 1 1 * 1 1 1 1 * * 1 1 * * 1 1 * 1 1 1 * 1 1 1 1 * 1 1 1 * 1 1 1 1 1 1 1 1 1
Again it can be seen from the table that the output is 6#9 only !hen all the inputs are 6#9. Again it can be seen from the table that the output is 6#9 only !hen all the inputs are 6#9.
Boolean Expre Boolean Expressionssion
F = A ! B ! C F = A ! B ! C
"o! that the
"o! that the three basic three basic gates have gates have been considered they been considered they can be ccan be combined to generate ombined to generate other other operations.
operations.
: :
NAND Gate NAND Gate This is a
This is a combination of the A"D gate and the "#T gate in combination of the A"D gate and the "#T gate in that order.that order. Symbol Symbol #utput ( #utput ( )nput A )nput A )nput 1 )nput 1 )nput A )nput A )nput 1 )nput 1 #utput #utput ((==A1A1 A1 A1 oth rep
oth representaresentations are equitions are equivalentvalent. . "ote that the bu"ote that the bubble0 %bble0 %oo& in the top symbol indicates& in the top symbol indicates the presence of
the presence of an inverter oan inverter on the on the output line. utput line. The top The top representation is more representation is more common. common. TheThe bottom representation indicates ho! a "A"D gate may be bro+en
bottom representation indicates ho! a "A"D gate may be bro+en do!n.do!n. Truth Table Truth Table A A (( * * ** 11 * * 11 11 1 1 ** 11 1 1 11 ** Boolean Expre
Boolean Expressionssion
B B A A F F == •• #r more
#r more commonlycommonly FF == ABAB
As can be seen from the table the inputs are A"Ded together and then "#Ted %inverted& to As can be seen from the table the inputs are A"Ded together and then "#Ted %inverted& to give the final outpu
give the final output. t. The timing diagram shoThe timing diagram sho!n belo! illustrates this.!n belo! illustrates this. Timing Diagram Timing Diagram #UT4UT #UT4UT )"4UT A )"4UT A )"4UT 1 )"4UT 1
Timing Diagram for a "A"D Timing Diagram for a "A"D gategate
; ;
NO Gate NO Gate
This is a combination of the #' gate and the "#T gate in that order. This is a combination of the #' gate and the "#T gate in that order. Symbol Symbol #utput 1 #utput ((==AA++1 )nput A )nput A )nput 1 )nput 1 A<1 A<1 #utput ( #utput ( )nput A )nput A )nput 1 )nput 1 oth rep
oth representaresentations are equitions are equivalentvalent. . "ote that the bu"ote that the bubble0 %bble0 %oo& in the top symbol indicates& in the top symbol indicates the presence of
the presence of an inverter oan inverter on the on the output line. utput line. The top The top representation is more representation is more common. common. TheThe bottom representation indicates ho! a "#' gate may be bro+en d
bottom representation indicates ho! a "#' gate may be bro+en do!n.o!n. Truth Table Truth Table A A (( * * ** 11 * * 11 ** 1 1 ** ** 1 1 11 ** Boolean Expre
Boolean Expressionssion
B B A A F F == ++
As can be seen from the table the inputs are #'ed together and then "#Ted %inverted& to As can be seen from the table the inputs are #'ed together and then "#Ted %inverted& to give the final outpu
give the final output. t. The timing diagram shoThe timing diagram sho!n belo! illustrates this.!n belo! illustrates this. Timing Diagram Timing Diagram #UT4UT #UT4UT )"4UT A )"4UT A )"4UT 1 )"4UT 1
Timing Diagram for a "#' gate Timing Diagram for a "#' gate
= =
Another gate !hich is made up of the A"D #' and "#T gates and !hich is commonly used Another gate !hich is made up of the A"D #' and "#T gates and !hich is commonly used is an >#' gate.
is an >#' gate. >#' gates connected to >#' gates connected to form an adder circuit allo! form an adder circuit allo! a computer to performa computer to perform add
additiition on subsubtractractiotion n mulmultiptiplicalicatiotion n and and divdivisiision on in in it?it?s s ArArithithmetmetic ic 6og6ogic ic UnUnit it %A6%A6U&.U&. Sho!n belo! is its basic layout.
Sho!n belo! is its basic layout. Logic Diagram
Logic Diagram )nput A )nput A
)nput 1
)nput 1 #utput#utput
B B A. A. .B .B A A F F== ++ A A B B B B A. A. .B .B A A
Again this is too large to be commonly used so it is summarised into a small logic symbol Again this is too large to be commonly used so it is summarised into a small logic symbol !hich is
!hich is sho!n belo!.sho!n belo!. Symbol Symbol #utput ( #utput ( )nput A )nput A )nput 1 )nput 1
The truth tab
The truth table for this symbole for this symbol is sho!n belo!l is sho!n belo!. . )t can be seen that the output go)t can be seen that the output goes 3)$3es 3)$3 only !hen the
only !hen the inputs differ. inputs differ. )f both inputs go )f both inputs go 3)$3 the outpu3)$3 the output goes 6#9t goes 6#9. . )f both inputs go)f both inputs go 6#9 the output goes 6#9.
6#9 the output goes 6#9. Truth Table Truth Table A A (( * * ** ** * * 11 11 1 1 ** 11 1 1 11 ** @ @
Timing Diagram Timing Diagram #UT4UT #UT4UT )"4UT A )"4UT A )"4UT 1 )"4UT 1
Timing Diagram for an E>56US)E #' %>#'& gate Timing Diagram for an E>56US)E #' %>#'& gate
Boolean Expre Boolean Expressionssion
The formula that describes the function of this gate is as follo!s. The formula that describes the function of this gate is as follo!s.
B B A A B B A A F F == •• ++ ••
This is more commonly e7pressed in oolean algebra by a dedicated symbol B an addition This is more commonly e7pressed in oolean algebra by a dedicated symbol B an addition sign enclosed in a circle as follo!sC
sign enclosed in a circle as follo!sC
B B A A F F == ⊕⊕
"NO Gate (#$c%usive NO) "NO Gate (#$c%usive NO)
This is a combination of the >#' gate and the "#T gate %)nverter& in that order. This is a combination of the >#' gate and the "#T gate %)nverter& in that order. Symbol Symbol #utput ( #utput ( nput A nput A nput 1 nput 1 Truth Table Truth Table A A (( * * ** 11 * * 11 ** 1 1 ** ** 1 1 11 11 As
As can can be be seeseen n frofrom m ththe e trutruth th tatablble e ththe e ininpuputs ts are are >#>#'e'ed d totogegethther er anand d ththen en "#"#TTeded %inverted& to give the final output.
%inverted& to give the final output.
1 1 A A ( ( == ⊕⊕ Timing Diagram Timing Diagram #UT4UT #UT4UT )"4UT A )"4UT A )"4UT 1 )"4UT 1
Timing Diagram for an E7clusive "#' %>"#'& $ate Timing Diagram for an E7clusive "#' %>"#'& $ate
Direct app%ications o& t'e asic %ogic
Direct app%ications o& t'e asic %ogic operationsoperations %Te
%Terminology - A rminology - A it is a inary Digit. it is a inary Digit. A A byte is made up of @ bits. byte is made up of @ bits. && 6ogic gates are the building
6ogic gates are the building bloc+s of computers. bloc+s of computers. 2ost of the functions 2ost of the functions in a computerin a computer !ith !ith the e7ception of certain types of memory are implemented !ith logic gates used on a very the e7ception of certain types of memory are implemented !ith logic gates used on a very large scale.
large scale. (or e7ample a microprocessor (or e7ample a microprocessor !hich is the main part o!hich is the main part of a computer f a computer is made upis made up of hundreds and thousands of logic gates.
of hundreds and thousands of logic gates. App%ication
-App%ication - 5omputers need to selectively manipulate certain bits in one or more bytes of 5omputers need to selectively manipulate certain bits in one or more bytes of data.
data. Selective bit mSelective bit manipulations are achieved anipulations are achieved using a using a mas+. mas+. (or e7ample (or e7ample to clear %mto clear %ma+e alla+e all *?s& the right four bits in a data byte but +eep the information in the left four bits the data *?s& the right four bits in a data byte but +eep the information in the left four bits the data byte
byte is is A"Ded !ith A"Ded !ith 11111111****. ****. "otice "otice that that any any bit A"Ded bit A"Ded !ith !ith ero ero !ill !ill be be * * and and any any bitbit A"Ded !ith one !ill remain the same.
A"Ded !ith one !ill remain the same. Ex 1:
Ex 1: 9hat is the r 9hat is the resulting byte if 1*1*1*11esulting byte if 1*1*1*11,, is A"Ded !ith the mas+ 1111**** is A"Ded !ith the mas+ 1111****,,FF
App%ication * +
App%ication * + Another mas+ operation that is used in computer programming selectively Another mas+ operation that is used in computer programming selectively ma+es certai
ma+es certain bits in a n bits in a data byte equal to 1 !hile not affecdata byte equal to 1 !hile not affecting any othting any other bit. er bit. This is calledThis is called settin
setting %setting %setting a bit to 1&. g a bit to 1&. This is achThis is achieved usieved using the #' oping the #' operatioeration. n. A A mas+ is usemas+ is used thatd that contains a 1 in any position !here a data bit is to be set.
contains a 1 in any position !here a data bit is to be set. Ex 2:
Ex 2: 3o! !ould one force the most significant bit in a data byte to equal 1 but leave all of 3o! !ould one force the most significant bit in a data byte to equal 1 but leave all of the other bits unchangedF
the other bits unchangedF
1* 1*
Active %o, inputs Active %o, inputs
An active lo! input is represente
An active lo! input is represented by either a d by either a small circle at the small circle at the inpuinput point to a t point to a gate or by agate or by a bar
bar0 over the input vari0 over the input variablable e on a on a datdata sheet. a sheet. ThThis small circis small circle reprele representsents s a "#T gatea "#T gate %inverter&.
%inverter&. 5onsi
5onsider for e7amplder for e7amplee 5S5S- chip select an acti- chip select an active lo! input to an inve lo! input to an integratetegrated circuit. d circuit. 5hip5hip
select is enabled only !h
select is enabled only !hen the input volten the input voltage is lo!. age is lo!. The bar0 indThe bar0 indicates that the input isicates that the input is active lo!.
active lo!.
Sho!n belo! is an e7ample
Sho!n belo! is an e7ample of an A"D gate !ith active lo! of an A"D gate !ith active lo! inputs.inputs.
#utput ( #utput ( )nput A )nput A )nput 1 )nput 1 #utput #utput ((==AA..11 A A 1 1 )nput A )nput A )nput 1 )nput 1 Truth Table Truth Table A A (( * * ** 11 * * 11 ** 1 1 ** ** 1 1 11 ** Timing Diagram Timing Diagram #UT4UT #UT4UT )"4UT A )"4UT A )"4UT 1 )"4UT 1 Timing
Timing diagram for an A"Ddiagram for an A"D gate !ith active lo! inputs. gate !ith active lo! inputs.
11 11
