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Control activities for SOC (LIALP)
S. Lesecq
D. Puschini, L. Vincent, Y. Akgul En partenariat avec
E. Beigné (LISAN) Ph Maurine (LIRMM)
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Control in context: definitions
System Σ
Inside / Outside (“boundary”)
Inputs u ( actuation)
Output y ( sensing)
System Σ
Open loop
Closed-loop with observer
System Σ u y System Σ y Controller u Ref (setpoint) S S S A A S: sensor A: actuator x: system state (not always fully x
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Control for MPSoC: genesis
Management of PW consumption Frequency Locked-LoopFLL (collaboration LISAN) (quasi-)Linear system « robust » approach (pole placement) 32nm 28 nm 65 nm
HWimplementation of control law Non linear control approach SW
saturations/ NL Similar results ANOC L2-RAM (256KB) ITs ITs
Debug & Trace Unit
NI CDMA-M S M Memory Mapped Peripherals WDT
HWS-TMS TCK TDI TDO BIBO TMS TCK TDI TDO BIBO TMS TCK TDI TDO BIBO TMS TCK TDI TDO BIBO 16KB P-$ OCE 32-KB TCDM #1 16KB P-$ OCE 32-KB TCDM #2 16KB P-$ OCE 32-KB TCDM Processor #3 16KB P-$ OCE 32-KB TCDM Processor #4 LoCoMoTIV Hopping / DCO S P V T CVP-U NI CVP-U NI NI NI Hopping/ DCO S P V T CVP-U NI Hopping / DCO S P V T NI NI FLL layout
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ANOC
L2-RAM (256KB)
ITs ITs
Debug & Trace Unit NI CDMA-M S M Memory Mapped Peripherals WDT
HWS-TMS TCK TDI TDO BIBO TMS TCK TDI TDO BIBO TMS TCK TDI TDO BIBO TMS TCK TDI TDO BIBO 16KB P-$ OCE 32-KB TCDM #1 16KB P-$ OCE 32-KB TCDM #2 16KB P-$ OCE 32-KB TCDM Processor #3 16KB P-$ OCE 32-KB TCDM Processor #4 LoCoMoTIV Hopping / DCO S PVT CVP-U NI CVP-U NI NI NI Hopping/ DCO S PVT CVP-U NI Hopping / DCO S PVT NI NI
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PW consumption management
Collaboration CRI-INRIA (NeCS team) DVFS under thermal constraints
Several VFI towards distributed control
DVFS [S. Durand, doctorat INPG, 2011]
Control for MPSoC
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Control for MPSoC
PW consumption management Joint V/F control 3èmeactuator (Vth) ?? Vth Domaine tension/fréquence Vdd Tâche à effectuer F C O N T R Ô L E U R V F Zone non fonctionnelle F2 F1 V1 V2
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Outline
Control strategy (F, Vdd) (F, Vdd, Vbb)Cliquez pour modifier le style du titre
Travaux de Lionel Vincent
Temperature and Fast Voltage On-Chip Monitoring using
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Embedded electronics
Performances Low power
Consumption
⇒Distributed Architectures and Management
⇒ Usually : DVFS in each resource
F V T° Vmin Vmax T° Worst case design Global Control Power Domain Core Power Domain Power Domain Power Domain Power Domain V generator F generator Local control
⇒Monitor the variability
Vdrop Applicative
constraints
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Power Domain
Core
Global Control
Power Power Power Power
V generator F generator Local DVFS control Fast local adjustment
⇒AVFS : Adaptive Voltage and Frequency Scaling : Adaptive
architecture to mitigate local but also dynamic PVT variations
Info extract
(Data fusion)
⇒Reach the most
energy efficient and safe operating point
Adaptive architecture Applicative constraints Vˆ Tˆ Vˆ Tˆ VˆTˆ VˆTˆ VˆTˆ VˆTˆ
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Sensor for variability monitoring ⇒ Proposed sensor : Multiprobe
⇒Standard library cell : Easy to design
⇒Small : Easy to integrate and duplicatemany times in a core
⇒Values of V and T not directly readable
Counter
ROs
31µm x 14.4µm = 450 µm² in CMOS 32nm
Ring-oscillator #1
Stage 1 Stage 2 Stage n &
Scan in Scan out
. . . Start / Stop Test A d re ss d e co d e r 8 -t o -1 m u lt ip le xe r Ring-oscillator #2 Ring-oscillator #7
28 bits Counter flow bitOver- Config3 bits
Ref: 2nd European Workshop on CMOS Variability VARI 2011, L. Vincent, et al., "A Fully Integrated 32nm Multiprobe for Dynamic PVT Measurements within Complex Digital SoC“.
⇒ Monitoring Framework Multiprobe VT estimation method Validation on Hardware platform Fast V estimation method Calibration
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Core
Power Domain
Data fusion based on KS test in IC
Comparison between Measurements and Models using
Kolmogorov-Smirnov test Core { }V ˆˆ,T Estimated Info extract Interpretation (Digital Block) Models (Memory) { }V ˆˆ,T Estimated MProbe MProbe KS test Info extract (Data fusion) Multiprobe (7 ROs sensors)
Patent: “Electronic system with embedded sensors, method for estimating an operating physical quantity value and corresponding computer program”, (FR, 2012, EP, US 2013), L. Vincent and al.,
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Measured Data
Ideal calibration phase
Principle : Store some Measurements as Models
VT Estimation (Digital Block) N Frequencies Models Storing Model Statistical Signal Computation (CDF) MultiProbe (7 ROs sensors) Models (Memory) M{ {V,T}} { } { } { }p { }pq i i q T V T V T V T V T V M M M M M , , , , , 1 1 1 1 L M M L
Cliquez pour modifier le style du titreRunning-time phase
Based on goodness-of-fit hypothesis test
Interpretation (Digital Block) 7 Frequencies Models Reading Models (Memory) { } { } { } { }p { }pq i i q T V T V T V T V T V M M M M M , , , , , 1 1 1 1 L M M L { } Measured Data Model Models Storing Goodness-of-fit test Kolmogorov-Smirnov test Statistical Signal Computation (CDF) MultiProbe (7 ROs sensors)
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Results: method validation
ᴏ Conditions applied V = 0,83V T = 12°C x Estimated state V = 0,831V T = 11,66°C
Average estimation errors of
3.7mVand 6.2°C
⇒ Equivalent to timing margins in
re-adaptation policy <3%
Dependent on:
• The number of models
• The statistical test choice
• The pre-treatment of the
measurements Dots = models M •Discrepancy •Similarity Vdd (V) T ( ° C ) MultiProbe (7ROs sensors) Interpretation (Digital Block) 7 Frequencies Statistical Signal Computation (CDF) Goodness-of-fit test Kolmogorov-Smirnov test Models Reading Models (Memory) { } { } { } { }p { }pq i i q T V T V T V T V T V M M M M M , , , , , 1 1 1 1 L M M L { }V ˆˆ,T Estimated Models Storing Aggregation of selected results Weighted mean … pValue CDF
Ref: DAC’12 “Embedding Statistical Tests for On-Chip Dynamic Voltage and Temperature Monitoring “ L. Vincent et al.
Cliquez pour modifier le style du titrePerformances on hardware platform
Software implementation on SThorm platform
2500 cycles by tested model
⇒605µs @ 500MHz
Hardware accelerator:
42 cycles by tested model 10kbits memory 9kgates ⇒10µs @ 500MHz 605µs 605µs T V
Ref : D. Melpignano and al. Platform 2012, a many-core computing accelerator for embedded SoCs : Performance evaluation of visual analytics applications. Design Automation Conference (DAC), 2012
T V
10µs
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Core
Info extract
(Digital Block)
Need for a Fast Voltage monitoring
Power Domain Core { }V ˆˆ,T Estimated VT Estimation Models (Memory) { }V ˆˆ,T MultiProbe (7 ROs sensors) MProbe MProbe Info extract (Data fusion) Fast V Estimation @Tˆ Vˆ Tˆ F r RO F
⇒Complementary and compliant
with the VT estimation method
{ }V ˆˆ,T
Cliquez pour modifier le style du titreFast Voltage monitoring method
Tˆ
RO F
Vˆ
⇒Principle : Take advantage of
the dynamics disparities
⇒ Hypothesis : The temperature is
constant during the measurement
⇒ On SThorm : t
m≈ 0.66µs << tT°
time constant (>10µs)
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Performances on hardware platform
Hardware accelerator :
2,3 cycles estimated by tested model
⇒0.28µs @ 500MHz
⇒Limited by measurements: 0.66µs
Monitoring using the two complementary methods T V x18 T V
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A complete framework to monitor Voltage and Temperature variations on wide range of dynamics
Low-cost digital and general purpose sensor VT estimation methods
VT conjoint data fusion method: Use of goodness-of-fit hypothesis tests
Fast voltage monitoring method
Calibration method
Validated on SThorm hardware platform
A complete framework to monitor Voltage and Temperature