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Hardware Transactional Memory for GPU Architectures

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Figure

Figure 1: High-Level GPU architecture exposed by the CUDA programming model. TX Log Unit, Commit Unit added for KILO TM
Figure 2 compares the performance of a set of GPU TM applica- applica-tions (described in Section 5) running on an ideal GPU TM system against fine-grained lock versions of the applications
Figure 3: SIMT stack handling divergence due to transaction aborts (validation fail). Thread 6 and 7 have failed validation and are restarted
Figure 4: Commit Unit. (a) Communication flow with a SIMT core. (b) Overview of a commit unit.
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