Engr 303
Digital Logic Design
LAB 7 Counter and Parallel Serial Register
You will build several circuits using flip flops.Deliverables:
0) 4-Bit Shift Register
1) 4-Bit Synchronous Binary Counter 2) 4-Bit Shift Register with Parallel Load
3) 16-Bit Shift/Parallel Register with Hex Display
Demonstration Requirement:
You must demonstrate on the DE2 board the 16 Bit Shift/Parallel Register with Hex Display.
Part 0 – A 4-Bit Shift Register
Use block diagram entry to implement the 4 bit shift register, shown below. Suggested project name “ShiftReg4bit”. Use the D Flip Flop primitive that comes with Quartus , which is a positive-edge flip flop with synchronous reset and preload. The D FF developed in Lab 6 didn’t include reset and preload. The reset and preload are active low which means you need to take this signal low to active. We will tie the preload high to Vcc to disable it this test. The D FF output Q’s are run out as “hooks” for testing.
For reference, the following is an equivalent 4-Bit shift register design in Verilog // 4-Bit Shift Register Verilog design
module ShiftReg4bit_Verilog (Din, Clock, ResetN, Q, Dout); input Din, Clock, ResetN;
output reg [3:0] Q; output Dout;
always @ (posedge Clock) if (~ResetN) Q <= 4'b0; else Q <= {Q[2:0], Din}; assign Dout = Q[3];
endmodule
The following is a simulation of the 4-Bit Shift Register design. Study your waveform to verify the operation of a shift register.
4-Bit Shift Register Waveform
Part 1 – A 4-Bit Synchronous Binary Counter
Use block diagram entry to implement the design shown below. Suggested project name
“SyncCntr4bit”. This design is based on Figure 7-13a in Logic and Computer Design Fundamentals, 4th
Edition, by Morris Mano and Charles Kime
4-Bit Synchronous Binary Counter
ENGR303
For reference, the following is an equivalent 4-Bit synchronous binary counter design in Verilog // 4-Bit Synchronous Binary Counter Verilog design
module SyncCntr4bit_Verilog (EN, Clock, Q, Cout); input EN, Clock;
output reg [3:0] Q; output Cout;
always @ (posedge Clock)
if (EN) Q <= Q + 1; // Increment count if enabled (EN=1) else Q <= Q; // Hold Q if disabled (EN=0)
assign Cout = (Q == 4'b1111); endmodule
Verify that the circuit counts as shown in the simulation below. Arrange the Q's from msb Q3 to lsb Q0 and group them. Use unsigned decimal radix for TheQs to make it easier to read.
4-Bit Synchronous Binary Counter Waveform
Part 2 – A 4-Bit Shift Register with Parallel Load
Use block diagram entry to implement the Shift Register with Parallel Load design diagram given at the end of this document. This design is based on Figure 7-10 in Mano’s textbook. Suggested project name “ShiftParReg4bit”.
For reference, the following is an equivalent 4-Bit synchronous binary counter design in Verilog // 4-Bit Shift Register with Parallel Load Verilog design
module ShiftParReg4bit_Verilog (Sin, Clock, D, Load, Shift, ResetN, Q); input Sin, Clock, Load, Shift, ResetN;
input [3:0] D; output reg [3:0] Q; always @ (posedge Clock)
if (~ResetN) Q <= 4'b0; else begin if (Load) Q <= D; else case (Shift) 0: Q <= Q; 1: Q <= {Q[2:0], Sin}; endcase end endmodule
ENGR303
Use the following inputs for simulation. Verify that the simulation result as shown, and include the waveform results in your lab report.
4-Bit Shift Register with Parallel Load Waveform
Part 3 – 16-Bit Shift/Parallel with Hex Display
Implement a 16-Bit Shift / Parallel Load register using the block diagram given at the end of this document of the following Verilog module. Suggested project name “ShiftParReg16bit”. Make sure to
include ShiftParReg4bit and SevenSeg folders in the project library.
// 4-Bit Shift Register with Parallel Load Verilog design
module ShiftParReg16bit_Verilog (Sin, Clock, D, Load, Shift, ResetN, B, HEX0, HEX1, HEX2, HEX3);
input Sin, Clock, Load, Shift, ResetN; input [15:0] D;
output reg [15:0] B;
output [6:0] HEX0, HEX1, HEX2, HEX3; always @ (posedge Clock)
if (~ResetN) B <= 15'b0; else begin if (Load) B <= D; else case (Shift) 0: B <= B; 1: B <= {B[14:0], Sin}; endcase end
SevenSeg inst0 (B[3:0], HEX0); SevenSeg inst1 (B[7:4], HEX1); SevenSeg inst2 (B[11:8], HEX2); SevenSeg inst3 (B[15:12], HEX3); endmodule
Note if using block diagram entry we need to use the "Orthogonal Bus Tool" to create a bus. Name the binary bus B[15..0] as shown, and name each of the single signal "Nodes" B[3] etc, as shown. You may also pull the B bus out as another set of outputs, as shown.
Verify the circuits operation as shown in the simulation waveform. Here, I am loading 16 ONES, then shifting in ZEROS for 4 cycles before setting Sin high and shifting in a ONE.
DE2 Board testing:
For testing we will use RED LEDs for B0 thru B15 the binary output B. Use the first 4 hex displays to display B0-B15 in hexidecimal. Use toggle switches SW0 thru SW15 for the D inputs. Use SW16 for Load. Use SW17 for Shift. Use Key0 for the Clock. Use Key1 for ResetN. Use Key2 for Sin.
LAB SIGNAL
DE2 Name
DE2 Pin
DE2-115 Pin
B[0]
LEDR[0]
PIN_AE23
PIN_G19
B[1]
LEDR[1]
PIN_AF23
PIN_F19
B[2]
LEDR[2]
PIN_AB21
PIN_E19
B[3]
LEDR[3]
PIN_AC22
PIN_F21
B[4]
LEDR[4]
PIN_AD22
PIN_F18
B[5]
LEDR[5]
PIN_AD23
PIN_E18
B[6]
LEDR[6]
PIN_AD21
PIN_J19
B[7]
LEDR[7]
PIN_AC21
PIN_H19
B[8]
LEDR[8]
PIN_AA14
PIN_J17
B[9]
LEDR[9]
PIN_Y13
PIN_G17
B[10]
LEDR[10]
PIN_AA13
PIN_J15
B[11]
LEDR[11]
PIN_AC14
PIN_H16
B[12]
LEDR[12]
PIN_AD15
PIN_J16
B[13]
LEDR[13]
PIN_AE15
PIN_H17
B[14]
LEDR[14]
PIN_AF13
PIN_F15
B[15]
LEDR[15]
PIN_AE13
PIN_G15
LAB SIGNAL
DE2 Name
DE2 Pin
DE2-115 Pin
D[0]
SW[0]
PIN_N25
PIN_AB28
D[1]
SW[1]
PIN_N26
PIN_AC28
D[2]
SW[2]
PIN_P25
PIN_AC27
D[3]
SW[3]
PIN_AE14
PIN_AD27
D[5]
SW[5]
PIN_AD13
PIN_AC26
D[6]
SW[6]
PIN_AC13
PIN_AD26
D[7]
SW[7]
PIN_C13
PIN_AB26
D[8]
SW[8]
PIN_B13
PIN_AC25
D[9]
SW[9]
PIN_A13
PIN_AB25
D[10]
SW[10]
PIN_N1
PIN_AC24
D[11]
SW[11]
PIN_P1
PIN_AB24
D[12]
SW[12]
PIN_P2
PIN_AB23
D[13]
SW[13]
PIN_T7
PIN_AA24
D[14]
SW[14]
PIN_U3
PIN_AA23
D[15]
SW[15]
PIN_U4
PIN_AA22
LAB SIGNAL
DE2 Name
DE2 Pin
DE2-115 Pin
Load
SW[16]
PIN_V1
PIN_Y24
Shift
SW[17]
PIN_V2
PIN_Y23
Clock
Key[0]
PIN_G26
PIN_M23
ResetN
Key[1]
PIN_N23
PIN_M21
SIn
Key[2]
PIN_P23
PIN_N21
Lab Signal Name
DE2 Pin
DE2-115 Pin
HEX0[0]
PIN_AF10
PIN_G18
HEX0[1]
PIN_AB12
PIN_F22
HEX0[2]
PIN_AC12
PIN_E17
HEX0[3]
PIN_AD11
PIN_L26
HEX0[4]
PIN_AE11
PIN_L25
HEX0[5]
PIN_V14
PIN_J22
HEX0[6]
PIN_V13
PIN_H22
HEX1[0]
PIN_V20
PIN_M24
HEX1[1]
PIN_V21
PIN_Y22
HEX1[2]
PIN_W21
PIN_W21
HEX1[3]
PIN_Y22
PIN_W22
HEX1[4]
PIN_AA24
PIN_W25
HEX1[5]
PIN_AA23
PIN_U23
HEX1[6]
PIN_AB24
PIN_U24
HEX2[0]
PIN_AB23
PIN_AA25
HEX2[1]
PIN_V22
PIN_AA26
HEX2[2]
PIN_AC25
PIN_Y25
HEX2[3]
PIN_AC26
PIN_W26
HEX2[5]
PIN_AB25
PIN_W27
HEX2[6]
PIN_Y24
PIN_W28
HEX3[0]
PIN_Y23
PIN_V21
HEX3[1]
PIN_AA25
PIN_U21
HEX3[2]
PIN_AA26
PIN_AB20
HEX3[3]
PIN_Y26
PIN_AA21
HEX3[4]
PIN_Y25
PIN_AD24
HEX3[5]
PIN_U22
PIN_AF23
4-Bit Shift Register with Parallel Load
(source: M. Mano and C. Kime, Logic and Computer Design Fundamentals, 4th Edition, Chapter 7 Figure 7-10)
