Universidad Politécnica de Madrid
José A. Cobos, Pedro Alou
Centro de Electrónica Industrial (CEI)
Outline
Motivation
Cout, Current & voltage steps
Optimal time control
Analog implementations
V
2, hysteresis
Proposed control implementation
Limitations of the proposed control
ESL, OpAmp bandwidth
Cout tolerances
Variable frequency. Freq loop
Experimental results
Summary
d e n ica ri al
Transient Response 5.5VIN/3.3VOUT,
0-6A, 10A/uS.
CIN = 50uF COUT = 50uF
EN5365QI
Control
L
v
oV
in5MHz Integrated Converter
Bandwidth limitations of Linear control
NON Linear Control
Robustness at very high frequency
- Noise
- Parasitic influence
d e n ica ri al
i
Lv
ov
o
C
L
)·
V
,
(V
k
t
min
≈
d
1
2
eq
⋅
(Constant load current during the transient)
i
L
Minimum time control
t
min?
Minimum time
Linear Simulation ResultsTime (sec) A m pl it ude 0.5 1 1.5 2 2.5 T o: Y (1) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 x 10-6 -10 0 10 20 30 40 50 T o: Y (2) Time (µs) ton toff Tmin iL (A) Vo(V)
Linear Simulation Results
Time (sec) A m pl it ude 0.5 1 1.5 2 2.5 T o: Y (1) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 x 10-6 -10 0 10 20 30 40 50 T o: Y (2) Time (µs) ton toff Tmin iL (A) Vo(V)
V
inNON Linear Control
Optimum response for load and voltage steps
Complex implementation
Digital Solutions
Non Linear
Take the system close to steady state
Linear
Steady state, but must not interfere (Instabilities)
Analog Solutions
Combination of Non-linear and Linear Control
d e n ica ri al
V
2
and V
OUT
Hysteretic approaches
Fast response to current steps
Two control loops:
• Fast loop: fast transients
• Slow loop: DC accuracy
Io IL VC Vo SW Vi Q Q PWM Latch PWM Comparator IL VO IO R C L _ + VS _ + _ + VREF
Sensing output voltage ripple:
noise problems
Triangular output voltage ripple
needed (ESR dominant)
Fast response to current steps
V
2
and V
OUT
Hysteretic approaches
VC Vo
d e n ica ri al
Depending on C
OUT
…
ESR dominant
Not ESR dominant
Voltage ripple provides an
instantaneous measurement of
C
OUTcurrent
Voltage ripple is delayed with
respect to C
OUTcurrent
LOAD STEP
Vout, ESR dominant
V
OUT
I
L
V
DRIVER
d e n ica ri al
∆
I
oI
oI
Cout0 A
I
CoutInstantaneous response under
current steps
i
L∆
I
o +-K
c*i
c refNon Linear + Linear control
V
ref +-v
o ref +-
+v
outK
c*i
c refRegulator
i
c_refv
reft
trackQ
cv
oi
c_refv
reft
trackQ
cv
oV
OK
c*i
c refLinear loop to regulate V
OUT
100kHz bandwidth is enough
2-3µs time response for a 1V voltage
step
d e n ica ri al
Equivalent RLC network + trans-impedance amplifier
Output Capacitor Current Sensor
∆
V
OV
S
= R1·I
s
I
sI
CoutCout
Output capacitor
Cs
ESL
1 2 +-ESR
Rs
R1
Output capacitor
Z
CoutI
S
= I
Cout
/n
Current sensor: design goals
Objective:
To design a parallel RLC
network
Scaled impedance magnitude
Equal phase and/or same time
constants
I
CoutI
st
A
Same phases
Scaled impedance
magnitude
Sensor Measurement (I
s)
Cout current (I
Cout)
ICout Cout ESR ESL IS CS L Req Load
Z
Cout
Z
s
n*
Z
Cout
(f
SW
)=Z
s
(f
SW
)
d e n ica ri al
ESL effect is given by Op Amp bandwidh
ΔB
R1
Ls
Li
=
=
Where:
Rs =
Sensor resistance
Ri =
Trans-impedance amplifier input resistance
Li =
Trans-impedance amplifier input inductance
10
ΔB
10
wp
A
w
<
DC⋅
=
Assuming
·i
s 1 2 1 2ESR
·i
1 2 1 2R1·I
ESL
1 2 1 2 1 2 Li 1 2 RiCout
Cs Rs IINI
CoutZ
CoutOutput capacitor
Z
sCs
Li
Ri
Rs
i
sI
Swp
A
DCΔ
B
w
db
Tolerance Analysis: Influence of different
Δ
B
Nominal case: Simulation results
-500.00m 500.00m
0
71.00u 71.50u 72.00u
T
Cout= T
sI
CoutI
S 500.00m 0≠ Ts
Sensor designed for 135 MHz
but
ΔB is 100MHz
500.00m
0
≠ Ts
Sensor designed for 135 MHz
but
ΔB is 170MHz
I
CoutI
SI
CoutI
SSensor gain is affected:
-15%
∆
B deviation produces
d e n ica ri al
Design specifications:
Switching frequency:
5MHz
C
OUTresonant frequency:
1.5MHz (approx.)
C
OUTdielectric:
X7R (Thermal variation +/- 15%)
System operates in inductive side
Cout ESR ESL
Cout
MLCC
Switching Frequency Capacitive side Inductive side Cout Resonant Frequency-12.40 12.46
-10.00 0 10.00
17.34u 17.50u 18.00u 18.27u AM1.I ...
155.00...
If sensor is designed for inductive side, but C
OUT
is reduced
and system changes from inductive to capacitive side:
Coutactual current
Cout sensed current
Incorrect
operation
Restriction:
Assure by design that system always
Restriction to output capacitor tolerance
i
Cout
d e n ica ri al
Worst case of f
RES
variation
System operates properly
, remaining on inductive side
Resonant frequency changes from 1.59 MHz to 2.1 MHz
Phase remains unchanged
1.00m 10.00 2.00m 3.00m 10.00m 20.00m 30.00m 100.00m 200.00m 300.00m 1.00 2.00 3.00
10.00k30.00k 100.00k 300.00k 1.00Meg 3.00Meg 10.00Meg 30.00Meg 100.00Meg 1.00G
5MHz Nominal case C-25% L-25% 1.00m 10.00 2.00m 3.00m 10.00m 20.00m 30.00m 100.00m 200.00m 300.00m 1.00 2.00 3.00
10.00k30.00k 100.00k 300.00k 1.00Meg 3.00Meg 10.00Meg 30.00Meg 100.00Meg 1.00G
5MHz Nominal case C-25% L-25% 1.00u 100.00m 2.00u 10.00u 20.00u 100.00u 200.00u 1.00m 2.00m 10.00m 20.00m
10.00k30.00k 100.00k 300.00k 1.00Meg 3.00Meg 10.00Meg 30.00Meg 100.00Meg 1.00G Nominal case C-25%L-25% 5MHz 1.5MHz XXMHz 1.00u 100.00m 2.00u 10.00u 20.00u 100.00u 200.00u 1.00m 2.00m 10.00m 20.00m
10.00k30.00k 100.00k 300.00k 1.00Meg 3.00Meg 10.00Meg 30.00Meg 100.00Meg 1.00G Nominal case C-25%L-25% 5MHz 1.5MHz 2.1MHz C -25% and ESL -25%
f
resincreases 1.32 times
Current sensor design: Experimental validation
ΔICout ΔVsScaled impedances
I
CoutI
SThe design must regard:
Tolerance of
∆
B: sensor gain variation
Design restriction: f
<f
d e n ica ri al
Limitation: frequency is not constant
Restrictions:
V
inand V
outrange
Output capacitor tolerances
Current sensor tolerances
I
Coutv
ov
outV
in=5V
2.7V - 5.5V
V
out=1V
1V - 2V
LO A D100 nH
I
Cout HHysteretic
Band
V
inrange
and
V
outrange
f
SW= 5 MHz
7.8MHz +59 %
5MHz
3.2MHz -35 %
Frequency loop: Proposed solution
LOAD +- -+ Vref -Vout s Ki 1 s · C · R Ke + Kc*icref Frequency Divider Counter Frequency/Voltage Converter fsw VCR (Voltage Controlled Resistor) Frequency Loop Regulator-+ Vfref V(f) FD sw k f Hysteretic Band Adjustment
d e n ica ri al
V
OUTV
REF1.5V
2.5V
I
LV
DRIVER1.5V
2
μ
s
2
μ
s
Experimental results of the whole system:
Voltage step
-
Very fast response!
Experimental results of the whole system:
frequency loop
V
OUTV
REF1.5V
2.5V
V
error(Hysteretic band adjustment)
V
DRIVER1.5V
340 mV
920 mV
920 mV
Frequency loop adjusts the switching frequency to the
4 s
4 s
d e n ica ri al
Conclusions
Hysteretic control of the output capacitor current
Very simple control strategy
Very fast dynamic response, close to Minimum Time Strategy
Reduction of output capacitors (5x)
Based on measuring capacitor current: Limitations
Always in the same side: Inductive or capacitive
Capacitance tolerances and Op Amp bandwidth must be regarded in
the design
Variable frequency, corrected by the frequency loop
Not direct application to Multiphase
Minimum time
[1] Z. Zhao, A. Prodic, "Continuous-Time Digital Controller for High-Frequency DC-DC Converters", in IEEE Transactions on Power Electronics, vol. 23, pp. 564-573, March 2008. [2] Costabeber, A.; Corradini, L.; Mattavelli, P.; Saggini, S., “Time optimal,
parameters-insensitive digital controller for DC-DC buck converters”, in Proc. Conf. PESC’08.
[3] Biel, D.; Martinez, L.; Tenor, J.; Jammes, B.; Marpinard, J.C., “Optimum dynamic performance of a buck converter”, in Proc. IEEE ISCAS’96.
Look-up-table
[4] Yousefzadeh, V. Babazadeh, A. Ramachandran, B. Alarcon, E. Pao, L. Maksimovic, D., “Proximate Time-Optimal Digital Control for Synchronous Buck DC–DC Converters”, in IEEE Transactions on Power Electronics, vol. 23, pp. 2018 - 2026, July 2008.
[5] Yousefzadeh, V. Choudhury, S., “Nonlinear digital PID controller for DC-DC converters”, in Proceedings of the IEEE Applied Power Electronics Conference APEC’08.
[6] Haitao Hu, Yousefzadeh, V., Maksimovic, D., “Nonlinear Control for Improved Dynamic
d e n ica ri al
Minimum time
[7] Meyer, E.; Zhang, Z.; Liu, Y.-F., “An Optimal Control Method for Buck ConvertersUsing a Practical Capacitor Charge Balance Technique”, in IEEE Trans. Power Electron., vol. 23, Jully 2008.
V
2and Vout hysteretic controls
[8] D. Goder and W. R. Pelletier, “V2 architecture provides ultra-fast transient response in switch mode power supplies”, in Proceedings of HFPC Power Conversion 1996
[9] K. S. Leung and H. S. Chung, “Dynamic hysteresis band control of the buck converter with fast transient response,” IEEE Trans. Circuits Syst., vol. 52, no. 7, Jul. 2005.
[10] Schuellein, G., “Current sharing of redundant synchronous buck regulators powering high performance microprocessors using the V2 control method”, in Proceedings of the IEEE Applied Power Electronics Conference APEC’98.
[11] Qu S., “Modeling and Design Considerations of V2 Controlled Buck Regulator”, in Proceedings of the IEEE Applied Power Electronics Conference APEC’01.
[12] W. Huang, “A New Control for Multi-phase Buck Converter with Fast Transient Response”, in Proceedings of the IEEE Applied Power Electronics Conference APEC’01.