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Side-Channel Security Analysis of Ultra-Low-Power FRAM-based MCUs

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Figure

Table 1. AES accelerator performance figures
Fig. 1. Structure of the two-way associative cache
Fig. 2. Measurement setup
Fig. 3. AES in hardware: (a) a sample trace (full AES), (b) and (c) CPA attack resultsusing 100 000 traces
+7

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