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Zero Temperature Coefficient Bias Point for Asymmetrical and Symmetrical Double Metal Double Gate MOSFETs

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Figure

Fig. 1 Schematic of simulated device (a) Asymmetric double metal double gate (ADMDG), (b) Symmetrical double metal double gate (SDMDG) SOI MOSFET
Fig. 4(a) shows the intrinsic capacitances (Cgs and Cgd) as a function of VGS for both sub-threshold or weak inversion and super-threshold or strong inversion regions
Fig. 2 (a) Drain current (ID) and transconductance (gm) as a function of gate voltage (VGS), (b) Drain current (ID) and output transconductance (gd) as a function of drain voltage (VDS), (c) Intrinsic gain (AV) as a function of gate voltage (VGS) for different configurations as ADMDG and SDMDG SOI MOSFETs
Fig. 3 (a) Drain insulated barrier lowering (DIBL), (b) Subthershold swing (SS), (c) On-Off current ratio (Ion/Ioff) as a function of temperature for different configurations as ADMDG and SDMDG SOI MOSFETs
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