High Speed VLSI Architecture of Wallace Tree Multiplier Utilised in FIR Filter

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 9, Issue 6, June 2019)

199

High Speed VLSI Architecture of Wallace Tree Multiplier

Utilised in FIR Filter

V. Kumara Swamy

1

, R.V.S Vishnu Vardhan

2

, A.Shravanthi

3

, B. Sai Krishna

4

1

Associate Professor & Associate Head, Dept of ECE, Sreenidhi Institute of Science and Technology, India

2,3,4Student, Sreenidhi Institute of Science and Technology, India

Abstract —Digital filters are used extensively in all areas of electronic industry in which FIR filters are most widely used. This paper presents a design of FIR filter by using BOOTH and WALLACE multiplier in replacement to the basic multiplier. Optimizing the speed and area of a multiplier is a major design issue. The area and speed are the conflicting constraints because the faster speed results in the larger area. The faster execution speed and smaller area are the important factors in designing the DSP systems. The multiplier used in the design is combined with carry save adder (CSA) and carry skip adder (CSK) of FIR filter, so that the performance is improved by maintaining the trade off. This criterion is very important in the fabrication of the chips and the high performance systems require components which are as fast as possible. Finally, the simulation and synthesis results obtained have proved that the implementation of a FIR filter using a Wallace Tree Multiplier and Carry Save Adder gives best performance in terms of speed.

Keywords BOOTH, CSA, CSK,DSP,WALLACE,FIR

I. INTRODUCTION

Filter is a frequency selective system. It permits a certain band of frequencies at the same time attenuating the other frequencies. Filters are of two types i.e. analog and digital depending upon the nature of inputs and outputs. They are further divided as finite impulse response and infinite impulse response filters based on impulse response. The details of types of filters are given below [1].

A.Analog Filters

Passive filters contains passive components (R,L,C), they do not depend upon an external power supply and/or they do not contain active components such as transistors or battery. The simplest passive filters, RC and RL filters, include only one reactive element, except HYBRID LC Filter which is characterized by inductance and capacitance integrated in one element.

Active filters are implemented using a combination of passive and active (amplifying) components and a power source. Operational filters are frequently used in active filter designs. These can have high Q Factor, and can achieve resonance without the use of inductors.

However, their upper frequency limit is limited by the bandwidth of the amplifiers. The most common types of active filters are classified into four such as Butterworth, Chebyshev, Bessel and Elliptical.

B.Digital Filters

Digital filters are used extensively in all areas of electronic industry. This is because digital filters have the potential to attain much better signal to noise ratios than analog filters and at each intermediate stage the analog filter adds more noise to the signal, the digital filter performs noiseless mathematical operations at each intermediate step in the transform. The digital filters have emerged as a strong option for removing noise, shaping spectrum, and minimizing inter-symbol interference in communication architectures. These filters have become popular because their precise reproducibility allows design engineers to achieve performance levels that are difficult to obtain with analog filters.

Digital Filters are further classified into : 1) FIR Filter

2) IIR Filter

Digital Filters can be constructed from 3 fundamental mathematical operations.

Addition (or subtraction).

Multiplication (normally of a signal by a constant). Time Delay i.e., delaying a digital signal by one or more [1].

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 9, Issue 6, June 2019)

200

II. THEORETICAL ANALYSIS

The Figure.2 below gives the Direct form FIR architecture. In the block diagram we have a register an adder an multiplier connected through a cascaded Direct form structure in this when the Input X(n) gives rise to an output Y(n).When the input of X(n) is passed through the register it gives rise to a delayed input X(n-1) and this input is passed on to next register to give rise to X(n-2) ,X(n-3) and so on. The multiplier used is replaced by architectures of Wallace Tree Multiplier and Booth Multiplier Whereas the Adder is replaced by adders like Ripple carry Adder, Carry Select Adder, Carry Look Ahead Adder, Carry skip Adder, Carry Save Adder.

Fig.2 Block diagram of Direct Form FIR Filter Architectur

A. Taps

Registers are the delay elements that are used in bulding a FIR filter. A FIR ―tap‖ is simply a coefficient/delay pair. The number of FIR taps, (often designated as ―N‖) is an indication of 1) the amount of memory required to implement the filter, 2) the number of calculations required, and 3) the amount of ―filtering‖ the filter can do; in effect, more taps means more stopband attenuation, less ripple, narrower filters, etc [2].

B.Multipliers

In the proposed FIR filter architecture we have chosen to use Wallace Tree Multiplier and Booth multiplier and compare for the architecture with least delay. Wallace Tree Multiplier is an efficient hardware implementation of a digital circuit that multiplies two integers. Wallace tree reduces the number of partial products and use carry select adder for the addition of partial products. Wallace tree guarantees the lowest whole delay. Booth multiplier reduces number of iteration step to perform multiplication as compare to conventional steps.

Booth algorithm ‗scans‘ the multiplier operand and skips chains of this algorithm can reduce the number of additions required to produce the result compared to conventional multiplication algorithm., where each bit of the multiplier is multiplied with the multiplicand and the partial products are aligned and added together.

1. Wallace Tree Multiplier:

C. S. Wallace (1964) propounded a fast technique to perform multiplication. A Wallace tree multiplier offers faster performance for large operands. Unlike an array multiplier the partial product matrix for a tree multiplier is rearranged in a tree-like format, reducing both the critical path and the number of adder cells needed. Figure 3 shows the tree structure of the partial product matrix.

Fig.3 Partial products in array multiplier and Wallace tree multiplier

The benefit of the Wallace tree is that there are only O(log n) reduction layers, and each layer has O(1) propagation delay. As making the partial products is O(1) and the final addition is O(log n), the multiplication is only O(log n), not much slower than addition (however, much more expensive in the gate count). Naively adding partial products with regular adders would require O(log^2n) time. From a complexity theoretic perspective, the Wallace tree algorithm puts multiplication in the class NC1.These computations only consider gate delays and don't deal with wire delays, which can also be very substantial.

2. Booth Multiplier:

The use of Booth‘s algorithm, in multiplication presents an efficient solution that suits the demands of high-speed multipliers, which also need to be efficient in terms of hardware design/area complexity.

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 9, Issue 6, June 2019)

201

It is a powerful algorithm for signed-number multiplication, which treats both positive and negative numbers uniformly and reduces the number of multiplicand multiples. Booth‘s algorithm effectively skips over runs of 1‘s and 0‘s that it encounters in the multiplier [4].

C. Adders

1. Ripple carry adder:

A ripple carry adder also known as ―n-bit parallel adder‖ is a combinational logic circuit used for the purpose of adding two n-bit binary numbers and requires ‗n‘ full adders in the circuit[4].

Fig.4 Block diagram of 16 bit ripple carry adder.

Half Adders can be used to add two one bit binary numbers. It is also possible to create a logical circuit using multiple full adders to add N-bit binary numbers [5]. Each full adder inputs a Cin ,which is the Cout of the previous adder.

This kind of adder is a Ripple Carry Adder, since each carry bit "ripples" to the next full adder. The first (and only the first) full adder may be replaced by a half adder [6]. The block diagram of 4-bit Ripple Carry Adder is shown in above diagram.

The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder [7].

The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is 31 * 2(for carry propagation) + 3(for sum) = 65 gate delays [5].

2. Carry look ahead adder:

The carry look ahead adder (CLA) solves the carry delay problem by calculating the carry signals in advance, based on the input signals. It is based on the fact that a carry signal will be generated in two cases: (1) when both bits ai and bi are 1, or (2) when one of the two bits is 1 and the carry-in is 1 . Thus, one can write

Ci+1=ai & bi + (ai ^ bi) &ci ---(1)

Si =ai ^ bi ^ ci ---(2)

The above two equations can be written in terms of two new signals pi and gi

Where, Pi = ai ^ bi Gi= ai & bi

Ci+1= Gi + PI & Ci Si= Pi ^ Ci

The disadvantage of CLA is that the carry logic block gets very complicated for more than 4-bits. For that reason, CLAs are usually implemented as 4-bit modules and are used in a hierarchical structure to realize adders that have multiples of 4-bits.

Fig.5 Block Diagram of 4 Bit Carry Look Ahead Adder.

Fig.6 Block Diagram of 16 Bit Carry Look Ahead Adder.

3. Carry Skip Adder:

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 9, Issue 6, June 2019)

202

The signal will be produced by this circuit and known as propagation signal. If the carry is transmitted through all the stages in the block then the carry signal entering the block can directly be by-passed. Depending on the position at which a carry signal has been generated the propagation time will be varied. If suppose there is no carry generation then only the addition time will be considered which will be considered as the best case. Here the design of 16 bit carry skip adder is considered and hence the block diagram consists of four multiplexers. The block diagram for the implementation of the Carry Skip Adder is shown below[11].

Fig.7 4 Bit Carry Skip Adder.

4. Carry Select Adder:

A CSLA generally consists of two RCA and a Multiplexer (MUX). It performs two additions in parallel, by assuming carry-in of 0 and carry-in of 1. A CSLA performs fast addition since adders are split in blocks of N bits A K-bit CSLA is shown in Figure. It contains two groups of adders as one for lower N/2 bits and another for higher N/2 bits. The higher N/2 bits group adder computes the partial sum and partial carry by assuming carry-in 1 and carry-in 0 in parallel with the lower N/2 bits. It generates final sum and carry based on the MUX selection input. Hence the delay of the CSLA can be defined as,

T select-add (N) = T add(N/2) + 1

The CSLA is widely used in High performance applications. But it consumes large area and power due to its increased hardware resources.

Many research articles have proposed various hints to reduce area and power in the CSLA structure.

Fig.8 Block diagram of 16 bit Carry Select Adder.

5. Carry Save Adder:

A carry-save adder is a type of digital adder, used in computer micro architecture to compute the sum of three or more n-bit numbers in binary. It differs from other digital adders in that it outputs two numbers of the same dimensions as the inputs, one which is a sequence of partial sum bits and another which is a sequence of carry bits.

Consider the sum:

12345678 + 87654322 =100000000.

Using basic arithmetic, we calculate right to left, "8+2=0, carry 1", "7+2+1=0, carry 1", "6+3+1=0, carry 1", and so on to the end of the sum. Although we know the last digit of the result at once, we cannot know the first digit until we have gone through every digit in the calculation, passing the carry from each digit to the one on its left. Thus adding two n-digit numbers has to take a time proportional to n, even if the machinery we are using would otherwise be capable of performing many calculations simultaneously [12].

III. PROPOSED ARCHITECTURES

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 9, Issue 6, June 2019)

203 Fig.9 Architecture of Direct Form FIR Filter Architecture using

Booth Multiplier and Carry Save Adder.

B. FIR filter using Wallace Tree multiplier and Carry Save Adder

In the design of the proposed architecture we have used a Wallace Tree Multiplier in place of a regular array multiplier for analyzing the delay that is obtained due to the operations performed in FIR. Booth multiplier uses booth recoding table in its booth algorithm which has codes for every operation. This helps in reducing delay and having efficient operation of FIR. In The below figure 10.

Fig.10 Architecture of Direct Form FIR Filter Architecture using Wallace Tree Multiplier and Carry Save Adder.

IV. RESULTS AND DISCUSSION A. Adders Comparison:

From below analysis in table 2 we can say that the Carry Save Adder utilizes the least delay and is efficient for building an FIR filter. Also figure 11 shows the delay comparison bar graph of different types of adders.

Table 2

Comparision Chart of Adders.

Fig.11 Delay Comparison Of Adders.

B.Multipliers Comparison:

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 9, Issue 6, June 2019)

204

From the above comparison in figure 14 of multipliers we can say that the Wallace multiplier has the least delay and it can be concluded that using Wallace tree multiplier over booth is necessary for faster computation in DSP operations. The figure 12 shows delay comparison of the multipliers that have been compared.

Fig.12 Delay comparison of Multipliers.

Fig.15 Simulation of Proposed Wallace Tree Multiplier.

V. CONCLUSION

The Proposed Wallace Tree Multiplier is designed by choosing a suitable adder and multiplier unit by comparing various adders and multipliers.

We can conclude from the results that using of a Wallace tree multiplier along with a carry save adder helps in reduction of delay in the FIR operation. The simulations have been carried out using Xilinx ISE design suite 13.2 and device used is xc3s200-5pqg208 of Spartan family.

REFERENCES

[1] A.Sirisha, P.Balanagu & N.Suresh Babu,‖ Design of Fir Filter Using Look up Table and Memory Based Approach‖ International Journal of Computer & Communication Technology ISSN (PRINT): 0975 -7449, Volume-5, Issue-1, 2016

[2] Abhijit Chandra , Sudipta Chattopadhyay , ― Design of Hardware efficient FIR filter:A review of the state-of-Art-approaches ―Engineering Science and Technology, an International Journal Volume 19, Issue 1, March 2016, Pages 212-226

[3] Sudha .S .A , Marimuthu C. N ―Design of Area Delay-Power Efficient Adaptive Filter using Wallace Tree Multiplier‖ International Journal of Scientific Engineering and Research (IJSER) ISSN (Online): 2347-3878 Volume 2 Issue 4, April 2014

[4] Vivek Gupta, Prof. Vaibhav Jindal ,‖ VLSI Architecture for Complex Vedic Multiplier using Hybrid Square Kogge Stone Adder Technique‖ International Journal of Innovative Research in Science, Engineering and Technology Vol. 7, Issue 6, June 2018

[5] http://vlabs.iitkgp.ac.in/coa/exp1/index.html [6] https://en.m.wikipedia.org/wiki/Adder_(electronics)

[7] http://www.ques10.com/p/26336/explain-ripple-carry-adder in-detail-1/

[8] https://www.scribd.com/document/135749594/Parallel Binary-Adder

[9] http://csi.fragnel.edu.in/labmanual/comporg.pdf

[10] https://www.scribd.com/document/219574607/i-43024751 [11]

https://www.scribd.com/document/30268048/2-Lecture-Notes-Lesson3-3

[12] Vadapalli Siddhartha ,‖ FIR Filter Design and Implementation using Remez Exchange Algorithm with Multipliers and Adders‖ International Journal of VLSI and Embedded Systems-IJVES ISSN: 2249 – 6556 Vol 06, Article 09634; October 2015

Figure

Fig.3 Partial products in array multiplier and Wallace tree multiplier

Fig 3.

Partial products in array multiplier and Wallace tree multiplier . View in document p.2
Fig.2 Block diagram of Direct Form FIR Filter Architectur

Fig 2.

Block diagram of Direct Form FIR Filter Architectur . View in document p.2
Table 1  Booth’s Recoding Table

Table 1.

Booth s Recoding Table . View in document p.2
Fig.7 4 Bit Carry Skip Adder.
Fig 7 4 Bit Carry Skip Adder . View in document p.4
Fig.8 Block diagram of 16 bit Carry Select Adder.

Fig 8.

Block diagram of 16 bit Carry Select Adder . View in document p.4
Fig.11 Delay Comparison Of Adders.

Fig 11.

Delay Comparison Of Adders . View in document p.5
Fig.10 Architecture of Direct Form FIR Filter Architecture using Wallace Tree Multiplier and Carry Save Adder

Fig 10.

Architecture of Direct Form FIR Filter Architecture using Wallace Tree Multiplier and Carry Save Adder. View in document p.5
Table 2   Comparision Chart of Adders.

Table 2.

Comparision Chart of Adders . View in document p.5
Table 3   Comparison of Multipliers.

Table 3.

Comparison of Multipliers . View in document p.5

References

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