OVERVIEW
Memory and data storage take many forms, even in a single computer system. Figure 6-1 classi- fies the various memory categories that are discussed in the following pages. There are two main classifications of memory families. These are RAM (Random Access Memory) and ROM (Read Only Memory) devices. RAM devices are volatile, which is to say they lose their memory content when the power to the host system is turned off. ROM devices are non-volatile, meaning they retain their stored data when the power is removed.
RAM products are read and written to with the same electrical characteristics. They are easy to write but are volatile, meaning that when the power is turned off, the devices lose the memory content.
ROM-based devices—ROM, EPROM, EEPROM, and flash memory devices are easy to read but are more difficult to program (write) than RAM devices. EEPROM and flash devices are more dif- ficult to program than they are to read. EPROMs need a mechanical step (UV-light) to erase the memory cells prior to re-programming the device. One-time programmable (OTP) EPROMs can
Memories
RAM
Volatile Non Volatile Non
Programmable
One-Time Programmable
Programmable Several Times ROM
SRAM DRAM NVRAM BRAM FRAM ROM OTP EPROM EEPROM Flash
19993A Source: ICE, "Memory 1997"
Figure 6-1. Memory Classification
be written only one time by the user. ROM products are programmed during process manufac- turing. Figure 6-2 shows the different types of memories and some of the main characteristics of the devices.
GENERAL TECHNOLOGY ISSUES
Memory devices have historically been considered “process drivers” as well as revenue produc- ers. A process driver is a product that is manufactured in large wafer volumes, that pushes the state-of-the-art in processing, and has a die yield that can be used to measure the effectiveness of the process.
FRAM
DRAM SRAM EPROM ROM Parallel Flash NVRAM
EEPROM Characteristic
Cell Organization
Storage Method
Number of Devices in Cell
Relative Cell Size Density Overhead Cost
Volatile (Power Off)
Data Retention (D.C. Power On)
In System Reprogrammable
Number of Reprogram Times (Endurance)
Typical Write (Reprogram) Speed
Typical Read Speed (ns)
1T + 1C
Charge on Capacitor
1.5
1.5 64Mbit
Refresh Logic
Yes 4ms
Yes
∞
100ns
100
1 Flip-Flop + 2T
Flip-flop circuit
4-6
4-6 4Mbit
No
Yes
∞
Yes
∞
25ns
25
1T with Floating Gate
Charge on Floating Gate
1.0
1.5 16Mbit
UV Erase Programmer
No 10 Years
No
100
30min
100
1T
Masked in Production
1.0
1.0 64Mbit
Mask Charges
No
∞
No
—
—
100
1T + 1T with Floating
Gate
Charge on Floating
Gate 2.0
3-4 4Mbit
No
No 10 Years
Yes
1,000,000
2.5s
200
1 SRAM Cell + 1 EEPROM Cell
SRAM + Back-Up in EEPROM
8-9
9-10 256K No
No 10 years
Yes
1,000,000
—
200 1T with
Floating Gate
Charge on Floating Gate
1.0
1.5 64Mbit
No
No 10 Years
Yes
10,000
2.5s
200
1T + 1C
Charge on Capacitor
2.0
2.0 256K
No
No 10 Years
Yes
1012
235ns
150
Source: ICE, "Memory 1997" 22610
Figure 6-2. Characteristics of MOS Memory Product Types
Memories are no longer considered the only “process drivers” in the industry. That distinction is shared among memory, MPU, and ASIC devices. Intel, in the mid-1980s, made a strategic deci- sion to abandon the memory market for economic reasons. Intel probably had a good notion that it could apply state-of-the-art processing techniques to microprocessors, thus making these devices process drivers as well.
Feature Size
The most critical issue in the advancement of IC technology is feature size; more specifically, the progression to reduced feature sizes every few years. Today’s processes require considerable process adjustment with each feature size reduction. In addition, each new generation of memory usually requires one or two additional mask layers. Figure 6-3 shows the past and projected fea- ture sizes for DRAMs and several other experimental devices. Design rules used to build these devices has decreased from about 3.0µm in 1980 to about 0.25µm in 1997. This represents about a 14 percent decrease every year. This trend is expected to continue and feature sizes are forecast to be about 0.15µm by 2000.
Figure 6-4 shows SIA’s technology roadmap through the year 2010. As shown, the integration levels are forecast to continue along historical trend lines.
80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 96
0.01 0.1 1 10
Microns
Year 1990 Forecasted Commercial
Limit For Optical Lithography (0.35µ)
= Laboratory Reasearch
MIT (0.06µ) X-Ray Bell Labs
(0.14µ)
Toshiba (0.25µ)
IBM (0.25µ) Gate Array
(X-Ray) Loose Production Resolution
Tight Production Resolution
Development HMOS II
(2.0µ)
HMOS IV
(1.0µ) 4M DRAM (0.8µ)
16M DRAM (0.5µ)
64M DRAM (0.35µ) 256K DRAM
(1.6µ) 1M DRAM (1.2µ)
16M DRAM (0.5µ)
64M DRAM (0.35µ) 4M DRAM
(0.8µ) WE 32100
32-Bit MPU (1.5µ)
10981R Source: ICE, "Memory 1997"
95
256M DRAM (0.25µ) 256M
DRAM (0.25µ) 1992 Forecasted Commercial
Limit For Optical Lithography (0.15µ)
97 1G DRAM (0.15µ) Toshiba
(0.1µ)
Toshiba (0.04µ)
98 00 02
(2.0µ)
(1.0µ)
(0.7µ)
4G DRAM (0.08µ)
1G DRAM (0.15µ)
1996 Forecasted Commercial Limit for Optical Lithography (0.1µ)
Figure 6-3. IC Feature Size Trends
Lifecycle
As with any commercial product, memories have a lifecycle. A memory will pass through the dif- ferent steps of the lifecycle, from its introduction where the IC manufacturer concentrates on cap- ital resources and R&D efforts, to the end of its life when the product becomes obsolete.
Year of first DRAM shipment Minimum feature (µm) Memory Density Bits/chip (DRAM/flash)
Logic Density (High volume: Microprocessor) Logic transistors/cm2 (packed)
Bits/cm2 (cache SRAM)
Logic Density (Low volume: ASIC) Transistors/cm2 (auto layout) Number of Chip I/Os
Chip to package (pads) high performance Chip frequency (MHz)
On-chip clock, cost-performance On-chip clock, high-performance Chip-to-board speed, high performance Chip size (mm2)
DRAM
Microprocessor ASIC
Oxide Thickness (nm) Junction Depth (µm)
Maximum number wiring levels (logic) On-chip
Minimum mask count Power supply voltage (V) Desktop
Battery Maximum power
High performance with heatsink (W) Logic without heatsink (W/cm2) Battery
1995 0.35
64M
4M 2M
2M
900
150 300 150
190 250 450 7-12 0.1-0.2
4–5 18
3.3 2.5
80 5 2.5
1998 0.25
256M
7M 6M
4M
1,350
200 450 200
280 300 660 4-6 0.1-0.15
5 20
2.5 1.8–2.5
100 7 2.5
2001 0.18
1G
13M 20M
7M
2,000
300 600 250
420 360 750 4-5 0.07-0.13
5–6 20
1.8 0.9–1.8
120 10 3.0
2004 0.13
4G
25M 50M
12M
2,600
400 800 300
640 430 900 4-5 0.05-0.1
6 22
1.5 0.9
140 10 3.5
2007 0.10
16G
50M 100M
25M
3,600
500 1,000
375
960 520 1,100
<4
<0.07
6–7 22
1.2 0.9
160 10 4.0
2010 0.07
64G
90M 300M
40M
4,800
625 1,100
475
1,400 620 1,400
<4
<0.05
7–8 24
0.9 0.9
180 10 4.5
Driver
D
L(µP)
L(A)
L,A
µP L
µP µP
µP L
µP A
µP A L A=ASIC
L=Logic
D=DRAM
µP=Microprocessor
20286C Source: SIA/ICE, "Memory 1997"
Figure 6-4. The 15-Year SIA Roadmap
Die Size Trends
In 1975, Intel Chairman Gordon Moore predicted that engineers could shrink semiconductor device dimensions by approximately 10 percent each year, creating a new generation of chips every three years with four times as many transistors. Twenty one years later, Moore’s prediction was impressively accurate. DRAM devices actually exceeded his expectations (Figure 6-5).
Figure 6-6 shows how the die area of leading-edge memory devices has increased about 13 per- cent per year. The trend toward larger die sizes is forecast to continue. The die sizes of the 1Gbit DRAMs described at the 1995 and 1996 ISSCC conferences ranged from 901K sq. mils to 1,451K sq.
mils (Figure 6-7). As shown, the NEC 1Gbit DRAM, if square, would be about 1.2 inches on a side.
Wafer Size
The IC industry is quickly moving to the new 300mm (12 inch) wafer standard. Figure 6-8 shows the wafer area increase that occurs each time the industry moves to the next wafer size. Currently the standard for high-volume advanced IC production is 200mm (8 inch). The area gained by moving from 200mm to 300mm wafers will be 125 percent.
Advancing from one wafer size to a new, larger size takes several years of development. In fact, development time increased substantially to transition to 200mm wafers and will be the same for the transition to 300mm wafers (Figure 6-9). Companies such as Samsung, Texas Instruments, and many other leading memory suppliers have indicated their willingness to build manufacturing facilities to support 300mm wafers. The big question is which company will be the one to take on the huge headaches and huge amount of capital needed to work out all the wrinkles associated with the transition to 300mm wafers.
19972A Source: IEDM 40th Anniversary Edition, "Memory 1997"
95 90 85 80 75 70 65 60 55
Year Moore's Curves
Limit
Logic DRAM
1 1K 1M 1G
Transistors Per Chip
Figure 6-5. Growth in Chip Complexity Since 1959
1,000
100
10 60
70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 Pentium
80486
80386 68020 80286
68000
8086 Z80
8080 4K
16K
256K 1M
4M 16M
64M 1G
= Microprocessor/Logic
= Memory
Year
Chip Area (Thousands of sq mils)
64K
Memory increase = 1.13/year MPU increase = 1.13/year
11746Q Source: Intel/ICE, "Memory 1997"
20 40 80 600
200 400 800
P54C
00 02 P8?
R4000 2,000
256M IBM
Gate Array Pentium Pro MPU and Cache
Pentium Pro MPU Only P7?
Figure 6-6. IC Die Size Trends
Feature
Size (µm) Cell Size (µm2)
Density Chip Size
(K sq. mils)
Access
Time (ns) Organization Conference Company
Hyundai Matsushita Mitsubishi1 Oki2
Mitsubishi3 Samsung4 Hitachi NEC
256M 256M 256M 256M
1G 1G 1G 1G
0.3 0.25 0.25 0.25
0.14 0.16 0.16 0.25
— 0.72 0.72 0.72
0.29
— 0.29 0.54
561 638 472 530
901 1,010 1,108 1,451
36
— 34
—
32
— 33
—
32M x 8 16M x 16 32M x 8 32M x 8
—
— 64M x 16
—
ISSCC '95 ISSCC '94 ISSCC '94 ISSCC '94
ISSCC '96 ISSCC '96 ISSCC '95 ISSCC '95 1 Produced using KrF excimer-laser lithography.
2 Packaged in a 64-pin 600-mil TSOP, produced using e-beam lithography.
3 SDRAM produced using synchrotron-generated x-ray lithography.
4 SDRAM produced using KrF excimer-laser lithography.
20289A Source: ICE, "Memory 1997"
Figure 6-7. ISSCC Advanced DRAMs
Defect Density
The cost to manufacture ICs is governed by many factors. One of the most important is the number of good dice per wafer started into the wafer fab. This number is dependent on the number of potential dice per wafer, and the number of defective dice.
0 50 100 150 200
,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
125 56
78
125 78
156 125
56
Wafer Diameter Transition
100mm → 125mm 100mm → 150mm 125mm → 200mm 150mm → 200mm 200mm → 250mm
Percent Increase
Source: ICE, "Memory 1997" 18603A
250mm → 300mm 200mm → 300mm 300mm → 400mm 300mm → 450mm
44
Figure 6-8. Wafer Area Increases (Percent)
100mm
8 years (EST) 5 years 3 years 3 years 3 years
125mm
150mm
200mm
300mm
Source: Rose Associates/ICE, "Memory 1997" 21192
Figure 6-9. Wafer Development Time Requirements (Time to Reach 100 MSI Production Rate)
Figure 6-10 shows the potential number of dice for various wafer sizes. The number of potentially good dice per wafer is dependent on the wafer size and the die size. The number of defective dice on a wafer are the result of random killer defects, usually expressed in defects per square cen- timeter, and the number of defective dice caused by parametric defects. In a world class fab, the number of dice lost because of parametric defects is very low.
As shown in Figure 6-11, random killer defects have a dramatic effect on the number of good dice per wafer, especially as the die size increases. Figure 6-12 shows the yield effect of various defect densities versus die size, where the yield is defined as the number of good dice divided by the number of potential dice.
Defect density control is extremely important for memory fabs since the cell array area in a memory IC contains extremely compact circuitry. Each generation (256Kbit, 1Mbit, 4Mbit, etc.) of memory chip is about 50 percent larger than the previous with four times the number of bits of storage.
As feature sizes become smaller, ICs are susceptible to smaller and smaller particles causing random killer defects. This means that if everything else remains constant, the killer defect den- sity will increase as smaller particulates become killer defects. Yield also decreases with increas- ing die sizes. Therefore, to maintain acceptable yields, extreme care must be taken to reduce particulates in the ambient air, the equipment, the process gases, and the process liquids.
Fab processes themselves generate particulates that can cause defects. In modern processes, each process step is given a defect “budget” for the number of defects per square centimeter added for the step. As the number of process steps increases, the job of reducing the defect density becomes more and more difficult.
Redundancy
As mentioned earlier, the effect of defect density on memory chips is a much larger problem than with most other products due to the circuit density in the storage cell array. Nearly any particu- late-caused defect in this area is a killer defect. To enhance memory chip yields, manufacturers use spare rows and columns (redundant rows and columns) that can replace defective rows or columns. During 100 percent wafer probe, defective rows and columns are “replaced” by these spares through the use of laser blown fuses that alter the decode mechanism. When external sig- nals try to access a defective row or column, the decode circuitry selects a spare one instead.
Figure 6-13 shows a simplified logic of redundancy programming. A normal decoder contains half as many decoding transistors as a redundant decoder. If redundancy is not required—that is, the chip is perfect—spare decoders will be deselected regardless of the input address.
DIE AREA mil x1000
2
mm2 3-INCH 100mm 125mm 150mm 200mm 10.0
12.1 14.4 16.9 19.6 22.5 25.6 28.9 32.4 36.1 40.0 44.1 48.4 52.9 57.6 62.5 67.6 72.9 78.4 84.1 90.0 96.1 102.4 108.9 115.6 122.5 129.6 136.9 144.4 152.1 160.0 168.1 176.4 184.9 193.6 202.5 211.6 220.9 230.4 240.1 250.0 260.1 270.4 280.9 291.6 302.5 313.6 324.9 336.4 348.1 360.0 372.1 384.4 396.9 409.6 422.5 435.6 448.9 462.4 476.1 490.0 504.1 518.4 532.9 547.6 562.5 577.6 592.9 608.4 624.1 640.0
6.5 7.8 9.3 10.9 12.6 14.5 16.5 18.6 20.9 23.3 25.8 28.5 31.2 34.1 37.2 40.3 43.6 47.0 50.6 54.3 58.1 62.0 66.1 70.3 74.6 79.0 83.6 88.3 93.2 98.1 103.2 108.5 113.8 119.3 124.9 130.6 136.5 142.5 148.6 154.9 161.3 167.8 174.5 181.2 188.1 195.2 202.3 209.6 217.0 224.6 232.3 240.1 248.0 256.1 264.3 272.6 281.0 289.6 298.3 307.2 316.1 325.2 334.5 343.8 353.3 362.9 372.6 382.5 392.5 402.6 412.9
mils mm
100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 460 470 480 490 500 510 520 530 540 550 560 570 580 590 600 610 620 630 640 650 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800
2.5 2.8 3.0 3.3 3.6 3.8 4.1 4.3 4.6 4.8 5.1 5.3 5.6 5.8 6.1 6.3 6.6 6.9 7.1 7.4 7.6 7.9 8.1 8.4 8.6 8.9 9.1 9.4 9.7 9.9 10.2 10.4 10.7 10.9 11.2 11.4 11.7 11.9 12.2 12.4 12.7 13.0 13.2 13.5 13.7 14.0 14.2 14.5 14.7 15.0 15.2 15.5 15.7 16.0 16.3 16.5 16.8 17.0 17.3 17.5 17.8 18.0 18.3 18.5 18.8 19.0 19.3 19.6 19.8 20.1 20.3 DIE SIZE**
AREA
508 432 356 300 256 216 188 164 148 132 120 112 96 88 80 76 68 60 52 52 52 44 44 40 32 32 32 32 32 24 24 24 24 24 16 16 16 16 16 12 12 12 12 12 12 12 12 12 12 12 12 12 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
936 780 656 548 468 416 360 316 284 256 224 208 188 164 148 148 120 120 112 96 96 88 80 76 76 68 60 52 52 52 52 52 44 44 40 32 32 32 32 32 32 32 24 24 24 24 24 24 24 16 16 16 16 16 16 16 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
1,528 1,272 1,060 904 780 688 600 524 460 416 376 332 308 284 256 240 208 200 188 164 156 148 140 120 120 112 112 96 96 88 80 80 76 76 68 68 60 52 52 52 52 52 52 44 44 40 40 32 32 32 32 32 32 32 32 24 24 24 24 24 24 24 24 24 16 16 16 16 16 16 16
2,276 1,892 1,576 1,348 1,152 1,012 880 780 688 616 556 500 456 424 384 356 324 300 276 256 240 224 208 192 188 164 156 148 148 140 120 120 112 112 104 96 96 88 88 80 76 76 76 68 68 68 60 52 52 52 52 52 52 52 44 44 44 40 40 32 32 32 32 32 32 32 32 32 32 24 24 CANDIDATE NUMBER OF WHOLE DICE
4,168 3,444 2,892 2,480 2,136 1,844 1,640 1,444 1,280 1,148 1,036 936 864 780 716 656 608 556 524 476 448 424 392 376 340 332 308 292 268 256 248 240 216 208 208 188 188 180 164 156 148 148 148 132 120 120 120 112 112 112 104 96 96 88 88 88 80 80 76 76 76 68 68 68 68 60 60 52 52 52 52 Corner of die at center of full radius wafer.
3mm band around edge of wafer not used.
Size after die separation, 3 mil saw kerf.
*
**
8317D Source: ICE, "Memory 1997"
300mm 9,700 8,040 6,772 5,784 4,992 4,344 3,828 3,388 3,024 2,692 2,448 2,212 2,000 1,836 1,688 1,560 1,428 1,328 1,232 1,148 1,060 1,012 936 880 820 780 732 688 656 616 600 556 540 508 492 460 440 432 392 392 376 356 340 332 316 308 292 284 268 256 256 248 240 224 216 208 208 200 188 188 180 180 164 164 156 156 148 148 148 148 132
Figure 6-10. Die Size Versus Die Count*
8 Good Dice Out of 16 = 50%
1 Good Die Out of 4 = 25%
0 Good Die Out of 1 = 0%
7438B Source: ICE, "Memory 1997"
Figure 6-11. Effect of Die Size on Yield
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360
Defect Density
100 90 80 70 60 50 40 30 20 10 0
YIELD (Percent)
DIE SIZE (sq mm) 3.00
1.502.00 1.00 0.50 0.20 0.10 0.05 0.02 0.01
32 62 93 124 155 186 217 248 279 310 341 372 403 434 465 496 527 558 DIE SIZE
(thousands of sq mils)
where A = die area in cm2 D = defect density per cm2 y = AD
2
Source: ICE, "Memory 1997" 14444K
1996 4M DRAM
1996 16M DRAM
1996 P54CS
1996 64M DRAM
1 – ε –AD
Figure 6-12. Murphy’s Probe Yield Model (As a Function of Defects per sq cm)
Process Complexity
Process complexity is usually measured by the number of critical mask layers, plus any special processes that may have a detrimental effect on yield. As feature sizes have become smaller, struc- tures under the surface of the silicon wafer have become more shallow. The structures above the wafer surface have remained relatively thick. The thicker interconnect layers are the result of the need to separate the conductive layers as much as possible, thus reducing the capacitive loading of the long thin conductors (polysilicon and aluminum) running the length and width of the chip.
If the deposited dielectric films are reduced in thickness, the parasitic capacitive load will increase, and the device will be considerably slower.
Several manufacturers have lowered the effect of parasitic capacitance through the use of materi- als with lower dielectric constants. Polyimide is one such material. The dielectric constant of polyimide is below 3.0, versus 3.9 for deposited silicon dioxide. The improvement in reduced par- asitic capacitance is a linear function with respect to dielectric constant.
VDD
VDD Chip
Enable, CE
A , A
o o A , An n
Laser Programmable
Link
VDD
VDD
Ao Ao An An
CE
SPARE DECODER
17612 Source: ICE, "Memory 1997"
Figure 6-13. Row Decode for Redundancy
Although the number varies somewhat from vendor to vendor, over twenty critical mask steps are required to produce today’s most advanced memory chips. Each new generation requires one or two additional mask layers. Each mask layer is composed of ten to twenty actual process opera- tions, some major and some minor.
With today’s processes composed of hundreds of steps, the requirement for tight process control on each step is critical. When processes are planned, budgets are established for process varia- tions at each process step. These budgets are modeled and used to predict manufacturability.
Uniformity across the die, across the wafer, from wafer to wafer, and from wafer lot to wafer lot can be predicted.
The size of memory chips is obviously very dependent on the size of a single memory cell.
Reducing the feature size reduces the cell (storage area for one bit) somewhat, but there are por- tions of the cell that do not reduce with feature size. To continue the reduction of cell area, designs are now utilizing three-dimensional structures. These will be described later in the various prod- uct descriptions, but in all cases, the addition of these structures leads to additional process steps.
POWER SUPPLY
Two factors are driving the reduction in memory operating voltages: power dissipation and process geometries. The market for low-voltage devices is growing fast, and IC manufacturers are concentrating significant R&D efforts to develop low-voltage versions of their memory ICs.
Power Dissipation
The demand for low power dissipation comes from two main factors. First, system and package power constraints demand lower operating voltage due to higher board integration and the use of more integrated chips.
Systems with dual power supplies (5V and 3.3V) consume system space and require careful inter- face design between the two supplies. For this reason, system manufacturers push ICs suppliers to produce low voltage devices so that they can design single low-voltage supply systems. Figure 6-14 shows the market transition from 5V to 3V systems.
The second reason for the rise in low-power ICs comes from growth in the portable electronics market including portable computers and digital cellular phones. This equipment requires low power and low voltage to increase battery life. Dissipation drops 36 percent when going from 5.5V to 3.3V, for example. Using 2.7V in a typical digital cellular phone design could extend talk time by 25 percent over 3.3V operation. Figure 6-15 shows 5V to 3.3V power savings in a typical notebook computer.
An extra incentive for designing 3.3V ICs is the U.S. government’s EPA Energy Star Program.
According to the EPA, computer systems account for five percent of commercial electricity con- sumption in the United States. Energy Star mandated energy reduction in any PC the federal gov- ernment purchased.
0 10 20 30 40 50 60 70 80 90 100
2000 1999 1998 1997 1996 1995 1994 1993 1992 1991 1990
Year
Source: VLSI Technology/ICE, "Memory 1997" 19179A
5V
3V
5/3V
2.xV
Percentage of Design Starts
Figure 6-14. Transition from 5V to 3V Systems
Notebook Computer System Components
Typical 5V Power
(W)
Power at 3.3V Logic
(W)
Expected 3.3V Power
(W) Power (W) at 5V
Logic Other Functions CPU Plus Core Logic
System Memory
Display Controller Subsystem LCD Panel Plus Backlight Hard-Disk Drive*
Miscellaneous Circuits DC/DC Conversion Total System Power
2.20 0.50 1.50 0.30 0.20 0.50 0.00
0.00 0.00 0.00 3.20 0.30 0.00 1.70
2.20 0.50 1.50 3.50 0.50 0.50 1.70 10.40
0.95 0.22 0.65 0.13 0.09 0.21 0.00
0.95 0.22 0.65 3.33 0.39 0.21 1.20 6.95
*Hard-disk drive power estimates reflect a mix of active and idle time.
Source: Cirrus Logic/Electronic Products/ICE, "Memory 1997" 19217
Figure 6-15. 3.3V Logic Power Savings in a Typical Notebook Computer
Process Geometries
For memory devices to become increasingly dense, feature sizes must shrink. Both gate oxides and gate lengths need lower voltage to avoid an increase in electrical field (Figures 6-16 and 6-17).
For a similar process on a given generation, 3.3V parts have longer access times than 5V parts.
Figure 6-18 gives the supply voltage decrease versus the technology and the memory density.
Unfortunately, it is more difficult to yield high-speed devices for low voltage ICs than it is for high voltage parts. Figure 6-19 shows a typical schmoo plot of the access time versus power supply.
DRAMs
During 1994, there was a significant ramping-up of low-voltage DRAMs (Figure 6-20). ICE fore- casts that in the year 2002, more than 95 percent of all DRAMs sold will be classified as low-volt- age (3.3V or lower).
Some PC manufacturers have delayed shifting to pure 3.3V motherboard designs because price premiums for 3.3V DRAMs would negatively impact the cost of their system. However, during 1996, all major DRAM suppliers were making the transition to 3.3V at the 16Mbit DRAM level.
160
140
120
100
80
60
40
20
0
0 0.1 0.2 0.3 0.4 0.5 0.6
Gate Length (µm)
Gate Oxide Thickness (Å)
Published Data Trend Line
20284A Source: Intel/ICE, "Memory 1997"
Figure 6-16. Gate Oxide Versus Gate Length
Price parity between 5V and 3.3V devices should quickly ensue. 64Mbit DRAMs are proposed only at the 3.3V level. The upcoming 256Mbit DRAM will operate internally at around 2.5V but will interface to 3.3V.
Certain drawbacks exist for DRAMs operating at lower internal voltages. For instance, it is more difficult to read the charge on a cell capacitor when a lower voltage is stored on the capacitor. The cell is also more susceptible to errors due to ground bounce (electrical noise) caused by the simul- taneous reading of several hundred cells at one time.
SRAMs
Advanced SRAMs are shifting to 3.3V technology even though there is a speed penalty versus a comparable 5V part. In terms of data sensitivity (i.e., noise immunity, alpha particles), the 6T CMOS cell is the best design. The benefits of a TFT (Thin Film Transistor) cell are described in Section 8. One additional benefit of the TFT is reduced power consumption. However, due to process complexity, most SRAM manufacturers stay away from this design.
ROMs
ROM technology is not necessarily state-of-the-art, but these products are moving to lower volt- age operation like the other memory technologies. Several manufacturers have proposed low- voltage ROMs. Sharp offers 16Mbit and 32Mbit ROMs with power supplies ranging from 2.7V to 3.6V. Other ROM makers such as AMI, Hitachi, and Ricoh also offer low-voltage ROMs.
6
5
4
3
2
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6
Published Data Trend Line
Operating Voltage (V)
Gate Length (µm)
20285A Source: Intel/ICE, "Memory 1997"
Figure 6-17. Gate Length Versus Operating Voltage
EPROMs
The development of high-density EPROMs has slowed due to the evolution of flash memories.
However, like other technologies, low-voltage parts are available. The low-voltage supply is only used for read operations. High voltages are required for the write operations (Figure 6-21).
EEPROMs
EEPROMs must internally generate high voltage for write/erase operations. The VCC power supply affects the internal high voltage supply (VPP). Low-voltage parts are much more complex.
There is, however, a need for low-power parts in applications such as digital cellular phones. 2.7V to 3.6V power supply EEPROM devices are available from several vendors.
1K 4K 16K 64K 256K 1M 4M 16M 64M 256M
1M/4M 16M 32M 64M 256M
1G
10
1
0.1
12V
5V
3.3V
1.5V
1970 1980 1990 2000
Process Technology
Year
Supply Voltage
8µm
5µm 3µm
2µm
1.3µm 0.8µm
0.5µm
0.35µm
0.25µm
0.15µm
Source: Hitachi, "Memory 1997" 20872A
256 1K 4K 16K 64K 256K 1M 4M 4M 16M 64M
DRAM SDRAM FLASH 1992/1993 1994 1995 1996 1999
Figure 6-18. Technology Roadmap/Wafer Process
