SECTION 1
INTRODUCTION TO THE DSP56002
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SECTION CONTENTS
1.1 INTRODUCTION . . . 1-3 1.2 FEATURES . . . 1-4
1.3 DSP56K CENTRAL PROCESSING UNIT OVERVIEW. . . 1-4
1.4 MANUAL ORGANIZATION . . . 1-5
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INTRODUCTION
1.1 INTRODUCTION
This manual describes the DSP56002 24-bit digital signal processor, its memory and
op-erating modes, and its peripheral modules. It is intended to be used with the DSP56K
Central Processing Unit Manual (DSP56KFAMUM/AD), which describes the central
pro-cessing unit, programming models, and includes details of the instruction set. The
DSP56002 Technical Data Sheet (DSP56002/D) provides timing, pinout, and packaging
descriptions (see Figure 1-1).
This section presents the DSP56002 features.
Central Processor and
• central processor • instruction set Device Manual • peripherals • memories Specification • electrical • mechanical Products 24-bit DSP56002 DSP56002 Technical Data # DSP56002/D # DSP56KFAMUM/AD DSP56000 Family Manual # DSP56002UM/AD DSP56002 User’s Manual Instruction Manual
Figure 1-1 DSP56002 Technical Literature
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FEATURES
1.2 FEATURES
DSP56K Central Processing Unit (CPU) Features
• 20 Million Instructions per Second (MIPS) at 40 MHz
• Single-Cycle 24 x 24 Bit Parallel Multiply-Accumulator
• Highly Parallel Instruction Set with Unique DSP Addressing Modes
• Zero Overhead Nested DO Loops
• Fast Auto-Return Interrupts
• Fully Static Logic, Operation Frequency Down to DC
• Very Low-power CMOS Design
• STOP and WAIT Low-power Standby Modes
DSP56002 Features
• 512 x 24 Program RAM
• Two 256 x 24 Data RAM
• Two 256 x 24 Data ROM (Sine and Cosine Tables)
• Full Speed Memory Expansion Port with 16-bit Address and 24-bit Data Buses
• Byte-wide Host Interface with DMA Support
• Synchronous Serial Interface Port
• Serial Communication Interface (Asynchronous) Port
• 24 General Purpose I/O Pins
• 24-bit Timer/Event Counter*
• On-chip Emulator (OnCE) for Unobtrusive, Full Speed Debugging
• Optional Program Security Feature Disables Unauthorized Program ROM and
OnCE Access
• PLL Based Clocking with Wide Input Frequency Range, Wide Range Frequency
Multiplication (1 to 4096) and Power Saving Clock Divider (2i, i=0,...,15) to
Reduce Clock Noise
1.3 DSP56K CENTRAL PROCESSING UNIT OVERVIEW
The DSP56K series of 24-bit modular processors is built on a common central processing unit (CPU). In the expansion area around the CPU, the chip can support various configu-rations of memory and peripheral modules which may change between series members.
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MANUAL ORGANIZATION
The central components are:
• Data Buses
• Address Buses
• Data Arithmetic Logic Unit (data ALU)
• Address Generation Unit (AGU)
• Program Control Unit (PCU)
• Memory Expansion (Port A)
Figure 1-2 shows a block diagram of the DSP56002, including the CPU and the expansion
area for memory and peripherals. The DSP56000 Family Manual(DSP56KFAMUM/AD)
presents the details of each of the above CPU components. 1.4 MANUAL ORGANIZATION
This manual includes the following sections:
SECTION 2 — PIN DESCRIPTIONS presents the DSP56002 pinout.
SECTION 3 — MEMORY MODULES AND OPERATING MODES presents the details of the DSP56002 memory maps and explains the various operating modes that affect the processor’s program and data memories.
SECTION 4 — PORT A describes the external memory port, its registers, and control signals.
SECTION 5 — PORT B describes the port B parallel I/O and the host interface, their reg-isters, and their controls.
SECTION 6 — PORT C describes the port C parallel I/O, the Synchronous Serial Inter-face, the Synchronous Communication InterInter-face, their registers, and their controls. SECTION 7 — DSP56002 TIMER AND EVENT COUNTER describes the timer/counter and its registers and controls.
APPENDIX A — BOOTSTRAP PROGRAM APPENDIX B — PROGRAMMING SHEETS
TROUBLE REPORT — This trouble report is a form that allows the reader to notify the factory of any errors or discrepancies discovered in this manual.
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MANUAL ORGANIZATION CLOCK GENERATOR INTERNAL DATA BUS SWITCH PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLER PROGRAM ADDRESS GENERATOR YAB XAB PAB YDB XDB PDB GDB CONTROL DATA ALU 24X24+56→56-BIT MAC TWO 56-BIT ACCUMULATORS
EXTERNAL ADDRESS BUS SWITCH BUS CONTROL EXTERNAL DATA BUS SWITCH ADDRESS D ATA 16 BITS 24 BITS POR T A PLL ADDRESS GENERATION UNIT OnCE EXPANSION AREA CONTR OL 24-Bit 56K CPU
Figure 1-2 DSP56002 Block Diagram
Program Control Unit
X MEMORY RAM 256X24 µ/A ROM 256X24 Y MEMORY RAM 256X24 SINE ROM 256X24 SSI INTERFACE SCI INTERFACE 6 15 3 5 CLOCK 16 10 24 4 PROGRAM 512x24 RAM BOOTSTRAP 64x24 ROM HOST INTERFACE 2
