Full Length Article
Low voltage high performance hybrid full adder
Pankaj Kumar
*
, Rajender Kumar Sharma
National Institute of Technology, Kurukshetra, India
A R T I C L E I N F O Article history:
Received 16 July 2015 Received in revised form 14 September 2015 Accepted 7 October 2015 Available online 27 October 2015 Keywords: High speed Low voltage Logic structure Hybrid adder A B S T R A C T
This paper presents a low voltage and high performance 1-bit full adder designed with an efficient in-ternal logic structure that leads to have a reduced Power Delay Product (PDP). The modified NOR and NAND gates, an essential entity, are also presented. The circuit is designed with cadence virtuoso tool with UMC 90-nm and 55-nm CMOS technologies. The proposed adder is compared with some of the popular adders based on power consumption, speed and power delay product. The proposed full adder cells achieve 56% and 76.69% improvement in speed and power delay product metric when compared with conven-tional C-CMOS full adder. It is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.
Copyright © 2015, The Authors. Production and hosting by Elsevier B.V. on behalf of Karabuk University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/ licenses/by-nc-nd/4.0/).
1. Introduction
The explosive growth of battery operated portable applica-tions such as cellular phones, smart cards, PDAs, laptops and the evolution of the shrinkage of the technology requires smaller silicon area, high throughput circuitry and most importantly low power
[1–3]. Power consumption of any system can be reduced by scaling the supply voltage and operating frequency. But, it increases the propagation delay of the system and degrade the driving
capabil-ity of the design[4,5]. Therefore, designing a full adder with
improved power delay characteristics is of great interest. Digital Signal Processing (DSP) is an important unit in electron-ic develectron-ices. DSP based processors are used to perform the operations such as video processing, filtering and fast Fourier transform (FFT). Such modules perform extensive sequence of addition/subtraction, multiplication and division computations. Addition is the most
fun-damental operation in arithmetic circuits[6,7]. Full adders are
encountered in the critical path of the complex arithmetic circuit
like multiplication, division and address calculations[8–13]. These
are the core elements of any system and can significantly influ-ence the performance of any system. That is why enhancing the performance of the 1-bit adder cell can enhance the overall system
performance[11,14,15].
Several logic styles have been used in the past to implement the full adder cell. Each logic style has its own advantages and disad-vantages. Standard static CMOS full adder (C-CMOS) is based on
regular CMOS structure with pull up and pull down transistors. This adder provides full output voltage swing against voltage and tran-sistor sizing. The limitations of this design are its larger area and slower speed due to the availability of PMOS devices and larger input
capacitance of the static CMOS logic gates[16]. On the other hand,
complementary pass transistor logic (CPL) is fast and also
pro-vides full voltage swing output[17]. CPL adder is based on dual rail
structure and requires 32 transistors. But it has larger power con-sumption because of the presence of static inverter and lot of internal
nodes[18,19]. The other adders are designed using hybrid logic styles
and are called hybrid adder. These adders are designed with a com-bination of more than one logic style to enhance the overall performance of the system. The main focus of hybrid logic style is to reduce the number of transistors and power dissipating nodes of the adder cell. Hybrid pass logic with static CMOS (HPSC) is an example of hybrid adder. HPSC provides full output voltage swing and has good output drive capability. The limitation of this adder
is its higher propagation delay[20]. On the other hand, hybrid adder
is a good choice in terms of power consumption and speed than HPSC but at the cost of increased number of transistors in the design
[21]. However, hybrid CMOS full adder is faster than HPSC at all
supply voltages. But its delay is increased with varying the load[1].
Full adder proposed in Reference2is designed with less
tran-sistors and consumes lesser amount of power. But it fails to provide full swing output voltage when operated at low voltages. This results into deteriorated signals and degradation in speed tremendously with the scaling of the supply voltage. In this adder, signals have higher rise and fall time at lower voltages and it makes the design inefficient at the scaled technology.
The internal logic structure based on transmission function theory
is proposed in Reference22to build the full adder cell as shown
inFig. 1. It consists of three main blocks to obtain the sum and carry
* Corresponding author. Tel.:+919996578201, fax: +911744238050. E-mail address:[email protected](P. Kumar). Peer review under responsibility of Karabuk University. http://dx.doi.org/10.1016/j.jestch.2015.10.001
2215-0986/Copyright © 2015, The Authors. Production and hosting by Elsevier B.V. on behalf of Karabuk University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
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Engineering Science and Technology,
an International Journal
j o u r n a l h o m e p a g e : h t t p : / / w w w. e l s e v i e r. c o m / l o c a t e / j e s t c h
Press: Karabuk University, Press Unit ISSN (Printed) : 1302-0056 ISSN (Online) : 2215-0986 ISSN (E-Mail) : 1308-2043
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outputs. Block 1 has XOR/XNOR gate to generate
(
A⊕B)
and(
A⊕B)
’signals and block 2 and block 3 are used as XOR blocks or multi-plexers to obtain the sum and carry outputs. This structure has been adopted by many researchers as a standard structure for design-ing the 1 bit full adder cells. Some of the popular designs are
described in References18,23–25. But the major problem of the
module reported in Reference22is the presence of intermediate
signals
(
A⊕B)
and(
A⊕B)
’[26,27]. These intermediate signals areused to drive the output blocks or multiplexers and therefore re-sponsible for higher propagation delay and power consumption.
To reduce the overall propagation delay and power consump-tion a new full adder cell is designed with internal logic structure. The proposed structure uses inputs signal C and its complement C’ to drive the output multiplexers in place of the intermediate signal
A⊕B
(
)
and its complement(
A⊕B)
’. The logic structure designedwith input signal C also helps in reducing the overall hardware cost of the design. This logic structure consists of XOR/XNOR gates, modi-fied NOR and NAND gates with multiplexers inserted at the output. Multiplexers are used to select the sum and carry outputs. The re-sultant full adder exhibits improved PDP compared to earlier reported adder designs. Proposed design also has full output swing and is found suitable when operated at lower voltages.
The rest of the paper is organized as follows.Section 2
intro-duces the proposed internal logic structure to build the 1-bit high
speed full adder cell.Section 3describes simulation test bench. The
simulation results and comparison of the entire referred and
pro-posed full adder cells are presented in section 4. Voltage and
temperature analysis of the proposed design is carried out insection
5.Section 6draws the conclusion.
2. Implementing 1-bit full adder with proposed internal logic structure
In the proposed structure, the selection of sum and carry outputs are made under the control of input signal C. This signal is not gen-erated internally and therefore provides full output voltage swings with no additional delay. It has good driving capability and used to drive the multiplexers at the output of the full adder cells. Based on this logic structure and using Swing Restored Complementary Pass transistor Logic (SR-CPL) new full adder is proposed. The block diagram of the proposed 1 bit full adder designed with internal logic
structure is shown inFig. 2. It is designed after analysing the truth
table of full adder cell as shown inTable 1. The transistors
sche-matic of the proposed design is shown inFig. 3.
InFig. 3(a.1–a.3) three basic CMOS inverter are shown which gives the complement output of the input signals A, B and C in the form
of A’ B’ and C’ respectively. SimilarlyFig. 3(b) represents the
SR-CPL based XOR gate and its complement in the form of XNOR gate.
A and B are the input signals applied on these gates. InFig. 3(c) and
(d) modified NOR and modified NAND gates are shown. Multiplex-ers required for generating the sum and carry outputs are shown inFig. 3(e.1) and (e.2). Transmission gates are used for designing the multiplexers. The proposed full adder cell is realized using the
logic structure ofFig. 3.
The modified NOR and modified NAND gates “as essential
en-tities” are also proposed and shown inFig. 3(c) and (d). A’ and
(
A⊕B)
are the inputs applied on NOR gate and outputs are shown in the
form of
[
A’+(
A⊕B)
]
’. Similarly B’ and(
A⊕B)
’are the inputs appliedon NAND gate and output are shown in the form of
[
B’.(
A⊕B)
’ ’]
.Due to this input combinations proposed NOR and proposed NAND gates require only three transistors. This makes the proposed design faster, compact and power saving. The operation of the modified
NOR and NAND gates are described inTables 2 and 3respectively.
The output combinations of these gates are selected by the output multiplexers to generate the final carry output.
After analysing the logic structure, it is obvious that Sum output
is equal to
(
A⊕B)
when C is 0 and becomes equal(
A⊕B)
’when Cis 1. Similarly, carry output is equal to
[
A’+(
A⊕B)
]
’when C is 0 andbecomes equal to
[
V’.(
A⊕B)
’ ’]
when C is 1. Therefore, thisopti-mized structure successfully operates under the control of input signal C. Hence, the proposed logic approach is faster due to the pres-ence of signal C. This signal reduces the overall delay and power consumption of the proposed designs. In addition to this, the ca-pacitive load of this signal C is also reduced as it is connected only to some transistor gates. Reductions in power consumption and prop-agation delay further improve the PDP of the proposed adder as compared with existing adders. Power consumption and propaga-tion delay can be minimized further by sizing the XOR/XNOR, Block 1 Block 2 Block 3 A Ci B Sum Cout
Fig. 1. Full adder module based on three logic blocks.
Table 1
Truth table of 1-bit full adder.
A B C SUM Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Multiplexer Multiplexer A C B’ Sum Cout HA B (A+B)’ [A’ +( A B)]’+ [B’.( A+B)’]’
Fig. 2. Proposed internal logic structure for designing the 1-bit full adder cell.
Table 2
Truth table of modified NOR gate. A’ (A⊕B) [A’+(A⊕B)]’ 0 0 1 0 1 0 1 0 0 1 1 0 Table 3
Truth table of modified NAND gate. B’ (A⊕B)’ [B’.(A⊕B)’ ’]
0 0 1
0 1 1
1 0 1
modified AND/OR gates and multiplexers accordingly. The sizing of the transistors is also helpful in balancing the propagation delay in the output and also reduces the glitches in cascaded applications.
3. Simulation test bench
Bhattacharyya et al.[2]used simulation test bench shown inFig. 4
to simulate the full adder circuits. The limitations of this structure are that all the input test patterns are applied only to the first adder cell and remaining adder cells are not tested properly. Secondly, the power consumed by each adder is different. On the other hand, each
Couthas two fan-out while sum output has only one fan-out.
There-fore, full adder is not properly loaded in this structure.
The structure shown inFig. 5is used successfully by the
re-searchers for the analysis of previous designs[1,27,28]and it is free
from the limitation of test bench described above. This test bench is used for the performance comparison of referred and proposed
full adders. The transistor sizes of each buffers is shown inFig. 5.
Buffers are inserted at all the inputs and output of the Device Under Test (DUT) to simulate in the real time environment. The sizes of the input buffer are chosen such that leads to experience suffi-cient signal distortion as expected in actual circuit. The sizes of the input buffers are chosen such that it leads to experience sufficient signal distortion as expected in actual circuit. The performances of DUT are calculated in terms of power dissipation, worst case delay and power delay product. Some input transitions do not change the output but some internal node has switching during that time. This switching activity leads to power dissipation. Therefore, entire input test patterns that can fairly test all the cases are considered for ac-curate result in this work. The delay is observed from 50% of voltage level of input to 50% of voltage level of resulting output for all the rise and fall transitions. For power delay product calculations worst case delay is chosen to be the larger delay amongst the sum and carry outputs. A B B’ B B’ A’ Sum Cout B B’ C C’ (A B)+ A’ A (A+B)’ A’ B (A B)+ A’ B’ (A B)’+ B’ A A’ A C C C C C’ C’ (A B)+ (A+B)’ Fig . 3 (a.1) Fig . 3 (a.2) Fig . 3 (a.3) Fig . 3 (b) Fig . 3 (c) Fig . 3 (d) Fig . 3 (e.1) Fig . 3 (e.2) [A’+(A B)]’+ [B’.(A B)’]’+ [A’+(A B)]’+ [B’.(A B)’]’+
Fig. 3. Full adder designed with proposed logic structure.
A
B
C
SumIn A
In B
In C
CoutA
B
C
Sum CoutA
B
C
Sum CoutSum
Cout
4. Simulation results and comparison
The simulation of the circuits C-CMOS, HPSC, Hybrid, Hybrid CMOS and proposed full adder are carried out with UMC 90-nm tech-nology and UMC 55-nm techtech-nology using cadence virtuoso tool. All the adders are simulated using the common test bench by the spectre simulator. The simulations are performed on varying supply voltage ranging from 0.4 V to 1.2 V. The maximum operating frequency is set at 100 MHz. The size of each full adder is taken as the same as those reported in literature. The proposed full adder (without test bench and with test bench) designed with internal structure is com-pared in terms of power consumption, propagation delay and Power Delay Product (PDP) with the existing full adders at UMC 90-nm
technology and UMC 55-nm technology as shown inTables 4–6
re-spectively. Full adder without test bench means analysing the full adder without having buffers at the input and without having buffers and capacitance at the output. In other word, full adder analysed under no-load condition. Similarly, Full adder with test bench means analysing the full adder with buffers inserted at the input and output in addition of the capacitance inserted at the output. In other word, full adder was analysed under load condition.
The proposed full adder (without test bench) achieves 69.36% reduction in propagation delay and 43.32% improvement in power delay product than the C-CMOS full adder when simulated with UMC 90-nm technology and 1.2 V. Similarly, proposed full adder (with test bench) achieves up to 56.95% reduction in propagation delay and 44.73% improvement in power delay product than the C-CMOS full adder when simulated with UMC 90-nm technology and 1.2 V. In addition to this, proposed full adder (with test bench) achieves up to 56% reduction in propagation delay and 76.69%
improve-ment in power delay product than the C-CMOS full adder when simulated with UMC 55-nm technology and 1.0 V. It was observed
that the power consumption and propagation delay can be tuned further by sizing the transistors individually in the proposed designs. During the simulation of adders at low voltages ranging from 0.4 V to 1.2 V, it is observed that the full adder HPSC fail at a supply voltage of 0.4 V in case of both UMC 90-nm and UMC 55-nm technologies while the remaining adders operates successfully at this supply
voltage as shown inTables 4–6. The lowest voltage at which HPSC
can operate successfully at 100 MHz is 0.6 V. The values of propa-gation delay and power-delay-product of the referred and proposed full adder cells simulated at UMC 90-nm technology (without test bench and with test bench) are evaluated by cadence under
differ-ent voltage as shown inFigs. 6–9respectively. Similarly, the values
of propagation delay and power-delay-product of the referred and proposed full adder cells simulated at UMC 55-nm technology (with test bench) are evaluated by cadence under different voltage as
shown inFigs. 10 and 11. These curves show that the proposed adder
cells are robust against voltage variation and also have minimum power-delay-product. The proposed adder operates successfully on low voltages and provides full output voltage swing and thus ex-hibits smaller power delay product at low voltages. This makes the proposed design a good candidate for low voltage and high speed VLSI applications. A B C Sum In A In B In C 6.4 f F 5 10 4 Cout 3
Fig. 5. Simulation Test bench.
Table 4
Power, delay and power-delay-product comparison of full adders (without test bench) in 90-nm technology at different voltages.
VDD(V) 0.4 0.6 0.8 1.0 1.2 Power Consumption (μW) C-CMOS[16] 0.1956 0.4528 0.8329 1.453 2.447 HPSC[20] — 0.4143 0.7765 1.258 2.172 Hybrid[21] 0.1543 0.353 0.6795 1.25 2.448 Hybrid CMOS[1] 0.2031 0.4377 0.811 1.492 2.664 Proposed 0.2818 0.6935 1.365 2.549 4.527 Delay (pS) C-CMOS[16] 896.6 234.4 131.8 97.4 81.93 HPSC[20] — 163 97.97 72.98 60.66 Hybrid[21] 546.6 164.6 99.83 75.82 75.5 Hybrid CMOS[1] 1558 256.6 95.89 60.62 46.94 Proposed 216.8 68.44 43.34 31.81 25.1 Power-delay-Product (aJ) C-CMOS[16] 175.374 106.136 109.776 141.522 200.482 HPSC[20] — 67.530 76.073 91.808 131.753 Hybrid[21] 84.340 58.103 67.834 94.775 184.824 Hybrid CMOS[1] 316.429 112.313 77.766 90.445 125.048 Proposed 61.094 47.463 59.159 81.083 113.627
Power, delay and power-delay-product comparison of full adders (with test bench) in 90-nm technology at different voltages.
VDD(V) 0.4 0.6 0.8 1.0 1.2 Power Consumption (μW) C-CMOS[16] 0.3624 0.8615 1.584 2.564 3.846 HPSC[20] — 0.9207 1.652 2.44 3.481 Hybrid[21] 0.3194 0.7672 1.419 2.285 3.389 Hybrid CMOS[1] 0.3647 0.8427 1.531 2.457 3.647 Proposed 0.4442 1.076 2.038 3.42 4.938 Delay (pS) C-CMOS[16] 1078 269.6 158.1 108.0 89.53 HPSC[20] — 206.2 117.7 87.13 72.05 Hybrid[21] 765.3 205.5 116.7 86.12 71.16 Hybrid CMOS[1] 2319 392.9 138.8 81.2 60.78 Proposed 432.9 109.2 64.74 48.98 38.54 Power-delay-Product (aJ) C-CMOS[16] 390.667 232.260 234.590 276.912 344.332 HPSC[20] — 189.848 194.440 212.597 250.806 Hybrid[21] 244.436 157.659 165.597 196.784 241.161 Hybrid CMOS[1] 845.739 331.096 212.502 199.5084 221.665 Proposed 192.294 117.499 131.940 167.511 190.310 Table 6
Power, delay and power-delay Product comparison of full adders (with test bench) in 55-nm technology at different voltages.
VDD(V) 0.4 0.6 0.8 1.0 Power Consumption (μW) C-CMOS[16] 0.574 1.357 2.508 4.152 HPSC[20] — 0.650 1.205 1.734 Hybrid[21] 0.225 0.550 1.036 1.703 Hybrid CMOS[1] 0.263 0.623 1.154 1.885 Proposed 0.2713 0.6612 1.274 2.199 Delay (pS) C-CMOS[16] 1071 189.8 85.47 56.41 HPSC[20] — 139.4 50.46 45.44 Hybrid[21] 954.8 179.1 85.07 58.15 Hybrid CMOS[1] 2718 325.8 120.8 62.28 Proposed 440.3 79.76 34.63 24.82 Power-delay-Product (aJ) C-CMOS[16] 615.396 257.558 214.358 234.214 HPSC[20] — 90.735 60.804 78.792 Hybrid[21] 215.689 98.522 88.132 99.029 Hybrid CMOS[1] 716.464 203.103 139.403 117.397 Proposed 119.453 52.737 44.118 54.579
Fig. 12shows the layout of the proposed full adder (excluding buffers and output capacitance) in UMC 55-nm technology. Cadence virtuoso layout editor has been used for designing the layout. DRC and LVS analyses are carried out using Caliber of Mentor-graphics tool. The presented full adder uses only two metal lines. The layout
area is calculated and found to be 77.07 μm2.
5. Voltage and temperature analysis
In highly scaled technology, voltage and temperature varia-tions can significantly affect the performance of the digital circuits. To investigate the effect of the same, leakage current variability of the proposed full adder cell are estimated. Temperature is varied
from−47 °C to +47 °C and supply voltage is varied from 0.4 V to 1.4 V.
The variation found in calculated leakage current ranges in nA when operated at 1.0 V, which is negligible. It is also observed that the leakage current variability decreases with the decrease in temper-ature and increases with the increase in tempertemper-ature. The
corresponding graph is shown inFig. 13. This shows the robustness
Fig. 6. Delay of the full adder cells (without test bench) in 90-nm technology for
different supply voltages.
Fig. 7. Delay of the full adder cells (with test bench) in 90-nm technology for
dif-ferent supply voltages.
Fig. 8. Power-delay-product of the full adder cells (without test bench) in 90-nm
technology for different supply voltages.
Fig. 9. Power-delay-product of the full adder cells (with test bench) in 90-nm
tech-nology for different supply voltages.
Fig. 10. Delay of the full adder cells (with test bench) in 55-nm technology for
of the proposed full adder cell against temperature and supply voltage variations.
6. Conclusion
In this paper, l-bit high performance full adder cells based on efficient internal logic structure have been presented. Spectre simu-lations are carried out on cadence environment using UMC 90-nm and 55-nm technologies to evaluate the new design and existing designs. Results show that the proposed design has high perfor-mance and best PDP in comparison with many existing full adder cells. Consequently, this new design is found appropriate at low volt-ages and has good output levels. This shows that proposed design can be a good choice in the future at scaled technology or nano-scaling. It is also verified through simulation results that the proposed design perform well under the projected variations in supply voltage and temperature.
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