Ao-90265ba Pci Card

Full text

(1)AO-90265 PCIIO-II: Data Interface FPGA for Generation II of PCI I/O Card. (MO-12899 & MO-13022) Revision BA Spec No.: Author: SSH File name: AO-90265BA.doc. Division: Burny Rev: BA Date: 13 NOV 2001. This document is the property of Cleveland Motion Controls, Inc. and is furnished as confidential information only. It must not be copied, traced or reproduced in any manner nor submitted to any outside parties for any purpose without our written permission. Any use of this document without written permission of Cleveland Motion Controls, Inc. is a violation of our exclusive rights..

(2) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. REVISION HISTORY Rev. ECO. Author. Date. AA Pre1. ---. SSH. 30-OCT-2001. AA Pre 2. ---. SSH. 13-NOV-2001. AA Pre 3. ---. DJM. 20-Dec-2001. AA Pre 4. ---. SSH. 7-Jan-2002. AA Pre 5. ---. SSH. 23-Jan-2002. AA Pre 6. ---. SSH. 07-Feb-2002. AA Pre 7. ---. DJM. 15-Mar-2002. AA Pre 8. ---. SSH. 25-Jun-2002. AA Pre 9. ---. SSH. 21-Sep-2002. AA Pre 10. ---. SSH. 24-Sep-2002. AA. ---. SSH. 20-Jan-2003. BA. CLE2427. SSH. 30-Jan-2003. Description of Change Preliminary draft of specification. Started with base design of PCIIO-1 (MO-12068) revision 1.9. Delete GPIO banks A, B and C with I/O control lines. Add two more quadrature encoder inputs -- 7 & 8. Add ‘new value’ to quadrature encoder index registers. Add two more analog outputs. Change ADC interface to dedicated SPI interface and registers for each channel. Change generic SPI interface for use with one device. Add PC16552 UART lines, with chip selects and interrupts. Change outputs that drive the opto’s from active high to active low. Rearrange register addresses. Change DUART to SC28L92 from Philips. Updated changes to add in the 16550 cells and updating the register map to reflect design changes in implementation. System clock rate now sourced from the PCI controller 33MHz output Change GP3 register to EIP1 and relocated to 0x4A. Created EIP0 at 0x48. Moved ADC and DAC Control registers to fit in EIP0 and EIP1. Updated address map. Change RELAYYOFF pin to open-drain with internal pull-up. Put in missing FPGA pin-out. Add register 0x7A and pin descriptions for generalpurpose bi-directional I/O. Updated register map including the sub counters Update register 0x40 WC(5:0) read back value and change 0x4C DRC(6:0) to DRC(5:0). Reorder ADC registers to make FPGA coding simpler. Remove selection number of ADC in 0x4E register. General revisions and added detail. Per input from Morelli: More detail for ADC registers when NADC < 7. Remove UART scratch registers to save gates. Release as version 2.0 Corrected glitches on ADC outputs caused when the application software updated the register currently being written out by the firmware (version 2.1 – not released). Changed GPO22 to ignore resets by ESTOP and watchdog timeouts. This output is used to select RS232 or RS422 from the application software. Released as version 2.2.. Page 2 of 46. AO-90265BA.

(3) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. TABLE OF CONTENTS PAGE Overview ............................................................................................................................................................4 Typical PCIIO-II Card Block Diagram ..............................................................................................................5 PCIIO-II Block Diagram ....................................................................................................................................6 PCIIO-II Pin Descriptions (208 pins).................................................................................................................7 Bus Interface (33 pins) ..................................................................................................................................7 System Control (5 pins).................................................................................................................................9 I2C Bus Interface (2 pins) ............................................................................................................................10 SPI Bus Interface (5 pins)............................................................................................................................10 Quadrature Encoder Inputs (24 pins)...........................................................................................................11 Serial ADC Interface (4 pins) ......................................................................................................................12 Serial DAC Interface (6 pins) ......................................................................................................................12 General Purpose Bi-directional (8 pins) ......................................................................................................13 General Purpose Outputs (32 pins)..............................................................................................................13 General Purpose Inputs and Buffer Chip Enables (7 pins) ..........................................................................14 SRAM Interface (3 pins) .............................................................................................................................14 DUART Interface (10 pins) .........................................................................................................................14 Unused (4 pins)............................................................................................................................................15 JTAG Port (4 pins) ......................................................................................................................................15 Special Pins (9 pins) ....................................................................................................................................15 Power Supplies (52 pins).............................................................................................................................16 PCIIO-II Register Descriptions ........................................................................................................................18 Quadrature Encoder Count Registers ..........................................................................................................18 Quadrature Encoder Index Registers ...........................................................................................................20 Configuration and Control Registers ...........................................................................................................24 Digital Analog Converter (DAC) Data Registers ........................................................................................29 Analog Digital Converter (ADC) Data Registers ........................................................................................30 SPI Bus Interface Registers .........................................................................................................................32 General Purpose Input (GPI) Data Registers ...............................................................................................32 General Purpose Input/Output (GPIO) Interface Registers .........................................................................33 General Purpose Output (GPO) Data Registers...........................................................................................33 Quadrature Encoder Sub-Count Registers...................................................................................................34 DUAL 16550 UARTs ......................................................................................................................................40 UART0 ........................................................................................................................................................40 UART1 ........................................................................................................................................................43 Battery Backed SRAM Description .................................................................................................................45 SRAM Address Space .................................................................................................................................45 PCIIO-II Card Address Map ............................................................................................................................46 Package ............................................................................................................................................................46. Page 3 of 46. AO-90265BA.

(4) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. Overview The PCIIO-II chip is designed using modern high density field programmable gate array (FPGA) technology, high level hardware description language, and logic synthesis. It provides: a programmable periodic interrupt source; eight 24-bit quadrature encoders; an SPI bus; dedicated serial DAC interface capable of controlling up to eight 16-bit DACs; dedicated serial, 8-channel, 12-bit ADC interface and over 80 bits of general purpose I/O. The PCIIO-II also provides for the control signals for a 128-kbyte battery backed SRAM and has two integrated 16550 UART.s. When combined with a PCI bridge chip the PCIIO-II creates a low cost, reliable PCI bus based data acquisition and control card.. Page 4 of 46. AO-90265BA.

(5) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. Typical PCIIO-II, Data Interface For Generation-II PCI Card FPGA. Isolated +/-15V Supplies In Serial-1. Serial-2. (TTL). (TTL). Connector. Connector. Primary I/O Connector Axes 1-4. Isolated +5V Supply. Secondary I/O Connector Axes 5-8. Silicon Serial # & Temperature Sensor. Inter-Board Connector. Parallel I/O Connector DAC & ADC. Dual. PCIIO-II FPGA. UART. Battery Backed SRAM 128Kx8. Optical Isolation. Keypad Interface Circuit. 2.5V Supply PCI. 5-Wire Touch Screen Connector. Bridge Touch Screen Controller Circuit. Chip 5V & 3.3V PCI Supplies Intra -Cabinet I/O Connector (Legacy). Membrane Keypad Connector USB Connector. PCI Connector. Card Block Diagram. Page 5 of 46. AO-90265BA.

(6) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. PCIIO-II, Data Interface For Generation-II PCI Card FPGA Block. Local Bus. DUART. SRAM Timing & WE generation. Serial DAC. Serial ADC. General Purpose. Interface. Interface. Outputs. Quadrature. Timer. General Purpose. Interface. Encoder Interface. Serial Bus 2 (SPI and I C) Interface. Inputs. Clock Generation. IEEE 1149.1 Boundary Scan. Diagram. Page 6 of 46. AO-90265BA.

(7) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. PCIIO-II, Data Interface For Generation-II PCI Card FPGA Pin Descriptions (208 pins) The FPGA uses low-level, 3.3V, TTL signaling. Unless otherwise noted all pins are 5V TTL logic level compatible. Minimum valid input high voltage is 2.0V, maximum valid input low voltage is 0.8V. Output drive capability for high output is -24 mA at 2.4V and for low output is 24 mA at 0.4V; however, currents should be kept to minimum to reduce ground bounce within the part. For the Type field, I is input, O is output, OZ is tristate output, OD is open drain output, IO is bi-directional, and P is power. All pins which have the letter ‘N’ as the final character in the pin name are considered to be active low. For pins with internal pull up or down resistors, the values may range from 50K to 100K.. Bus Interface (33 pins) The CPU Bus Interface is designed to connect directly to the local bus created by a PCI bridge chip. Name Pin Type Description A7 3 I Bus Address Bit 7 A6 4 I Bus Address Bit 6 A5 5 I Bus Address Bit 5 A4 6 I Bus Address Bit 4 A3 7 I Bus Address Bit 3 A2 8 I Bus Address Bit 2 A1 9 I Bus Address Bit 1 These input pins are connected to the bus address. D15 42 IO Local Bus Data Bit 15 D14 41 IO Local Bus Data Bit 14 D13 37 IO Local Bus Data Bit 13 D12 36 IO Local Bus Data Bit 12 D11 35 IO Local Bus Data Bit 11 D10 34 IO Local Bus Data Bit 10 D9 33 IO Local Bus Data Bit 9 D8 31 IO Local Bus Data Bit 8 D7 30 IO Local Bus Data Bit 7 D6 29 IO Local Bus Data Bit 6 D5 27 IO Local Bus Data Bit 5 D4 24 IO Local Bus Data Bit 4 D3 23 IO Local Bus Data Bit 3 D2 22 IO Local Bus Data Bit 2 D1 21 IO Local Bus Data Bit 1 D0 20 IO Local Bus Data Bit 0 These bi-directional pins are connected to the CPU data bus. BHEN 15 I Byte High Enable This active low input pin indicates that the byte corresponding to D[15:8] should be accessed. BLEN 16 I Byte Low Enable This active low input pin indicates that the byte corresponding to D[7:0] should be accessed. CSN 10 I Chip Select This active low input is the chip select for the PCIIO-II, it is connected to a chip select generated by the PCI bridge. ADSN 14 I Address Strobe. Page 7 of 46. AO-90265BA.

(8) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. LWR. 17 I. LRDYN. 47 O. LIRQ1. 46 O. LIRQ2. 43 O. LRESETN. 75 I. LCLK. 77 I. This active low input pin is the local bus address strobe which indicates the start of new bus cycle, asserted during the first clock of a bus access. Local Bus Write/Read This input pin is high for bus write cycles, low for bus read cycles. Local Bus Ready This active low output pin indicates that the PCIIO-II, Data Interface For Generation-II PCI Card FPGA is ready to complete the requested bus cycle. Local Bus Interrupt Request 1 This active high output is the PCIIO-II, Data Interface For Generation-II PCI Card FPGA interrupt request. Local Bus Interrupt Request 2 This active high output is the DUART interrupt request. Local Bus System Reset This active low input is the master reset signal for the PCIIO-II, Data Interface For Generation-II PCI Card FPGA. Clock Input This is the clock for use by the PCIIO-II, Data Interface For GenerationII PCI Card FPGA, it must be a fixed frequency and is used to determine the bus timing, interrupt and watchdog timing, SPI, DAC and ADC serial port timing, and the quadrature encoder data filter timing. A 33.3 MHz frequency is assumed in this document.. Page 8 of 46. AO-90265BA.

(9) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. System Control (5 pins) These pins perform special functions required by the system. Name Pin Type Description RELAYOFF 69 OD Relay Off Output This active high signal is used to indicate when the relay to the external machine should be turned off. This output is active if a watchdog timeout occurs or the main system controller is in a stop state waiting for the user to cycle the STOPPBN pin. This pin is forced active by LRESETN or chip configuration and will remain active until a write is performed to the Watchdog & Serial Number Control Register. This pin has an internal pull up resistor. STOP 192 I Stop This active high input indicates an abnormal condition in the system and causes the PCIIO-II, Data Interface For Generation-II PCI Card FPGA to hold all of its registers in the reset state until a low to high transition is seen on the STOPPBN input. This pin has an internal pull up resistor. STOPPBN 191 I Stop Push Button A low to high transition on this pin is required to clear error conditions in the chip. QSMS 48 I Quadrature Sync Master/Slave This input pin selects slave (low) or master (high) mode for the quadrature synchronization pin. QSYNC 140 IO Quadrature Synchronization The direction of this active high pin is determined by the QSMS pin. In master mode the quadrature encoder latch signal generated by the interrupt timer is output onto this pin. In slave mode the internal quadrature latch signal comes in from this pin (the internal interrupt timer can still generate an interrupt, but it is not used to latch the quadrature encoders).. Page 9 of 46. AO-90265BA.

(10) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. I2C Bus Interface (2 pins) This interfaces allows I2C devices to be accessed under software control. The PCIIO-1 used this for an X24001 EEPROM that is now obsolete. The PCIIO-II, Data Interface For Generation-II PCI Card FPGA card uses this interface for a DS1624 Digital Thermometer with EEPROM. Name Pin Type Description SCLN 58 O Serial Clock This active low output pin connects to an inverter to drive an I2C twowire bus clock line. SDA 57 IO Serial Data This bi-directional pin connects directly to the data bus of I2C devices.. SPI Bus Interface (5 pins) This interface allows the PCIIO-II, Data Interface For Generation-II PCI Card FPGA to communicate with a device that uses the Serial Peripheral Interconnect (SPI) bus. Note: The PCIIO-1 supported two SPI devices. One was the 8-channel ADC and the other was a front panel device (currently not in use). With the PCIIO-II, Data Interface For Generation-II PCI Card FPGA, only one generic SPI device is supported. The ADC interface is now a dedicated sub-system. Name Pin Type Description SPIDON 139 O Serial Data Out This active low output pin is the transmitted data to the SPI device. SPIDI 135 I Serial Data In This input pin is the received data from the SPI device. SPICLKN 136 O Serial Clock This active low output pin is the clock to the SPI device. SPICSN 138 O Serial Chip Select This active low output pin is the chip select for the SPI device. RESETN 49 O Reset This active low output is the reset for any devices which require it. It is controlled by software.. Page 10 of 46. AO-90265BA.

(11) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. Quadrature Encoder Inputs (24 pins) This interfaces allows up to 8 quadrature encoders to be connected to the PCIIO-II, Data Interface For Generation-II PCI Card FPGA. The counter clock rate is programmable, and the resolution or each encoder is 20 bits. Index pulse is defined as a rising edge on QExCHA while QExIDX is high. If the IDXMODE bit is set, index is defined as a rising edge on QExIDX followed by a rising edge on QECHA. The quadrature encoder counter will count up on a rising edge on QExCHA while QExCHB is low, a rising edge on B while A is high, a falling edge on A while B is high, or a falling edge on B while A is low. The counters will count down on a rising edge of B with A low, a rising edge on A with B high, a falling edge on B with A high, or a falling edge on A with B low. Additionally, each encoder input pins is registered so that it can be used as a general-purpose input pin or for advanced encoder troubleshooting and testing. Encoder inputs for channels 1-4 are registered in EIP0 and inputs for channels 5-8 are registered in EIP1. Name Pin Type Description QE1CHA 168 I Quadrature Encoder 1 - Channel A (EIP0, bit 0) QE1CHB 167 I Quadrature Encoder 1 - Channel B (EIP0, bit 1) QE1IDX 166 I Quadrature Encoder 1 - Index (EIP0, bit 2) These inputs are for quadrature encoder 1. To prevent them from floating when unconnected, these pins should have an external pull up/down resistor. QE2CHA QE2CHB QE2IDX. 165 I 164 I 163 I. Quadrature Encoder 2 - Channel A (EIP0, bit 3) Quadrature Encoder 2 - Channel B (EIP0, bit 4) Quadrature Encoder 2 - Index (EIP0, bit 5) These inputs are for quadrature encoder 2. To prevent them from floating when unconnected, these pins should have an external pull up/down resistor.. QE3CHA QE3CHB QE3IDX. 162 I 161 I 160 I. Quadrature Encoder 3 - Channel A (EIP0, bit 6) Quadrature Encoder 3 - Channel B (EIP0, bit 7) Quadrature Encoder 3 - Index (EIP0, bit 8) These inputs are for quadrature encoder 3. To prevent them from floating when unconnected, these pins should have an external pull up/down resistor.. QE4CHA QE4CHB QE4IDX. 152 I 151 I 150 I. Quadrature Encoder 4 - Channel A (EIP0, bit 9) Quadrature Encoder 4 - Channel B (EIP0, bit 10) Quadrature Encoder 4 - Index (EIP0, bit 11) These inputs are for quadrature encoder 4. To prevent them from floating when unconnected, these pins should have an external pull up/down resistor.. QE5CHA QE5CHB QE5IDX. 189 I 188 I 187 I. Quadrature Encoder 5 - Channel A (EIP1, bit 0) Quadrature Encoder 5 - Channel B (EIP1, bit 1) Quadrature Encoder 5 – Index (EIP1, bit 2) These inputs are for quadrature encoder 5. To prevent them from floating when unconnected, these pins should have an external pull up/down resistor.. Page 11 of 46. AO-90265BA.

(12) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). QE6CHA QE6CHB QE6IDX. 181 I 180 I 179 I. Quadrature Encoder 6 - Channel A (EIP1, bit 3) Quadrature Encoder 6 - Channel B (EIP1, bit 4) Quadrature Encoder 6 – Index (EIP1, bit 5) These inputs are for quadrature encoder 6. To prevent them from floating when unconnected, these pins should have an external pull up/down resistor.. QE7CHA QE7CHB QE7IDX. 178 I 176 I 175 I. Quadrature Encoder 7 - Channel A (EIP1, bit 6) Quadrature Encoder 7 - Channel B (EIP1, bit 7) Quadrature Encoder 7 – Index (EIP1, bit 8) These inputs are for quadrature encoder 7. To prevent them from floating when unconnected, these pins should have an external pull up/down resistor.. QE8CHA QE8CHB QE8IDX. 174 I 173 I 172 I. Quadrature Encoder 8 - Channel A (EIP1, bit 9) Quadrature Encoder 8 - Channel B (EIP1, bit 10) Quadrature Encoder 8 – Index (EIP1, bit 11) These inputs are for quadrature encoder 8. To prevent them from floating when unconnected, these pins should have an external pull up/down resistor.. Serial ADC Interface (4 pins) This interface allows the PCIIO-II, Data Interface For Generation-II PCI Card FPGA to communicate with a MAX1202 Analog-to-Digital converter that uses a Serial Peripheral Interconnect (SPI) bus interface. The interface is tailored to continuously cycle through the ADC channels at the highest possible conversion rate timing. Name Pin Type Description ADCDON 86 O Serial Data Out to ADC This active low output pin is the transmitted data to the ADC device. ADCDI 87 I Serial Data In from ADC This input pin is the received data from the ADC device. ADCCLKN 83 O Serial Clock to ADC This active low output pin is the clock to the ADC device. ADCCSN 84 O Serial Chip Select This active low output pin is the chip select for the ADC device.. Serial DAC Interface (6 pins) This interface allows up to (4) serial interface dual DACs to be connected to the PCIIO-II, Data Interface For Generation-II PCI Card FPGA. Name Pin Type Description SDCLKN 148 O Serial DAC Clock This active low output provides the clock to the serial DACs. SDDATAN 149 O Serial DAC Data This active low output provides the data to the serial DACs. SDSELAN 141 O Serial DAC Select A This active low output provides the channel select to serial DAC–A, channels 1 and 2. SDSELBN 142 O Serial DAC Select B. Page 12 of 46. AO-90265BA.

(13) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. SDSELCN. 146 O. SDSELDN. 147 O. This active low output provides the channel select to serial DAC–B, channels 3 and 4. Serial DAC Select C This active low output provides the channel select to serial DAC–C, channels 5 and 6. Serial DAC Select D This active low output provides the channel select to serial DAC–D, channels 7 and 8.. General Purpose Bi-directional (8 pins) Name GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0. Pin 206 205 204 203 202 201 200. Type IO IO IO IO IO IO IO. GPIODIR. 185 I. Description General Purpose I/O bit 6 General Purpose I/O bit 5 General Purpose I/O bit 4 General Purpose I/O bit 3 General Purpose I/O bit 2 General Purpose I/O bit 1 General Purpose I/O bit 0 These bi-directional pins are available for use as input or output pins as needed. These pins have a weak (~50K) internal pull-up. GPIO Direction This active high input pin causes the GPIO pins to become inputs.. General Purpose Outputs (32 pins) Name GPO31 GPO30 GPO29 GPO28 GPO27 GPO26 GPO25 GPO24 GPO23 GPO22 GPO21 GPO20 GPO19 GPO18 GPO17 GPO16 GPO15 GPO14 GPO13 GPO12 GPO11 GPO10 GPO9 GPO8 GPO7 GPO6. Pin 134 133 132 129 127 126 125 123 122 121 120 119 115 114 113 112 111 110 109 108 102 101 100 99 98 97. Type O O O O O O O O O O O O O O O O O O O O O O O O O O. Description General Purpose Output 31 General Purpose Output 30 General Purpose Output 29 General Purpose Output 28 General Purpose Output 27 General Purpose Output 26 General Purpose Output 25 General Purpose Output 24 General Purpose Output 23 General Purpose Output 22 General Purpose Output 21 General Purpose Output 20 General Purpose Output 19 General Purpose Output 18 General Purpose Output 17 General Purpose Output 16 General Purpose Output 15 General Purpose Output 14 General Purpose Output 13 General Purpose Output 12 General Purpose Output 11 General Purpose Output 10 General Purpose Output 9 General Purpose Output 8 General Purpose Output 7 General Purpose Output 6. Page 13 of 46. AO-90265BA.

(14) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). GPO5 GPO4 GPO3 GPO2 GPO1 GPO0. 96 95 94 90 89 88. O O O O O O. General Purpose Output 5 General Purpose Output 4 General Purpose Output 3 General Purpose Output 2 General Purpose Output 1 General Purpose Output 0 These output pins are used as general purpose outputs.. General Purpose Inputs and Buffer Chip Enables (7 pins) These pins are used to control the enables of external 74HCT224 or 74LS224 type buffers, each chip enable is assumed to be connected to a pair of octal buffer devices to form a 16 bit input port which drives the local bus when enabled. Name Pin Type Description GPICS0N 59 O General Purpose Input Port Chip Select 0 GPICS1N 60 O General Purpose Input Port Chip Select 1 GPICS2N 61 O General Purpose Input Port Chip Select 2 These active low output pins are fully decoded chip selects (including strobe timing) for external 16 bit wide input port buffers. UIP0 193 I User Input Pin 0 UIP1 194 I User Input Pin 1 UIP2 195 I User Input Pin 2 UIP3 199 I User Input Pin 3 This is a 4-bit general-purpose user input. These inputs have internal pull-ups.. SRAM Interface (3 pins) This optional interface allows a single 8 bit wide static RAM chip to be connected to the PCIIO-II, Data Interface For Generation-II PCI Card FPGA chip. The address base and size of the SRAM is programmable in the PCI bridge chip. Name Pin Type Description SRAMCSIN 18 I SRAM Chip Select In This active low input is the chip select input for an optional external SRAM chip. This pin is driven by the PCI bridge chip. SRAMCSN 44 O SRAM Chip Select This active low output is the chip select output for an optional external SRAM chip. SRAMWEN 45 O SRAM Write Enable This active low output is the write enable for an optional external SRAM chip.. DUART Interface (10 pins) The following pins are for the dual integrated U16550 cells. The cells support only the CTS/RTS and OUT1 modem pins. Name Pin Type Description RXDATA0 81 I UART RX data UART0 RXDATA1 82 I UART RX data UART1 This is the RX data for the dual UARTs. If the UART(s) are not used then the pin needs a pull-up. CTS0N 62 I Clear to send UART0. Page 14 of 46. AO-90265BA.

(15) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). CTS1N. 63 I. TXDATA0 TXDATA1. 73 O 74 O. RTS0N RTS1N. 70 O 71 O. OUT1N0 OUT1N1. 67 O 68 O. Clear to send UART1 This is the clear to send modem control signal for the integrated dual 16550s. If the UARTs are not used then the inputs need a pull-up. UART TX data UART0 UART TX data UART1 This is the TX data for the dual UARTs. Ready to send UART0 Ready to send UART1 This is the ready to send modem output for the integrated dual 16550s. OUT1N output UART0 OUT1N output UART1 This is the modem OUT1 output for the dual 16550s.. Unused (4 pins) These pins are not connected in the FPGA. Name Pin Type Description NC1 55 U No Connect NC2 56 U No Connect GCLK0 GCLK2. 80 I 182 I. Global Clock 0 or User Input Global Clock 2 or User Input. JTAG Port (4 pins) This is an industry standard IEEE1149.1 (JTAG) boundary scan test access port. Pin Type Description Name TDI 159 I JTAG Test Data Input TDO 157 OZ JTAG Test Data Output TMS 2 I JTAG Test Mode Select TCLK 207 I JTAG Clock These pins provide an industry standard IEEE1149.1 (JTAG) Boundary Scan port. The TDI and TCLK pins should be grounded if this interface is not used.. Special Pins (9 pins) These pins are reserved and should not be connected unless otherwise noted. Name Pin Type Description M0 52 I Mode 0 M1 50 I Mode 1 M2 54 I Mode 2 These pins are grounded for normal (master serial configuration) FPGA configuration. DONE 104 IO Done PROGN 106 I Program DIN 153 I Program Data In CCLK 155 O Program Clock INITN 107 IO Program Memory Initialization DOUT 154 O Data Out. Page 15 of 46. AO-90265BA.

(16) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). These pins are used during PCIIO-II, Data Interface For Generation-II PCI Card FPGA configuration, see the FPGA chip documentation for details.. Power Supplies (52 pins) These pins provide power and ground connectivity to the chip. All VCCINT pins must be connected to the same 2.5V power supply. For 5V tolerant TTL I/O, all VCCO pins must connect to the same 3.3V power supply. Name Pin Type Description VCCINT1 13 P VCCINT VCCINT2 28 P VCCINT VCCINT3 38 P VCCINT VCCINT4 66 P VCCINT VCCINT5 76 P VCCINT VCCINT6 91 P VCCINT VCCINT7 118 P VCCINT VCCINT8 128 P VCCINT VCCINT9 143 P VCCINT VCCINT10 171 P VCCINT VCCINT11 186 P VCCINT VCCINT12 196 P VCCINT VCCINT is 2.5V +/- 5% power supply voltage. VCCO1 12 P VCCO VCCO2 26 P VCCO VCCO3 39 P VCCO VCCO4 53 P VCCO VCCO5 65 P VCCO VCCO6 78 P VCCO VCCO7 92 P VCCO VCCO8 105 P VCCO VCCO9 117 P VCCO VCCO10 130 P VCCO VCCO11 144 P VCCO VCCO12 156 P VCCO VCCO13 170 P VCCO VCCO14 184 P VCCO VCCO15 197 P VCCO VCCO16 208 P VCCO VCCO is 3.3V +/- 5% power supply voltage. GND1 1 P Ground GND2 11 P Ground GND3 19 P Ground GND4 25 P Ground GND5 32 P Ground GND6 40 P Ground GND7 51 P Ground GND8 64 P Ground GND9 72 P Ground GND10 79 P Ground GND11 85 P Ground GND12 93 P Ground GND13 103 P Ground GND14 116 P Ground GND15 124 P Ground GND16 131 P Ground. Page 16 of 46. AO-90265BA.

(17) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24. 137 145 158 169 177 183 190 198. P P P P P P P P. Ground Ground Ground Ground Ground Ground Ground Ground Power supply ground.. Page 17 of 46. AO-90265BA.

(18) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. PCIIO-II, Data Interface For Generation-II PCI Card FPGA Register Descriptions This section describes the registers in the PCIIO-II, Data Interface For Generation-II PCI Card FPGA, which can be accessed by software. Bit numbers are shown above the register field graphic and the bit values loaded into the register upon reset is shown below. Fields marked undefined will return random values when read. Note: 1) All registers should be accessed using 16 bit transfers. 2) The ‘Base’ address is defined by the address assigned to the PCI card by the PCI bridge master plus the base address configuration of chip select 0 (CS0) of the PCI bridge chip. CS0 base address is currently configured to 0x0 and the range limited to 256 bytes (0xFF). 3) When reading the Quadrature Encoder Count and Index registers, the Low Word must be read first, and this read must be followed by a read of the High Word. Reading the High Word first, or reading the Low Word without reading the High Word next may cause the Quadrature Encoders to malfunction. 4) When reading the Encoder Sub-Count registers -- for each channel – the Denominator Low word must be read first, followed by a read of the Denominator High Word, followed by a read of the Numerator Low Word and then followed by a read of the Numerator High Word. Reading the Sub-Count registers in any other order will return incorrect data. For example, read Base + 0x80, 0x82, 0xA0 and 0xA2 for encoder channel 1; then go on to another four registers for another channel, if needed.. Quadrature Encoder Count Registers Base + 0x00 RO. Q1L: Quadrature Encoder 1 Count Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 1. 15 14 13 12 11 10 9 8 7 6 5 4 3. 2. 1. 0. 2. 1. 0. 2. 1. 0. 2. 1. 0. Q1(15:0) 15:0. Q1(15:0). Quadrature Encoder 1 Lower 16 bits. Base + 0x02 RO. Q1H: Quadrature Encoder 1 Count High Word. This register contains the upper 8 bits of the latched count for quadrature encoder 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 Undefined 3:0. Q1(19:16). Q1(23:16) Quadrature Encoder 1 Upper 4 bits. Base + 0x04 RO. Q2L: Quadrature Encoder 2 Count Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 2. 15 14 13 12 11 10 9 8 7 6 5 4 3 Q2(15:0) 15:0. Q2(15:0). Quadrature Encoder 2 Lower 16 bits. Base + 0x06 RO. Q2H: Quadrature Encoder 2 Count High Word. This register contains the upper 8 bits of the latched count for quadrature encoder 2. 15 14 13 12 11 10 9 8 7 6 5 4 3 Undefined 3:0. Q2(19:16). Q2(23:16) Quadrature Encoder 2 Upper 4 bits. Page 18 of 46. AO-90265BA.

(19) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x08 RO. Q3L: Quadrature Encoder 3 Count Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 3. 15 14 13 12 11 10 9 8 7 6 5 4 3. 2. 1. 0. 2. 1. 0. 2. 1. 0. 2. 1. 0. 2. 1. 0. 2. 1. 0. 2. 1. 0. Q3(15:0) 15:0. Q3(15:0). Quadrature Encoder 3 Lower 16 bits. Base + 0x0A RO. Q3H: Quadrature Encoder 3 Count High Word. This register contains the upper 8 bits of the latched count for quadrature encoder 3. 15. 14. 13. 12. 11. 10. 9. 8. 7. 6. 5. Undefined 3:0. Q3(19:16). 4. 3. Q3(23:16) Quadrature Encoder 3 Upper 4 bits. Base + 0x0C RO. Q4L: Quadrature Encoder 4 Count Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 4. 15 14 13 12 11 10 9 8 7 6 5 4 3 Q4(15:0) 15:0. Q4(15:0). Quadrature Encoder 4 Lower 16 bits. Base + 0x0E RO. Q4H: Quadrature Encoder 4 Count High Word. This register contains the upper 8 bits of the latched count for quadrature encoder 4. 15 14 13 12 11 10 9 8 7 6 5 4 3 Undefined 3:0. Q4(19:16). Q4(23:16) Quadrature Encoder 4 Upper 4 bits. Base + 0x10 RO. Q5L: Quadrature Encoder 5 Count Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 5. 15. 14. 13. 12. 11. 10. 9. 8. 7. 6. 5. 4. 3. Q5(15:0) 15:0. Q5(15:0). Quadrature Encoder 5 Lower 16 bits. Base + 0x12 RO. Q5H: Quadrature Encoder 5 Count High Word. This register contains the upper 8 bits of the latched count for quadrature encoder 5. 15 14 13 12 11 10 9 8 7 6 5 4 3 Undefined 3:0. Q5(19:16). Base + 0x14 RO. Q5(23:16) Quadrature Encoder 5 Upper 4 bits. Q6L: Quadrature Encoder 6 Count Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 6. 15 14 13 12 11 10 9 8 7 6 5 4 3 Q6(15:0) 15:0. Q6(15:0). Quadrature Encoder 6 Lower 16 bits. Page 19 of 46. AO-90265BA.

(20) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x16 RO. Q6H: Quadrature Encoder 6 Count High Word. This register contains the upper 8 bits of the latched count for quadrature encoder 6. 15. 14. 13. 12. 11. 10. 9. 8. 7. 6. 5. Undefined 3:0. Q6(19:16). 4. 3. 2. 1. 0. 2. 1. 0. 2. 1. 0. 2. 1. 0. 2. 1. 0. 2. 1. 0. Q6(23:16) Quadrature Encoder 6 Upper 4 bits. Base + 0x18 RO. Q7L: Quadrature Encoder 7 Count Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 7. 15. 14. 13. 12. 11. 10. 9. 8. 7. 6. 5. 4. 3. Q7(15:0) 15:0. Q7(15:0). Quadrature Encoder 7 Lower 16 bits. Base + 0x1A RO. Q7H: Quadrature Encoder 7 Count High Word. This register contains the upper 8 bits of the latched count for quadrature encoder 7. 15 14 13 12 11 10 9 8 7 6 5 4 3 Undefined 3:0. Q7(19:16). Q7(23:16) Quadrature Encoder 7 Upper 4 bits. Base + 0x1C RO. Q8L: Quadrature Encoder 8 Count Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 8. 15 14 13 12 11 10 9 8 7 6 5 4 3 Q8(15:0) 15:0. Q8(15:0). Quadrature Encoder 8 Lower 16 bits. Base + 0x1E RO. Q8H: Quadrature Encoder 8 Count High Word. This register contains the upper 8 bits of the latched count for quadrature encoder 8. 15. 14. 13. 12. 11. 10. 9. 8. 7. 6. 5. Undefined 3:0. Q8(19:16). 4. 3. Q8(23:16) Quadrature Encoder 8 Upper 4 bits. Quadrature Encoder Index Registers Base + 0x20 RO. Q1IL: Quadrature Encoder 1 Index Low Word. This register contains the lower 16 bits of the latched index for quadrature encoder 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 Q1I(15:0) 15:0. Q1I(15:0). Quadrature Encoder 1 Index Lower 16 bits. Page 20 of 46. AO-90265BA.

(21) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x22 RO. Q1IH: Quadrature Encoder 1 Index High Word. This register contains the upper 8 bits of the latched index for quadrature encoder 1. 15. 14. 13. 12. Q1N. 11. 10. 9. 8. 7. 6. 5. Undefined. 4. 3. 2. 1. 0. Q1I(23:16). 3:0. Q1I(19:16). Quadrature Encoder 1 Index Upper 4 bits. 15. Q1N. Quadrature Encoder 1 New Index Value bit. This bit is set every time a Quadrature Encoder 1 Index register value is latched and is cleared after every read of the register.. Base + 0x24 RO. Q2IL: Quadrature Encoder 2 Index Low Word. This register contains the lower 16 bits of the latched index for quadrature encoder 2. 15 14 13 12 11 10 9 8 7 6 5 4 3. 2. 1. 0. 1. 0. Q2I(15:0) 15:0. Q2I(15:0). Quadrature Encoder 2 Index Lower 16 bits. Base + 0x26 RO. Q2IH: Quadrature Encoder 2 Index High Word. This register contains the upper 8 bits of the latched index for quadrature encoder 2. 15. 14. 13. 12. Q2N. 11. 10. 9. 8. 7. 6. 5. Undefined. 4. 3. 2. Q2I(23:16). 3:0. Q2I(19:16). Quadrature Encoder 2 Index Upper 4 bits. 15. Q2N. Quadrature Encoder 2 New Index Value bit. This bit is set every time a Quadrature Encoder 2 Index register value is latched and is cleared after every read of the register.. Base + 0x28 RO. Q3IL: Quadrature Encoder 3 Index Low Word. This register contains the lower 16 bits of the latched index for quadrature encoder 3. 15 14 13 12 11 10 9 8 7 6 5 4 3. 2. 1. 0. 1. 0. Q3I(15:0) 15:0. Q3I(15:0). Quadrature Encoder 3 Index Lower 16 bits. Base + 0x2A RO. Q3IH: Quadrature Encoder 3 Index High Word. This register contains the upper 8 bits of the latched index for quadrature encoder 3. 15. 14. 13. Q3N. 12. 11. 10. 9. 8. 7. Undefined. 6. 5. 4. 3. 2. Q3I(23:16). 3:0. Q3I(19:16). Quadrature Encoder 3 Index Upper 4 bits. 15. Q3N. Quadrature Encoder 3 New Index Value bit. This bit is set every time a Quadrature Encoder 3 Index register value is latched and is cleared after every read of the register.. Page 21 of 46. AO-90265BA.

(22) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x2C RO. Q4IL: Quadrature Encoder 4 Index Low Word. This register contains the lower 16 bits of the latched index for quadrature encoder 4. 15 14 13 12 11 10 9 8 7 6 5 4 3. 2. 1. 0. 1. 0. Q4I(15:0) 15:0. Q4I(15:0). Quadrature Encoder 4 Index Lower 16 bits. Base + 0x2E RO. Q4IH: Quadrature Encoder 4 Index High Word. This register contains the upper 8 bits of the latched index for quadrature encoder 4. 15. 14. 13. 12. Q4N. 11. 10. 9. 8. 7. 6. 5. Undefined. 4. 3. 2. Q4I(23:16). 3:0. Q4I(19:16). Quadrature Encoder 4 Index Upper 4 bits. 15. Q4N. Quadrature Encoder 4 New Index Value bit. This bit is set every time a Quadrature Encoder 4 Index register value is latched and is cleared after every read of the register.. Base + 0x30 RO. Q5IL: Quadrature Encoder 5 Index Low Word. This register contains the lower 16 bits of the latched index for quadrature encoder 5. 15 14 13 12 11 10 9 8 7 6 5 4 3. 2. 1. 0. 1. 0. Q5I(15:0) 15:0. Q5I(15:0). Quadrature Encoder 5 Index Lower 16 bits. Base + 0x32 RO. Q5IH: Quadrature Encoder 5 Index High Word. This register contains the upper 8 bits of the latched index for quadrature encoder 5. 15. 14. 13. 12. Q5N. 11. 10. 9. 8. 7. Undefined. 6. 5. 4. 3. 2. Q5I(23:16). 3:0. Q5I(19:16). Quadrature Encoder 5 Index Upper 4 bits. 15. Q5N. Quadrature Encoder 5 New Index Value bit. This bit is set every time a Quadrature Encoder 5 Index register value is latched and is cleared after every read of the register.. Base + 0x34 RO. Q6IL: Quadrature Encoder 6 Index Low Word. This register contains the lower 16 bits of the latched index for quadrature encoder 6. 15 14 13 12 11 10 9 8 7 6 5 4 3. 2. 1. 0. Q6I(15:0) 15:0. Q6I(15:0). Quadrature Encoder 6 Index Lower 16 bits. Page 22 of 46. AO-90265BA.

(23) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x36 RO. Q6IH: Quadrature Encoder 6 Index High Word. This register contains the upper 8 bits of the latched index for quadrature encoder 6. 15. 14. 13. 12. Q6N. 11. 10. 9. 8. 7. 6. 5. Undefined. 4. 3. 2. 1. 0. Q6I(23:16). 3:0. Q6I(19:16). Quadrature Encoder 6 Index Upper 4 bits. 15. Q6N. Quadrature Encoder 6 New Index Value bit. This bit is set every time a Quadrature Encoder 6 Index register value is latched and is cleared after every read of the register.. Base + 0x38 RO. Q7IL: Quadrature Encoder 7 Index Low Word. This register contains the lower 16 bits of the latched index for quadrature encoder 7. 15 14 13 12 11 10 9 8 7 6 5 4 3. 2. 1. 0. 1. 0. Q7I(15:0) 15:0. Q7I(15:0). Quadrature Encoder 7 Index Lower 16 bits. Base + 0x3A RO. Q7IH: Quadrature Encoder 7 Index High Word. This register contains the upper 8 bits of the latched index for quadrature encoder 7. 15. 14. 13. 12. Q7N. 11. 10. 9. 8. 7. 6. 5. Undefined. 4. 3. 2. Q7I(23:16). 3:0. Q7I(19:16). Quadrature Encoder 7 Index Upper 4 bits. 15. Q7N. Quadrature Encoder 7 New Index Value bit. This bit is set every time a Quadrature Encoder 7 Index register value is latched and is cleared after every read of the register.. Base + 0x3C RO. Q8IL: Quadrature Encoder 8 Index Low Word. This register contains the lower 16 bits of the latched index for quadrature encoder 8. 15 14 13 12 11 10 9 8 7 6 5 4 3. 2. 1. 0. 1. 0. Q8I(15:0) 15:0. Q8I(15:0). Quadrature Encoder 8 Index Lower 16 bits. Base + 0x3E RO. Q8IH: Quadrature Encoder 8 Index High Word. This register contains the upper 8 bits of the latched index for quadrature encoder 8. 15. 14. 13. Q8N. 12. 11. 10. 9. 8. 7. Undefined. 6. 5. 4. 3. 2. Q8I(23:16). 3:0. Q8I(19:16). Quadrature Encoder 8 Index Upper 4 bits. 15. Q8N. Quadrature Encoder 8 New Index Value bit. This bit is set every time a Quadrature Encoder 8 Index register value is latched and is cleared after every read of the register.. Page 23 of 46. AO-90265BA.

(24) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. Configuration and Control Registers The registers in this section allow the PCIIO-II, Data Interface For Generation-II PCI Card FPGA to be configured for operation, allow the silicon serial number to be read, the temperature to be read and the interrupt to be acknowledged.. WCR: Watchdog & I2C Bus Control Register. Base + 0x40 RW 15. 14. MS. TB. pin. 0. 13. 12. 11. 10. 9. 8. WC(5:0) ?. ?. ?. ?. ?. ?. 7. 6. 5. 4. 3. SC. SD. SE. TO. RST. 0. pin. 0. 0*. 0. 2. 1. 0. WTD(2:0) 0*. 0*. 0*. * These bits are reset by the hardware reset pin only and are not reset by a time out. Note: The RELAYOFF pin is active after chip reset or configuration and will remain active, ignoring transitions on the STOPPBN pin, until after the first write to this register has been performed. This allows normal operation in situations where the STOPPBN pin glitches on power up. 2:0 WTD(2:0) Watchdog Timer Duration These bits set the watchdog timer duration. Once a non-zero value is written, the timer becomes enabled and this field cannot be changed. ‘000’ = Watchdog not enabled. ‘001’ = 250 µs time out ‘010’ = 1 ms ‘011’ = 2 ms ‘100’ = 5 ms ‘101’ = 10 ms ‘110’ = 20 ms ‘111’ = 50 ms 3. RST. Front Panel Reset This bit is sets the RESETN pin to control the front panel reset. A ‘0’ sets the RESETN pin active to hold the front panel controller in reset. A ‘1’ releases the front panel from reset. Note that on system reset the front panel is held in reset.. 4. TO. Time Out This bit is set when the watch dog timer trips. All PCIIO-II, Data Interface For Generation-II PCI Card FPGA ports are held in their reset state and the RELAYOFF pin will be active until the time out is cleared by a low to high transition on STOPPBN.. 5. SE. Serial Bus Data Output Enable This bit controls the direction of the serial bus data pin. Write ‘1’ to cause the data pin to drive out (and the SD bit to control it), write ‘0’ to cause the data pin to become an input (which is read using the SD bit).. 6. SD. Serial Bus Data When the SE bit is ‘1’ this bit controls the SDA pin. Reading this bit always returns the state of the SDA pin.. 7. SC. Serial Bus Clock This bit controls the SCLN pin, write ‘1’ for force the clock low, write ‘0’ to force the clock high.. 13:8. WC(5:0). Watchdog Command Write ‘101001’ to kick the watchdog to prevent time out. Writing any other value while the watchdog is enabled will cause an immediate time out. Depending on the FPGA implementation, these may read back as all 0’s or all 1’s.. Page 24 of 46. AO-90265BA.

(25) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). 14. TB. Time Base This bit toggles LCLKfrequency/166 times per second (every 5 microseconds with the 33.3 MHz LCLK).. 15. MS. Master / Slave This pin indicates the quadrature encoder synchronization pin mode, ‘1’ for master, ‘0’ for slave. See the QSMS pin for additional information.. Base + 0x42 RW 15. 14. 13. RELAY DISABLE. IA. T. 0. ?. ?. ICR: Interrupt Control Register 12. 11. 10. 9 8. IN(4:0) 0. 0. 0. 0 0. 7. 6. 5. 4 3 2 1 0. RELAY OFF. STOP. STOPPBN. IP(4:0). pin. pin. pin. 0 0 0 0 0. 15. RELAYDISABLE. Relay Disable Write ‘1’ to disable the external relay by forcing the RELAYOFF pin high. Write ‘0’ to enable the external relay to follow the normal error conditions. Note that enabling the external relay does not force it on. All other error conditions must be satisfied before the RELAYOFF pin will go low to turn on the external relay.. 14. IA. Interrupt Acknowledge Write ‘1’ to acknowledge an interrupt, it is not necessary to write a ‘0’ after writing the ‘1’. Note that reading this bit gives a random result.. 3. T. Test Mode Enable. This bit is used for manufacturing test only, when set it causes the GPO pins to float. (Formerly GPIODIR bit 3 for PCIIO-1).. 12:8. IN(4:0). Interrupt Number This value is read only, and is incremented each time an interrupt is requested. It may be used to detect missed interrupts.. 7. RELAYOFF. RELAYOFF This bit reflects the RELAYOFF pin value.. 6. STOP. STOP This bit reflects the STOP input pin value.. 5. STOPPBN. STOPPBN This bit reflects the STOPPBN input value. A low to high transition will reset a watchdog timeout.. 4:0. IP(4:0). Interrupt Rate These bits set the interrupt according to the formula LCLK frequency/(5000 * IP). For the default 10MHz LCLK, IP is interrupt period in milliseconds. Write ‘0000’ to disable the interrupt.. Base + 0x44 WO 15. 14. 13. 12. STG: Soft Trigger Register 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. Undef. 15:0. ST. Soft Trigger A write of any value to this register will force a trigger to the interrupt quadrature latch to capture the current encoder counter values. This soft trigger is independent of the interrupt and can work concurrently with an enabled interrupt.. Page 25 of 46. AO-90265BA.

(26) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x46 WR. QCCR: Quadrature Clock Control Register. This register controls the clock used by the quadrature encoder counters. 15. 14. 13. 12. 11. 10. 9. 8. 7. ID ?. ?. ?. ?. 6. 5. 4. Undefined ?. ?. ?. ?. ?. ?. ?. 3. 2. QCM. I. 0. 0. ?. 1. 0 RFU. ?. ?. 15:8. ID(7:0). Current revision of the PCIIO FPGA, see the Revision History section of this document for version number details. The ID is stored in BCD format.. 3. QCM. Quadrature Count Mode This bit changes the behavior of the quadrature encoder counters. When this bit is cleared, the quadrature encoder counters will function as normal 24-bit up/down counters. When this bit is set, the quadrature encoder counters will clear on each index pulse. The clearing of the counters happens whenever the index pulse is high, channel B is high and there is a transition on channel A.. 2. I = IDXMODE. When set this bit changes the behavior of the index detection circuit from index = rising edge on QExCHA during QExIDX high to index = rising edge on QExIDX followed by rising edge on QExCHA.. 1:0. RFU. Reserved for Future Use Formerly QCFR – Quadrature Clock Filter Rate in PCIIO-I. Quad counter filtering of the inputs is fixed to LCLK/8. (33.3 MHz/8 = 4.16 MHz). Base + 0x48 RO. EIP0: Encoder Input Pin Register 0. This register contains the state of each input pin for encoder channels 1-4. 15. 14. 13. Undefined. 12. 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. E4X E4B E4A E3X E3B E3A E2X E2B E2A E1X E1B E1A. 11. E4X. Encoder 4 Index This is the value of the QE4IDX pin.. 10. E4B. Encoder 4 Channel B This is the value of the QE4CHB pin.. 9. E4A. Encoder 4 Channel A This is the value of the QE4CHA pin.. 8. E3X. Encoder 3 Index This is the value of the QE3IDX pin.. 7. E3B. Encoder 3 Channel B This is the value of the QE3CHB pin.. 6. E3A. Encoder 3 Channel A This is the value of the QE3CHA pin.. 5. E2X. Encoder 2 Index This is the value of the QE2IDX pin.. 4. E2B. Encoder 2 Channel B This is the value of the QE2CHB pin.. 3. E2A. Encoder 2 Channel A This is the value of the QE2CHA pin.. Page 26 of 46. AO-90265BA.

(27) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). 2. E1X. Encoder 1 Index This is the value of the QE1IDX pin.. 1. E1B. Encoder 1 Channel B This is the value of the QE1CHB pin.. 0. E1A. Encoder 1 Channel A This is the value of the QE1CHA pin.. Base + 0x4A RO. EIP1: Encoder Input Pin Register 1. This register contains the state of each input pin for encoder channels 5-8. In also contains the state of the four user input pins on the FPGA. 15. 14. 13. UIP[3:0]. 12. 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. E8X E8B E8A E7X E7B E7A E6X E6B E6A E5X E5B E5A. 15:12. UIP[3:0]. User Input Pins GPI[3:0]. These bits are the UIP[3:0] pin values.. 11. E8X. Encoder 8 Index This is the value of the QE8IDX pin.. 10. E8B. Encoder 8 Channel B This is the value of the QE8CHB pin.. 9. E8A. Encoder 8 Channel A This is the value of the QE8CHA pin.. 8. E7X. Encoder 7 Index This is the value of the QE7IDX pin.. 7. E7B. Encoder 7 Channel B This is the value of the QE7CHB pin.. 6. E7A. Encoder 7 Channel A This is the value of the QE7CHA pin.. 5. E6X. Encoder 6 Index This is the value of the QE6IDX pin.. 4. E6B. Encoder 6 Channel B This is the value of the QE6CHB pin.. 3. E6A. Encoder 6 Channel A This is the value of the QE6CHA pin.. 2. E5X. Encoder 5 Index This is the value of the QE5IDX pin.. 1. E5B. Encoder 5 Channel B This is the value of the QE5CHB pin.. 0. E5A. Encoder 5 Channel A This is the value of the QE5CHA pin.. Page 27 of 46. AO-90265BA.

(28) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x4C RW. DAC Control Register. This register controls the clock used by the DAC interface. 15 14 13 12 11 10 9 8 7 DR 1. Undefined ?. ?. ?. NDAC ?. ?. 1. 6. 5. 4. Und.. 1. ?. 3. 2. 1. 0. 1. 1. DCR(5:0) ?. 1. 1. 1. 1. 15. DR. DAC Interface Reset When ‘1’ this bit forces the DAC interface to transmit all zeros to all DAC channels.. 9:8. NDAC. Number of DAC chip select outputs. This value sets the number of AD1866 DAC chips the FPGA supports. This number is the number of DAC chips minus 1. The DACs need to be connected to SDSELA – SDSELD. Supporting less DAC outputs increases the rate of change at the DAC output. Each AD1866 DAC has two channels; therefore, setting NDAC to ‘11’ supports 4 DACs and thus 8 DAC channels.. 5:0. DCR(5:0). DAC Clock Rate This value sets the divide rate for the DAC interface. DAC Clock = LCLK/[2(1+DCR)] The DAC Clock range is 16.6 MHz to 260 kHz for the 33.3 MHz LCLK. Note: The AD1866 can support 13.5 MHz clocks, but the opto-isolation limits the clock to about 6 MHz.. Base + 0x4E RW. ADC Control Register. This register controls the clock used by the DAC interface. 15 14 13 12 11 10 9 8 7 Undefined ?. ?. ?. NADC ?. ?. 1. 1. 6. 5. 4. ST 1. ?. 0. 3. 2. 1. 0. 1. 1. ACR(5:0) 1. 1. 1. 1. 10:8. NADC(2:0). Number of ADC channels This value is the number of MAX1202 ADC channels minus one that are monitored. Supporting less channels increases the sample rate of the remaining ADC inputs. By design of the MAX1202 and in an effort to reduce the complexity of the FPGA, channels 0 to N-1 are sequentially monitored in the following order: 0, 2, 4, 6, 1, 3, 5 and 7. As NADC is reduced below ‘111’, channels are dropped off the end of the sequence. The sequence is registered starting at Base + 0x62 and increasing by 0x02. The last monitored channel is always placed in the Base + 0x60 register. The ADC registers (starting at Base + 0x60) are named based on NADC = ‘111’.. 6. ST. Start Bit This is the start control of the ADC controller. If set, the ADC controller will sequentially monitor the specified ADC channel inputs.. 5:0. ACR(5:0). ADC Clock Rate This value sets the divide rate for the ADC interface. ADC Clock = LCLK/[2(1+ACR)] The ADC Clock range is 16.6 MHz to 260 kHz for the 33.3 MHz LCLK. Note: The MAX1202 can only support clocks up to 2 MHz.. Page 28 of 46. AO-90265BA.

(29) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. Digital Analog Converter (DAC) Data Registers Base + 0x50 WO 15. 14. 13. 12. DAC1: DAC 1 Data 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 0. DAC1(15:0) 0 15:0. 0. 0. 0. DAC1(15:0). 14. 13. 0. 0. 0. 0. Digital-to-Analog Converter 1 Data. Base + 0x52 WO 15. 0. 12. DAC2: DAC 2 Data 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 0. DAC2(15:0) 0 15:0. 0. 0. 0. 14. 13. 0. 0. 0. 0. Digital-to-Analog Converter 2 Data. Base + 0x54 WO 15. 0. DAC2(15:0). 12. DAC3: DAC 3 Data 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 0. DAC3(15:0) 0 15:0. 0. 0. 0. DAC3(15:0). 14. 13. 0. 0. 0. 0. Digital-to-Analog Converter 3 Data. Base + 0x56 WO 15. 0. 12. DAC4: DAC 4 Data 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 0. DAC4(15:0) 0 15:0. 0. 0. 0. DAC4(15:0). 14. 13. 0. 0. 0. 0. Digital-to-Analog Converter 4 Data. Base + 0x58 WO 15. 0. 12. DAC5: DAC 5 Data 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 0. DAC5(15:0) 0 15:0. 0. 0. 0. DAC5(15:0). 14. 13. 0. 0. 0. 0. Digital-to-Analog Converter 5 Data. Base + 0x5A WO 15. 0. 12. DAC6: DAC 6 Data 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 0. DAC6(15:0) 0 15:0. 0. 0. DAC6(15:0). 0. 0. 0. 0. 0. 0. Digital-to-Analog Converter 6 Data. Page 29 of 46. AO-90265BA.

(30) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x5C WO 15. 14. 13. 12. DAC7: DAC 7 Data 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 0. DAC7(15:0) 0 15:0. 0. 0. 0. DAC7(15:0). 14. 13. 0. 0. 0. 0. Digital-to-Analog Converter 7 Data. Base + 0x5E WO 15. 0. 12. DAC8: DAC 8 Data 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 0. DAC8(15:0) 0 15:0. 0. 0. 0. 0. DAC8(15:0). 0. 0. 0. 0. Digital-to-Analog Converter 8 Data. Analog Digital Converter (ADC) Data Registers Note: The order of the ADC channel registers is not sequential. This was done to reduce FPGA complexity.. Base + 0x60 RO 15. 14. 13. 12. ADC7: ADC 7 Data 11. 10. 9. 8. 7. Undefined ? 11:0. ?. ?. ?. 0. ADC7(11:0). 14. 13. 0. 11:0. ?. 4. 3. 2. 1. 0. 0. 0. 0. 12. ?. ADC0(11:0). 0. 0. 0. 0. 0. 0. 0. Analog-to-Digital Converter 7 Data This is the ADC channel 7 for NADC = ‘111’. The contents of this register will change based on the value of NADC in the ADC Control Register (0x4E). The follow table list the contents of this register based on the value of NADC. NADC Register Contents ‘111’ ADC Channel 7 ‘110’ ADC Channel 5 ‘101’ ADC Channel 3 ‘100’ ADC Channel 1 ‘011’ ADC Channel 6 ‘010’ ADC Channel 4 ‘001’ ADC Channel 2 ‘000’ ADC Channel 0. ADC0: ADC 0 Data 11. 10. 9. 8. 7. Undefined ?. 5. ADC7(11:0). Base + 0x62 RO 15. 6. 6. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. ADC0(11:0) ?. 0. 0. 0. 0. 0. 0. 0. Analog-to-Digital Converter 0 Data This is the ADC Channel 0 value for ‘001’ ≤ NADC ≤ ‘111’.. Page 30 of 46. AO-90265BA.

(31) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x64 RO 15. 14. 13. 12. ADC2: ADC 2 Data 11. 10. 9. 8. 7. Undefined ? 11:0. ?. ?. ?. 0. ADC2(11:0). 14. 13. 0. 0. 0. 0. 11:0. ?. 12. ?. 13. 11. 10. 9. 8. ?. ?. ?. 0. 12. 0. 0. 0. 11:0. ?. ?. 11 0. 12. 10. 9. 8. 11:0. ?. ?. 11 0. 12. 0. 0. 0. 11:0. ?. 6. 0. 10. 9. 8. 0. 7. 0. 0. 0. 6. 0. 11. 10. 9. 8. 0. 7. ?. 0. 0. 0. 0. 6. 0. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 5. 4. 3. 2. 1. 0. 12. ?. ADC5(11:0). 0. 0. 0. 0. 0. 0. 0. Analog-to-Digital Converter 3 Data This is the ADC Channel 3 value for ‘110’ ≤ NADC ≤ ‘111’.. ADC5: ADC 5 Data 11. 10. 9. 8. 7. Undefined ?. 5. ADC3(11:0). ?. 13. 0. ADC3: ADC 3 Data. ADC3(11:0). 14. 0. Analog-to-Digital Converter 1 Data This is the ADC Channel 1 value for ‘101’ ≤ NADC ≤ ‘111’.. Base + 0x6E RO 15. 0. 7. Undefined ?. 0. ADC1(11:0). ?. 13. 0. ADC1: ADC 1 Data. ADC1(11:0). 14. 0. Analog-to-Digital Converter 6 Data This is the ADC Channel 6 value for ‘100’ ≤ NADC ≤ ‘111’.. Base + 0x6C RO 15. 6. 0. Undefined ?. 0. ADC6(11:0). ?. 13. 0. ADC6: ADC 6 Data. ADC6(11:0). 14. 1. Analog-to-Digital Converter 4 Data This is the ADC Channel 4 value for ‘011’ ≤ NADC ≤ ‘111’.. Base + 0x6A RO 15. 0. 7. Undefined 11:0. 2. ADC4: ADC 4 Data. ADC4(11:0). 14. 3. ADC4(11:0). Base + 0x68 RO 15. 4. Analog-to-Digital Converter 2 Data This is the ADC Channel 2 value for ‘010’ ≤ NADC ≤ ‘111’.. Undefined ?. 5. ADC2(11:0). Base + 0x66 RO 15. 6. 6. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. ADC5(11:0) ?. 0. 0. 0. 0. 0. 0. 0. Analog-to-Digital Converter 5 Data This is the ADC Channel 5 value for NADC = ‘111’.. Page 31 of 46. AO-90265BA.

(32) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. SPI Bus Interface Registers Base + 0x70 RW 15. 14. 13. 12. Undefined ?. ?. SPIBCS: SPI Bus Control and Status 11. 10. 9. 8. SCR(5:0) ?. ?. ?. ?. ?. ?. 7. 6. Und.. SBB. ?. 0. 5. 4. 3. Und. ?. 2. 1. 0. SDS(3:0) ?. ?. ?. ?. ?. 9:8. SCR(5:0). Serial Clock Rate This value sets the divide rate for the SPI interface clock. SPI Clock = LCLK/[2(1+SCR)] The SPI Clock range is 16.6 MHz to 260 kHz for the 33.3 MHz LCLK. 6. SBB. Serial Bus Busy When ‘1’ this bit indicates that the serial bus is busy. This bit is set by a write to the SPID register and cleared when the serial bus transaction is complete and data from the target is available to be read.. 3:0. SDS(3:0). Serial Data Size ‘1111’ = 16 bit, ‘1110’ = 15 bit, etc. Note that ‘0010’ (3), ‘0001’ (2) and ‘0000’ (1 bit) are not valid.. Base + 0x72 RW 15. 14. 13. 12. SPID: SPI Bus Data 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 0. 0. 0. 0. 0. 0. 0. SPID(15:0) 0 15:0. 0. 0. 0. 0. SPID(15:0). 0. 0. 0. 0. SPI Bus Data Writing to this register starts a serial bus transaction, the data written will be shifted out onto the SPI bus output least significant bit first and the data from the SPI bus inputs will be shifted into this register most significant bit first. This was done to reduce FPGA complexity. For data sizes other than 16-bit the low order bits are used.. General Purpose Input (GPI) Data Registers Note that these registers are implemented by external hardware with only a chip select being provided by the PCIIO-II, Data Interface For Generation-II PCI Card FPGA.. Base + 0x74 RO 15. 14. 13. 12. GPI0: General Purpose Input Register 0 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 3. 2. 1. 0. GPI(15:0) 15:0. GPI(15:0). General Purpose Input Value. Base + 0x76 RO 15. 14. 13. 12. GPI1: General Purpose Input Register 1 11. 10. 9. 8. 7. 6. 5. 4. GPI(31:16) 15:0. GPI(31:16). General Purpose Input Value. Page 32 of 46. AO-90265BA.

(33) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x78 RO 15. 14. 13. 12. GPI2: General Purpose Input Register 2 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 2. 1. 0. 1. 1. 1. GPI(47:32) 15:0. GPI(47:32). General Purpose Input Value. General Purpose Input/Output (GPIO) Interface Registers Base + 0x7A RW 15. 14. 13. GPIO: General Purpose Input/Output 12. GPIODIR pin. 11. 10. 9. 8. 7. 6. 5. 4. Undefined ?. ?. ?. ?. 3 GPIO(6:0). ?. ?. ?. ?. 1. 1. 1. 1. 15. GPIODIR. General Purpose I/O Direction When ‘0’ this bit indicates that the GPIO pins are outputs. This bit is controlled by an input pin on the chip, when the pin is ‘1’ the GPIO pins are inputs.. 6:0. GPIO(6:0). General Purpose I/O When read, this register is a direct read of the GPIO pin inputs. Writes control the GPIO pins only if the GPIODIR is 0. The GPIO bits are set to all ‘1’s by reset, ESTOP or watchdog timeout.. General Purpose Output (GPO) Data Registers Base + 0x7C RW 15. 14. 13. 12. GPO0: General Purpose Output Register 0 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 1. 1. 1. 1. 1. 1. 1. GPO(15:0) 1 15:0. 1. 1. 1. GPO0(15:0). 14. 13. 1. 1. 1. 1. General Purpose Output Pin Control Writes to this register control the state of the GPO[15:0] pins. This register is set to all ‘1’s by reset, ESTOP or watchdog timeout.. Base + 0x7E RW 15. 1. 12. GPO1: General Purpose Output Register 1 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1. 0. 1*. 1. 1. 1. 1. 1. 1. GPO(31:16) 1 13:0. 1. 1. 1. GPO1(31:16). 1*. 1*. 1*. 1*. 1. General Purpose Output Pin Control Writes to this register control the state of the GPO[31:16] pins. Except as noted below, this register is set to all ‘1’s by reset, ESTOP or watchdog timeout. *Note: Bits 11:8 & 6 (GPO[27:24] & GPO22) are set to ‘1’s by reset only.. Page 33 of 46. AO-90265BA.

(34) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. Quadrature Encoder Sub-Count Registers One way to improve low speed encoder resolution is to do what is some times called "Sub-Count Interpolation". It requires two additional high speed counters for each encoder channel. The goal is to measure the distance traversed between the encoder pulses. One counter (the Denominator) is feed the highest frequency possible (LCLK) and measures the time between the last two encoder edges observed. The second counter (the Numerator) is feed the same high frequency input (LCLK) and measures the time since the last encoder edge was observed. Time = (counter value) * (LCLK period * 8). With LCLK = 33.3 MHz, LCLK period = 30 nsec. For each quadrature encoder channel, both counter values are latched when its quadrature encoder count is read.. Base + 0x80 RO. Q1SDL: Quadrature Encoder 1 Sub-Count Denom. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 1 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q1SD(15:0) 15:0. Q1SD(15:0). Base + 0x82 RO. Quadrature Encoder 1 Sub-Count Denominator Lower 16 bits. Q1SDH: Quadrature Encoder 1 Sub-Count Denom. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 1 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q1SD(31:16) 7:0. Q1SD(23:16). Base + 0x84 RO. Quadrature Encoder 1 Sub-Count Denominator Upper 16 bits. Q2SDL: Quadrature Encoder 2 Sub-Count Denom. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 2 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q2SD(15:0) 15:0. Q2SD(15:0). Base + 0x86 RO. Quadrature Encoder 2 Sub-Count Denominator Lower 16 bits. Q2SDH: Quadrature Encoder 2 Sub-Count Denom. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 2 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q2SD(31:16) 7:0. Q2SD(23:16). Quadrature Encoder 2 Sub-Count Denominator Upper 16 bits. Page 34 of 46. AO-90265BA.

(35) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x88 RO. Q3SDL: Quadrature Encoder 3 Sub-Count Denom. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 3 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q3SD(15:0) 15:0. Q3SD(15:0). Base + 0x8A RO. Quadrature Encoder 3 Sub-Count Denominator Lower 16 bits. Q3SDH: Quadrature Encoder 3 Sub-Count Denom. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 3 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q3SD(31:16) 7:0. Q3SD(23:16). Base + 0x8C RO. Quadrature Encoder 2 Sub-Count Denominator Upper 16 bits. Q4SDL: Quadrature Encoder 4 Sub-Count Denom. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 4 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q4SD(15:0) 15:0. Q4SD(15:0). Base + 0x8E RO. Quadrature Encoder 4 Sub-Count Denominator Lower 16 bits. Q4SDH: Quadrature Encoder 4 Sub-Count Denom. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 4 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q4SD(31:16) 7:0. Q4SD(23:16). Base + 0x90 RO. Quadrature Encoder 4 Sub-Count Denominator Upper 16 bits. Q5SDL: Quadrature Encoder 5 Sub-Count Denom. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 5 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q5SD(15:0) 15:0. Q5SD(15:0). Base + 0x92 RO. Quadrature Encoder 5 Sub-Count Denominator Lower 16 bits. Q5SDH: Quadrature Encoder 5 Sub-Count Denom. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 5 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q5SD(31:16) 7:0. Q5SD(23:16). Quadrature Encoder 5 Sub-Count Denominator Upper 16 bits. Page 35 of 46. AO-90265BA.

(36) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0x94 RO. Q6SDL: Quadrature Encoder 6 Sub-Count Denom. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 6 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q6SD(15:0) 15:0. Q6SD(15:0). Base + 0x96 RO. Quadrature Encoder 6 Sub-Count Denominator Lower 16 bits. Q6SDH: Quadrature Encoder 6 Sub-Count Denom. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 6 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q6SD(31:16) 7:0. Q6SD(23:16). Base + 0x98 RO. Quadrature Encoder 6 Sub-Count Denominator Upper 16 bits. Q7SDL: Quadrature Encoder 7 Sub-Count Denom. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 7 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q7SD(15:0) 15:0. Q7SD(15:0). Base + 0x9A RO. Quadrature Encoder 7 Sub-Count Denominator Lower 16 bits. Q7SDH: Quadrature Encoder 7 Sub-Count Denom. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 7 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q7SD(31:16) 7:0. Q7SD(23:16). Base + 0x9C RO. Quadrature Encoder 7 Sub-Count Denominator Upper 16 bits. Q8SDL: Quadrature Encoder 8 Sub-Count Denom. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 8 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q8SD(15:0) 15:0. Q8SD(15:0). Base + 0x9E RO. Quadrature Encoder 8 Sub-Count Denominator Lower 16 bits. Q8SDH: Quadrature Encoder 8 Sub-Count Denom. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 8 denominator used in sub-count calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q8SD(31:16) 7:0. Q8SD(23:16). Quadrature Encoder 8 Sub-Count Denominator Upper 16 bits. Page 36 of 46. AO-90265BA.

(37) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0xA0 RO. Q1SNL: Quadrature Encoder 1 Sub-Count Num. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 1 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q1SN(15:0) 15:0. Q1SN(15:0). Base + 0xA2 RO. Quadrature Encoder 1 Sub-Count Numerator Lower 16 bits. Q1SNH: Quadrature Encoder 1 Sub-Count Num. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 1 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q1SN(31:16) 7:0. Q1SN(23:16). Base + 0xA4 RO. Quadrature Encoder 1 Sub-Count Denominator Upper 16 bits. Q2SNL: Quadrature Encoder 2 Sub-Count Num. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 2 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q2SN(15:0) 15:0. Q2SN(15:0). Base + 0xA6 RO. Quadrature Encoder 2 Sub-Count Numerator Lower 16 bits. Q2SNH: Quadrature Encoder 2 Sub-Count Num. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 2 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q2SN(31:16) 7:0. Q2SN(23:16). Base + 0xA8 RO. Quadrature Encoder 2 Sub-Count Denominator Upper 16 bits. Q3SNL: Quadrature Encoder 3 Sub-Count Num. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 3 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q3SN(15:0) 15:0. Q3SN(15:0). Base + 0xAA RO. Quadrature Encoder 3 Sub-Count Numerator Lower 16 bits. Q3SNH: Quadrature Encoder 3 Sub-Count Num. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 3 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q3SN(31:16) 7:0. Q3SN(23:16). Quadrature Encoder 3 Sub-Count Denominator Upper 16 bits. Page 37 of 46. AO-90265BA.

(38) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0xAC RO. Q4SNL: Quadrature Encoder 4 Sub-Count Num. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 4 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q4SN(15:0) 15:0. Q4SN(15:0). Base + 0xAE RO. Quadrature Encoder 4 Sub-Count Numerator Lower 16 bits. Q4SNH: Quadrature Encoder 4 Sub-Count Num. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 4 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q4SN(31:16) 7:0. Q4SN(23:16). Base + 0xB0 RO. Quadrature Encoder 4 Sub-Count Denominator Upper 16 bits. Q5SNL: Quadrature Encoder 5 Sub-Count Num. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 5 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q5SN(15:0) 15:0. Q5SN(15:0). Base + 0xB2 RO. Quadrature Encoder 5 Sub-Count Numerator Lower 16 bits. Q5SNH: Quadrature Encoder 5 Sub-Count Num. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 5 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q5SN(31:16) 7:0. Q5SN(23:16). Base + 0xB4 RO. Quadrature Encoder 5 Sub-Count Denominator Upper 16 bits. Q6SNL: Quadrature Encoder 6 Sub-Count Num. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 6 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q6SN(15:0) 15:0. Q6SN(15:0). Base + 0xB6 RO. Quadrature Encoder 6 Sub-Count Numerator Lower 16 bits. Q6SNH: Quadrature Encoder 6 Sub-Count Num. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 6 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q6SN(31:16) 7:0. Q6SN(23:16). Quadrature Encoder 6 Sub-Count Denominator Upper 16 bits. Page 38 of 46. AO-90265BA.

(39) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022). Base + 0xB8 RO. Q7SNL: Quadrature Encoder 7 Sub-Count Num. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 7 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q7SN(15:0) 15:0. Q7SN(15:0). Base + 0xBA RO. Quadrature Encoder 7 Sub-Count Numerator Lower 16 bits. Q7SNH: Quadrature Encoder 7 Sub-Count Num. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 7 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q7SN(31:16) 7:0. Q7SN(23:16). Base + 0xBC RO. Quadrature Encoder 7 Sub-Count Denominator Upper 16 bits. Q8SNL: Quadrature Encoder 8 Sub-Count Num. Low Word. This register contains the lower 16 bits of the latched count for quadrature encoder 8 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q8SN(15:0) 15:0. Q8SN(15:0). Base + 0xBE RO. Quadrature Encoder 8 Sub-Count Numerator Lower 16 bits. Q8SNH: Quadrature Encoder 8 Sub-Count Num. High Word. This register contains the upper 16 bits of the latched count for quadrature encoder 8 numerator used in subcount calculations. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Q8SN(31:16) 7:0. Q8SN(23:16). Quadrature Encoder 8 Sub-Count Denominator Upper 16 bits. Page 39 of 46. AO-90265BA.

(40) PCI IO-II: Data Interface FPGA for Gen-II PCI I/O Card (MO-12899 & MO-13022).. DUAL 16550 UARTs This section is the register map for the dual integrated 16550 UARTS. The integrated UARTs use an identical register map as the original 16550 device with the exception of the 8 bit register on 16bit boundaries. For additional information of the 16550 register map, refer to the 16550 data sheet accompanying this specification.. UART0 Base + 0xC0 RO 15. 14. 13. (DLAB=0) RX Buffer. 12. 11. 10. 9. 8. 7. 6. 5. 4. Undefined 7:0. 13. 12. 11. 10. 9. 8. 7. 6. 5. 4. 13. 12. 11. 10. 9. 8. 7. 6. 5. 4. ?. ?. 11. 10 9. 8. 7 6. 5 4. ?. ?. ?. ?. ? ?. 1. 0. EDSSI. ELSI. ETBEI. ERBFI. 0. 0. 0. 0. ? ?. Enable Modem Status Interrupt. 2. ELSI. Enable RX Line Status Interrupt. 1. ETBEI. Enable TX Hold Register Empty Interrupt. 0. ERBFF. Enable RX Data Available Interrupt. Base + 0xC2 RW 13. 12. (DLAB=1) Divider Latch MSB 11. 10. 9. 8. 7. 6. 5. Undefined 7:0. 0. 2. EDSSI. 14. 1. 3. 3. 15. 2. (DLAB=0) Interrupt Enable Register. Undefined ?. 3. This is LSB of the baud rate divider.. Base + 0xC2 RW. ?. 0. Divider. Divider(7:0). 15 14 13 12. 1. (DLAB=1) Divider Latch LSB. Undefined 7:0. 2. This is the TX data. A write of this location pushes a value to the TX FIFO. Base + 0xC0 RW 14. 3. TX Data. TXData(7:0). 15. 0. (DLAB=0) TX Buffer. Undefined 7:0. 1. This is the RX data. A read of this location pops an RX value.. Base + 0xC0 WO 14. 2. RX Data. RXData(7:0). 15. 3. Divider(15:8). 4. 3. 2. 1. 0. Divider This is MSB of the baud rate divider.. Page 40 of 46. AO-90265BA.

No results found