Real Time FPGA Communication System Using Ethernet for Robotics

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Procedia Computer Science 76 ( 2015 ) 406 – 410

Peer-review under responsibility of organizing committee of the 2015 IEEE International Symposium on Robotics and Intelligent Sensors (IRIS 2015) doi: 10.1016/j.procs.2015.12.320

ScienceDirect

2015 IEEE International Symposium on Robotics and Intelligent Sensors (IEEE-IRIS2015)

Real Time FPGA Communication System Using Ethernet for Robotics

Nazmin Arif Mohd Noh

a

*, Azilah Saparon

a

, Habibah Hashim

a

Faculty of Electrical Engineering, 40450 UiTM Shah Alam, Selangor, Malaysia

Abstract

In this paper, Ethernet bridging on Field Programmable Gate Arrays (FPGA) is being discussed. Ethernet has been used widely in the embedded design industry nowadays. The transferring data between FPGAs are essential with the advancement of embedded system technologies. Ethernet bridging between FPGAs has been chosen because its reliability on transferring data. There are a lot of companies producing FPGA boards, one of it is ALTERA. ALTERA has manufactured different kinds of boards to suite the requirement of engineers nowadays. One of the examples of it is the DE2-115 FPGA board. This board has a soft-core processor in it which is called Nios II. Network bridging on DE2-115 FPGA requires the programming of the Nios II. In this paper, the network bridge system on FPGA is set up and an input which is the data is send through the network. The result expected from the experiment is the input is properly displayed and it is send successfully in through the network.

(http://creativecommons.org/licenses/by-nc-nd/4.0/).

Peer-review under responsibility of organizing committee of the 2015 IEEE International Symposium on Robotics and Intelligent Sensors (IRIS 2015)

Keywords:Ethernet; Nios II; FPGA; DE2-115; Triple Speed Ethernet

* Corresponding author..

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1.Introduction

Robots are used in many aspects of human life nowadays. Effective robotics communication is the key for it to complete the task given. Robotics communication system technology plays an important role so that the robots do what they are purposely built for. Engineers working hard to improve the robotics communication system by looking into embedded system as an alternate option. In today’s modern world, FPGA technologies are being looking into to help to improve the robotics communication system. FPGAs are equipped with Ethernet technology that has been used widely in the embedded design industry nowadays. Ethernet helps in bridging the network for the FPGA boards. The standard protocol used for the Ethernet is the IEEE 802.3. Network bridging using Ethernet for FPGA can improve in terms of communication because of it assures high throughput and reasonable latency. The paper is organized in four sections which are related work, framework, results and conclusion.

2.Related work

Networking using FPGA boards has been used widely in embedded design technologies. W Zhang et al. [1] have developed networking for high speed data. Using their method, the result of the data transfer of the networking system was clear levels, the simulation of the data of the system was accurate and the testing result was reliable.

According to V. R. Gad et al. [2], their experiment was based on implementation of Ethernet standard using FPGA. Through their experiment, Gigabit Ethernet performance were analysed which is the Gigabit Ethernet Standard 1000LX, 1000 Base-SX and 1000Base-T. D. Qiu et al. [3] on the other hand have worked on networking between FPGAs which used System on Programmable Chip (SOPC) to implement the Gigabit Ethernet. Using their method, the network of the Gigabit system is set up using SOPC builder and the data transmission are connected using TCP/IP protocol. The results of their research are the power dissipation during the networking is reduced and it improves the flexibility of the Gigabit Ethernet system. Fritz Mayer-Lindenberg [4] , implemented networks on FPGA through mapping process. The mapping process is designed on Spartan-3A and Virtex-5 FPGA boards which are from Xilinx. From the research, the performance of the FPGA boards tested are measured and analysed.

G. Brebner et al. [5] implemented networking on chip with platform FPGA. Their method of networking the fpga was by sending data packet using switching network on Xilinx Virtex fpga board. A. S. Bharadwaj et al. [6] have put forward an implementation of the Ethernet Bridge using Avalon Memory-Mapped Interface. The network connection was established between two DE2-115 ALTERA FPGA boards. The two Nios II processors were configured to control the network system. The outcome from their research showed that the speed of the data transfer was increased greatly and the power usage during the networking process on the other hand had been reduced.

P. P. P. Zode [7], has presented a novel approach for the implementation of an embedded web server on Nios embedded platform. Through this method, the web server is used for the networking process. The embedded web server communicates with the web browser through TCP/HTTP. The author came up with a design of the networking system which was simpler and more efficient in terms of re-configurability, and in addition to that, the cost of building the system was lower whilst the power consumption used during the process was greatly reduced. Tercio A.S.Filho et al. [8], introduced the research on Network Nod with Wireless and Wired Interfaces on FPGAs. Their technique involved setting up the network gateway with two interfaces, one using wireless using Zigbee method while the other was directly connected via RS232. The two methods were developed using Nios II soft-core processor and uClinux operating system. They were able to improve the flexibility of the networking, to be more adaptable to network conditions.

According to the research conducted by Kees Goosens et al. [9], utilizing networks on chip are hardwired in FPGA, saves configuration of the footprints (bits) as well as the configuration time. The use of hard busses can result in quicker reprogramming compared to its soft counterparts. The hard interconnects are also disjointed from the soft IPs and layout restrictions were reduced. Chen Xin Zhi et al. [10], implemented Ethernet ports on FPGA as the networking system for the FPGA. Through their method, the systems receive and deal sampled values (SV) data packet from multiple Ethernet ports at the same time. The FPGA is used to implement the independent Ethernet MAC for each port. Through this method, the pre-processor board does some extra work to boost up the performance of the protection processor. From the previous experiments reviewed, the area which can be improve for network bridging using FPGA are throughput and the speed of the data transfer during the network bridging process.

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3. Framework

The objective of the experiment is to evaluate the network bridge performance of the FPGA. The performances looking into are the speed of data transfer and the throughput is successfully sent through the network system. For the experiment, a DE2-115 FPGA board from ALTERA is used to set up the network bridge between the board with the pc. The DE2-115 board is connected to the PC using Universal Serial Bus (USB) Blaster connection.

The system is build using Verilog code in Quartus II software. The Ethernet Bridge system is built using Qsys sytem. Qsys is compiled in the Quartus II software for the hardware configuration using the Qsys builder such as Figure 3. The Nios II processor [11] sends stream of Ethernet packets to the Triple Speed Ethernet (TSE) MegaCore [12] function which can be looped back. In this system, the Nios II processor is used as a control plane component for setting up and configuring system components. Other than that, the Nios II generates and monitors the Ethernet packets. In the system, the on-chip memory is used for the program code, and also as descriptors for the Scatter-Gather DMA Controller. There are also the parallel input outputs (I/O) to provide access to the required data transfer needed.

Joint Test Action Group (JTAG) Universal Asynchronous Receiver Transmitter (UART) core transfers serial character streams between the Nios II processor and Qsys builder system. Phase-Locked loop (PLL) core takes the input clock and generates the desired output clock as system wide clock for the Triple Speed Ethernet (TSE) MegaCore function. Triple Speed Ethernet MegaCore applies the MAC sublayer and a fractional Physical layer when needed based on the interface type.

4.Results

The hardware system configured using the Qsys system [13] is downloaded to the DE2-115 FPGA board. An application program called ALTERA Monitor Program is used to monitor the system. The program accepts the string input that the user types in the terminal window of the program and the input is sent and looped back successfully in the system( refer to Fig. 1). The Ethernet system provides the fast data transfer of the string input that the user entered in the terminal window.

Fig. 1. The terminal window of the ALTERA Monitor Program

The length of the characters that can be send as input by the user is tested in the experiment. A limitation of the system requires that the string input that can be entered is only up to 45 characters according to Fig. 2.

Fig. 2. The result of the input length test in the terminal window.

A network switch is added to the system to check the content of the packets so that the correct data is sent into the network system. A programme called Wireshark is used to analyse the packet that was sent through the network system. According to Fig. 3, a new input is sent through the network for Wireshark to analyse the packet which entered the network.

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Fig. 3. The input sent that will be analysed by Wireshark.

The data send process is monitored separately in a response window as shown in Fig. 4. The content sent through the network is revealed and the details of the packet are shown in the window.

Fig. 4. The analysed data packet sent through the system.

Another response window as shown in Fig. 5 illustrates the data received process that occurs in the network when the input entered was successfully received through the network.

Fig. 5. The analysed data packet received by the system.

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The details of the speed of the transfer is also analysed by the Wireshark application. Fig. 6 shows the details of the speed of the networking system. The speed of the data transfer is 118.427 Mbit per second. The transfer process involved 246723.765 average packets per second and the average packet size is 60 bytes. The data transfer is successfully as the packets are displayed fully 100 percent and displayed correctly according to Figure 4 and Figure 5.

5. Conclusion

From the experiment, we can conclude that the implementation of network bridging on the DE2-115 FPGA board has been done successfully. The Ethernet system provides communication between devices which support Ethernet standards. The performance of the network bridge is analysed in terms of the data transfer which is the throughput. In addition, the speed of the data transfer from the network bridge is also measured in the experiment. The result of this experiment will provide information to help in robotics communication system.

Acknowledgements

This research work was supported by the Ministry of Education (MOE) Malaysia that provided the grant 600-RMI/NRGS 5/3 (5/2013) and Universiti Teknologi MARA (UiTM).

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