VHDL code for 4-bit ALU

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VHDL code for 4-bit ALU

BY ADMIN · PUBLISHED MAY 19, 2014 · UPDATED MAY 23, 2016

ALU’s comprise the combinational logic that implements logic operations such as AND, OR, NOT gate and arithmetic operations, such as Adder, Subtractor. Functionally, the operation of typical ALU is represented as shown in diagram FPGA Video Tutorial

VHDL VHDL Video Tutorial Xilinx Tutorial Altera Tutorial Simulation Tutorial " 30/4/17, 12*37 am VHDL code for 4-bit ALU

below,

Functional Description of 4-bit Arithmetic Logic Unit

Controlled by the three function select inputs (sel 2 to 0), ALU can perform all the 8 possible logic operations

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VHDL Code for 4-bit ALU 1 2 3 4 5 6 7 8

librarylibrary IEEE;

useuse IEEE.STD_LOGIC_1164.ALLALL; useuse IEEE.NUMERIC_STD.ALLALL; entityentity alu isis

Port ( inp_a : inin signed(3 downtodownto 0); inp_b : inin signed(3 downtodownto 0);

sel : inin STD_LOGIC_VECTOR (2 downtodownto 0);

30/4/17, 12*37 am VHDL code for 4-bit ALU

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

out_alu : outout signed(3 downtodownto 0)); endend alu;

architecturearchitecture Behavioral ofof alu isis beginbegin

processprocess(inp_a, inp_b, sel) beginbegin

casecase sel isis whenwhen "000" =>

out_alu<= inp_a + inp_b; --addition whenwhen "001" =>

out_alu<= inp_a - inp_b; --subtraction whenwhen "010" =>

out_alu<= inp_a - 1; --sub 1 whenwhen "011" =>

out_alu<= inp_a + 1; --add 1 whenwhen "100" =>

out_alu<= inp_a andand inp_b; --AND gate whenwhen "101" =>

out_alu<= inp_a oror inp_b; --OR gate whenwhen "110" =>

out_alu<= notnot inp_a ; --NOT gate whenwhen "111" =>

out_alu<= inp_a xorxor inp_b; --XOR gate whenwhen othersothers =>

NULLNULL; endend casecase;

endend processprocess; endend Behavioral;

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Testbench VHDL Code for 4-Bit ALU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

LIBRARYLIBRARY ieee;

USEUSE ieee.std_logic_1164.ALLALL; USEUSE ieee.numeric_std.ALLALL;

ENTITYENTITY Tb_alu ISIS ENDEND Tb_alu;

ARCHITECTUREARCHITECTURE behavior OFOF Tb_alu ISIS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENTCOMPONENT alu PORTPORT(

inp_a : ININ signed(3 downtodownto 0); inp_b : ININ signed(3 downtodownto 0);

sel : ININ std_logic_vector(2 downtodownto 0); out_alu : OUTOUT signed(3 downtodownto 0) );

ENDEND COMPONENTCOMPONENT;

--Inputs

signalsignal inp_a : signed(3 downtodownto 0) := (othersothers => signalsignal inp_b : signed(3 downtodownto 0) := (othersothers => signalsignal sel : std_logic_vector(2 downtodownto 0) := (othersothers --Outputs

signalsignal out_alu : signed(3 downtodownto 0);

30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 BEGINBEGIN

-- Instantiate the Unit Under Test (UUT)

uut: alu PORTPORT MAPMAP ( inp_a => inp_a, inp_b => inp_b, sel => sel, out_alu => out_alu ); -- Stimulus process

stim_proc: processprocess beginbegin

-- hold reset state for 100 ns. waitwait forfor 100 ns;

-- insert stimulus here

inp_a <= "1001"; inp_b <= "1111";

sel <= "000"; waitwait forfor 100 ns; sel <= "001";

waitwait forfor 100 ns; sel <= "010";

waitwait forfor 100 ns;

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Tags: ALU VHDL code arithmetic and loogic unit vhdl code

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Download Post as PDF Simulation Result for 4-bit ALU

61 62 63 64 65 66 67 68 sel <= "101"; waitwait forfor 100 ns; sel <= "110";

endend processprocess; ENDEND;

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LAST UPDATED JUNE 8, 2016 Synchronous and Asynchronous Reset VHDL

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Admin&_{May 25, 2014 at 10:36 am}

Soon, we will come up with step by step procedure to download bit in FPGA for all VHDL code and verify it.

Reply

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user&_{October 5, 2015 at 3:17 pm}

Temp <= std_logic_vector((unsigned("0" & Nibble1) + unsigned(Nibble2)));

i need an explanation to the above usage of "0" & nibble1….means i want to know the clear intention of the statement…..hope i will get a response

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thank you Reply

Admin&_{February 2, 2016 at 2:34 am}

‘0’ is concatenated with nibble because the output result give carry at MSB. Reply

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malu&_{October 14, 2016 at 10:16 am}

i am not understand the program,another method will tri sir. Reply Name * Email * LEAVE A REPLY Comment Website 30/4/17, 12*37 am VHDL code for 4-bit ALU

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VHDL code for 4-bit ALU

VHDL code for 4-bit ALU

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