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Worst-Case Analysis of Digital Control Loops with Uncertain Input/Output Timing

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Figure

Figure 1: Timing model for IO and computation with dataflow dependencies, the timing barrierTb[k] and its corresponding virtual dependencies.
Figure 2: Legend for hybrid automata used in this publication
Figure 3: Specification of controller and clock
Figure 4: Specification of sample-and-hold (SH) element
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