Arasan Chip Systems Inc North First Street, Suite #510 San Jose, CA Ph: Fx:

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Arasan Chip Systems Inc.

2010 North First Street, Suite #510 San Jose, CA 95131

Ph: 408-282-1600 Fx: 408-282-7800

www.arasan.com

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Revision Number: 2.0 Copyright © 2014, Arasan Chip Systems Inc. ii This document is written in good faith with the intent to assist the readers in the use of the product. Circuit diagrams and other information relating to Arasan Chip Systems’ products are included as a means of illustrating typical applications. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. Information contained in this document is subject to continuous improvements and developments.

Arasan Chip Systems’ products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of Arasan Chip Systems Inc. will be fully at the risk of the customer.

Arasan Chip Systems Inc. disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, title, and infringement and the like, and any and all warranties arising from any course or dealing or usage of trade.

This document may not be copied, reproduced, or transmitted to others in any manner. Nor may any use of information in this document be made, except for the specific purposes for which it is transmitted to the recipient, without the prior written consent of Arasan Chip Systems Inc. This specification is subject to change at any time without notice. Arasan Chip Systems Inc. is not responsible for any errors contained herein.

In no event shall Arasan Chip Systems Inc. be liable for any direct, indirect, incidental, special, punitive, or consequential damages; or for loss of data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of Arasan Chip Systems Inc or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of buyers is held to have failed of its essential purpose, and whether or not Arasan Chip Systems Inc. has been advised of the possibility of such damages.

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Copyright Notice

No part of this specification may be reproduced in any form or means, without the prior written consent of Arasan Chip Systems Inc.

Questions or comments may be directed to: Arasan Chip Systems Inc.

2010 North First Street, Suite 510 San Jose, CA 95131

Ph: 408-282-1600 Fx: 408-282-7800

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Revision Number: 2.0 Copyright © 2014, Arasan Chip Systems Inc. iii

1

Introduction ... 1

1.1

Overview ... 1

1.2

Features ... 1

2

Architecture ... 2

2.1

Functional Description ... 2

2.1.1 UHS II PHY ... 3 2.1.2 Transaction Layer ... 4

2.2

Functional Block Diagram and Description ... 4

2.2.1 UHS-II PHY and UHS-I Interface ... 4

2.2.2 Layer Stack ... 5

2.2.3 Registers ... 5

2.2.4 First In First Out (FIFO) ... 5

2.2.5 Direct Memory Access (DMA) Module ... 5

2.2.6 Host Processor Interface ... 5

3

PIN Diagram ... 5

3.1

SD4.1 Device IP Pinout ... 5

4

SoC Level Integration ... 9

4.1

Deliverables ... 9

4.2

Verification Environment ... 10

4.3

Verification Deliverables ... 10

4.4

Figure 1: SD4.1 Device Controller IP Core Layer Structure ... 3

Figure 2: SD4.1 Device Controller IP Core Layer Structure Block Diagram ... 4

Figure 3: Verification Environment of SD4.1 Device IP ... 10

Table 1: AHB Slave Interface ... 5

Table 2: AHB Master Interface ... 6

Table 3: RAM Interface Signals ... 6

Table 4: System Interface Signals ... 7

Table 5: SD 3.0 Interface... 8

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1

Introduction

1.1

Overview

The rapid proliferation of high-performance mobile and handheld devices has

resulted in increasing requirements for non-volatile memory. Memory interfaces with

larger capacities and faster access times are needed. In response to these trends, the

SD 4.1 specification was published in May, 2011. The SD 4.1 spec employs the serial

differential interface, UHS-II, to achieve a peak data rate of 3.12Gbps. In addition to

supporting the high data rate, SD 4.1 also added ADMA3 to support very large data

amount of data transfer.

Arasan SD 4.1 Device Controller IP core, fully complaint to SD 4.1 specification, is used

to implement SD memory cards that are connected to a SD host or card-reader. The

Device Controller IP comprises of two parts, the digital controller IP core and the

analog UHS-II PHY. This datasheet introduces the digital controller IP core, its

interfaces to UHS-II PHY, and the interface to processor or MCU core. A separate

datasheet introduces UHS-II PHY.

This SD 4.1 device controller IP interface is backward compatible; it supports both the

SD 4.1 UHS-II mode and the legacy SD bus interface mode. When the UHS-II device is

connected to a host supporting only legacy SD bus interfaces, this UHS-II device will

run at the maximum speed of the legacy SD bus speed. Other backward compatibility

supports include up to USH-I, SDXC, mini-SD, eSD standard function interface code,

and extended 2.7-3.6V operating voltages.

The SD Device IP core is available with many system bus interfaces including AHB,

Advanced eXtensible Interface (AXI), and Open Core Protocol (OCP).

1.2

Features



Compliant with SD Specification 4.1



Communicates with SD 3.0 host using the UHS-I interface



High-performance UHS-II or UHS-I Host connection



Supports all SD form factors including standard, mini and micro SD card



Supports tuning command in single date rate SDR104



SD4.1 device feature supports:



Sub-LVDS Differential PHY signalling



Dual operating voltage range 2.7V – 3.6V and 1.7V - 1.95V



Spread Spectrum clocking to reduce EMI



Flexible transmission rate between 390Mbps to 1.56Gbps per lane



Transfers up to 312 Mbps (UHS156) in Half Duplex mode and 156

Mbps in Full Duplex mode

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Revision Number: 2.0 Copyright © 2014, Arasan Chip Systems Inc. 2



Point to point and multi device connection using Ring Connection

topology



Integrated solution with built-in termination, no external components

required



Low frequency differential reference clock (1/15th or 1/30th) of data

rate



Enhanced power management scheme allowing Low Power States

(LPS) – Electrical IDLE (EIDL) and DORMANT



CRC7 and CRC16 integrity checks for Command and Data



SD4.1 device is programmable through AMBA 3.0 Advanced High

Performance Bus (AHB)



Host clock rate from 0 to 208 MHz (SDR104)



Supports SPI (Only SD3.0), 1-bit, and 4-bit SD modes



Up to 104MB/s read/write with 4-bit data lines in SDR104 mode, and up

to 50MB/s in dual data rate (DDR50)



Supports ultra-high speed type I (SDR12, SDR25, SDR50, DDR50, SDR104)

mode

2

Architecture

2.1

Functional Description

The SD4.1 Device Controller IP core consists of Link layer and Transaction layer. The

Physical layer is offered separately as UHS-II PHY IP.

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Revision Number: 2.0 Copyright © 2014, Arasan Chip Systems Inc. 3 Figure 1: SD4.1 Devic e Controller IP C ore Layer Structur e

2.1.1

UHS II PHY

The Link Layer is in charge of controlling data flow and the management of LINK and

PHY. The key features of Link Layer are:



PHY Initialization Control



Data Integrity: Packet framing with SOP and EOP, CRC generation and

checking.



Flow Control:

Fixed window flow control only for Data packet transfer



Direction Control:

Duplex mode switching between FD mode and 2L-HD

mode (Optional)



Power Management (PM)



Lane level power saving state (EIDL: Electrical Idle)



Link level power saving state (Dormant)



PHY and LINK error handling



Packet Bypassing

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Revision Number: 2.0 Copyright © 2014, Arasan Chip Systems Inc. 4

2.1.2

Transaction Layer

The key features are:



New packet based protocol considering legacy SD compatibility



ID based routing for multiple device connectivity



CM_TRAN for common architecture between Host and Device



Transaction Layer consists of two sub layers called CM_TRAN (lower

sub-layer) and application specific SD-TRAN (upper sub-sub-layer). This layering

implementation is intended to define the common part of TRAN

(CM-TRAN) between Host and Device. As a result, the same CM-TRAN can be

used in both Host and Device side

2.2

Functional Block Diagram and Description

Figure 2: SD4.1 Devic e Controller IP C ore Layer Structur e Block Diagram

2.2.1

UHS-II PHY and UHS-I Interface

The controller communicates with an SD 4.1 host through the UHS-II PHY, or with SD

3.0 host using the UHS-I interface. The UHS-II interface utilizes transmission lines

(including socket and pins) and terminations which are meant to keep the

impedance matching for high-speed transmission. UHS-II interface has two Data

Lanes. D0 and D1 Lanes are used for differential transmission between Host and

Device that are dedicated to UHS-II interface only, and are separate from signals of

legacy SD interface.

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Revision Number: 2.0 Copyright © 2014, Arasan Chip Systems Inc. 5

2.2.2

Layer Stack

The stack consists of a Link layer and Transfer layer. The Link Layer manages the flow

control and data between LINK and PHY. The Transfer Layer consists of Common

Transfer Layer and SD Transfer Layer. The Common Transfer Layer performs the data

transfers by performing configuration mechanism and transaction management The

SD Transfer Layers acts as a bridge between SD legacy and UHS-II common protocol

layer.

2.2.3

Registers

The register block contains configuration information. The processor accesses these

registers through AHB (or other) slave interface.

2.2.4

First In First Out (FIFO)

The FIFO Control block contains one dual port FIFO for performing both read and

write transactions. During write transaction (data is transferred from SD Host to

Processor SD Device the data is filled in to the first and second half of the FIFO

alternatively. During a read transaction (data is transferred from SD Device to SD

Host) the data from Host process is written to the two halves of the FIFO’s

alternatively. When data from one half of the FIFO is transferring to SD Host, the

second half of the FIFO will be filled and vice-versa and thereby the throughout will

be maximum.

2.2.5

Direct Memory Access (DMA) Module

The scatter/gather DMA controller is programmed by the processor. It performs

scatter and gather transfers to main memory.

2.2.6

Host Processor Interface

This AHB Master is responsible for transferring data between the ARM Processor and

the - AHB/ APB bridge for read and write operations using scatter-gather DMA. The

AHB/APB slave block consists of the operational registers. The AHB bridge or ARM

processor handles the reading and writing of these registers.

3

PIN Diagram

3.1

SD4.1 Device IP Pinout

The SD4.1 Device IP interface signals are described in the sections below.

Table 1 : AHB Sl ave Interfac e

Pin Direction Description

clk_ahb Input AHB System Clock

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Pin Direction Description

ahb_sd_haddr[16:0] Input Address Bus (Byte Addresses) ahb_sd_hwdata[31:0] Input Write Data Bus

ahb_sd_hrdata[31:0] Output Read Data Bus

ahb_sd_hwrite Input Write or Read Direction Indication ahb_sd_hsize[2:0] Input Size (Byte, Half Word or Word)

ahb_sd_htrans[1:0] Input Transfer Type

ahb_sd_hready_glb Input Global Ready

ahb_sd_hready Output Slave Ready

ahb_sd_hresp[1:0] Output Transfer Response

int_to_arm Output Interrupt to Processor

Table 2 : AHB Master I nterface

Name Direction Description

ahb_sd_dma_hbusreq Output AHB Bus Request

ahb_sd_dma_hgrant Input AHB Bus Grant

ahb_sd_dma_haddr[31:0] Output AHB Slave DMA address (byte addresses) ahb_sd_dma_hwdata[31:0] Output AHB write data

ahb_sd_dma_hrdata[31:0] Input AHB read data

ahb_sd_dma_hwrite Output Write / Read Direction Indication ahb_sd_dma_hsize[2:0] Output Size (byte, half word or word) ahb_sd_dma_hburst[2:0] Output Burst Size

ahb_sd_dma_hrdyglb Input Global ready signal ahb_sd_dma_htrans[1:0] Output Transfer type ahb_sd_dma_hresp[1:0] Input Transfer response

Table 3 : RAM Interfac e Signals

sd_addra OUT ADDRESS bus for SD Domain

sd_dina OUT Data Input for SD Domain

sd_wea OUT Active high write Enable for SD Domain

sd_ena OUT Active High Chip Select (SD)

sd_douat IN Data output for SD Domain

sd_addrb OUT ADDRESS bus for AHB Domain

sd_dinb OUT Data Input for AHB Domain

sd_web OUT Active high write Enable for AHB Domain

sd_enb OUT Active High Chip Select (AHB)

sd_doubt IN Data output for AHB Domain

Note:

The RAM interface signals width can be varied according to the PARAMETERS

defined in ram_params.v

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pwr_on_rst_n Input Active Low. Asynchronous Hardware reset

from the External environment

ahb_clk_wkup Output Active high signal to wakeup AHB clock. After power on reset this signal asserted as 1’b0 as the chip in Auto wakeup mode. If Auto clk enable bit is set to “1” in Clock wakeup Register

SD_Combo_AHB Controller enable ahb_clk_wkup signal depending on the activity on the bus when required. If Manual Clock enable bit is set to “1” in Clock wakeup Register this bit is asserted always 1’b1.

pullup_en Output Active hIgh Pull-up Enable from the Arasan SD-Combo-AHB bridge for Card Detection

scan_mode Input Active Low. If set as

1’b1 - bypass all reset pulses generated internally

1’b0 - POR will be asserted asynchronously.

clk_sd Input SD Clock

clk_sd_inv Input Inverted SD Clock

SD_CMD cmd_di sel_sd_resp sel_resp_en INOUT IN OUT OUT

SD4 bit mode: Command Line SD1 bit mode: Command Line SPI mode: Data Input

Command Input Command Output Command Output Enable SD_DAT0 data0 sel_tx_dat0 sel_tx_dat0_en INOUT IN OUT OUT

SD4 bit mode: Data Line 0 SD1 bit mode: Data Line SPI mode: Data Output

Data0 Input Data0 Output Data0 Output Enable SD_DAT1 data1 sel_tx_dat1 sel_tx_dat1_en INOUT IN OUT OUT

SD4 bit mode: Data Line1 or Interrupt (optional)

SD1 bit mode: Interrupt SPI mode: Interrupt

Data1 Input Data1 Output Data1 Output Enable SD_DAT2

data2

INOUT

IN

SD4 bit mode: Data Line2 or Read Wait (optional)

SD1 bit mode: Read Wait (optional) SPI mode: Not Used

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sel_tx_dat2 sel_tx_dat2_en

OUT OUT

Data2 Output Data2 Output Enable SD_DAT3 data3 sel_tx_dat3 sel_tx_dat3_en INOUT IN OUT OUT

SD4 bit mode: Data Line 3 SD1 bit mode: Not Used SPI mode: Card Select Data3 Input

Data3 Output Data3 Output Enable

Table 5 : SD 3.0 Interface

clk_sd Input SD Clock

clk_sd_inv Input Inverted SD Clock

SD_CMD cmd_di sel_sd_resp sel_resp_en INOUT IN OUT OUT

SD4 bit mode: Command Line SD1 bit mode: Command Line SPI mode: Data Input

Command Input Command Output Command Output Enable SD_DAT0 data0 sel_tx_dat0 sel_tx_dat0_en INOUT IN OUT OUT

SD4 bit mode: Data Line 0 SD1 bit mode: Data Line SPI mode: Data Output

SD4 bit mode: Data Line1 or Interrupt (optional)

SD1 bit mode: Interrupt SPI mode: Interrupt

SD4 bit mode: Data Line2 or Read Wait (optional)

SD1 bit mode: Read Wait (optional) SPI mode: Not Used

SD4 bit mode: Data Line 3 SD1 bit mode: Not Used SPI mode: Card Select Data3 Input

Data3 Output Data3 Output Enable

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CLK/RESET/SUPPLY Interface

RSTN INPUT Hardware power on reset Input to SD4.1

device IP

PLL_EN INPUT PLL lock enable Input to SD4.1 device IP

RCLK (1*) INPUT Transmit Reference clock input to SD4.1

device IP from host

PCLK INPUT PLL clocked clock Input to SD4.1 device IP

Tx Interface

TD (8/16 bit) Output Transmit Data for Tx Block

TDM (1/2 bit) Output Coding Mode (0: D-Symbol, 1: K-Symbol) TDM (8/16 bit) Output Transmit Data for Rx Block

TDM (1/2 bit) Output TDR Coding Mode (0: D-Symbol, 1: K-Symbol)

CT[7:0] Output PHY Control (CT[3:0] = PINIT/PCMD

depending on MODE) Rx Interface

RD (8/16 bit) Input Receive Data of Rx Block

RDM (1/2 bit) Input RD Coding Mode (0: D-Symbol, 1: K-Symbol)

RDT (8/16 bit) Input Receive Data of Tx Block

RDTM (1/2 bit) Input RDT Coding Mode (0: D-Symbol, 1: K-Symbol)

ST[7:0] Input PHY Status

Note:

1* Transmit Reference clock is input for SD4.1 device IP and output for SD4.1

host IP.

4

SoC Level Integration

4.1

Deliverables



RMM-compliant synthesizable RTL design in Verilog



Easy-to-use test environment



Synthesis scripts



Technical documents



User guide

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4.2

Verification Environment

The SD4.1 Device IP core has been verified in the simulation environment using the

behavioral models of the surrounding environment (RTL verification).

Figure 3: Verification Environment of SD 4.1 Device IP

4.3

Verification Deliverables



Comprehensive suite of simulation tests for ease of SoC integration



Verification components and test files provided



Verification environment and test suite well documented

4.4