Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies

CIRCUITREE®

Fiber Weave Effect:

Practical Impact Analysis and

Mitigation Strategies

Jeff Loyer, Intel® Corp.

[email protected]

Richard Kunze, Intel® Corp.

[email protected]

Xiaoning Ye, Intel® Corp.

[email protected]

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This paper outlines the findings of Intel’s Fiberweave Work Group which investigated short and long term strategies for dealing with the negative signal integrity effects of fiberglass weave in the materials of which circuit boards are made. It discusses the methods used to quantify the impact of fiberweave, strategies studied to mitigate it, and validation of effectiveness of those strategies.

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Jeff Loyer is currently the Signal Integrity Lead for Intel’s Enterprise Server Division. He has authored articles on

Signal Integrity for both EDN and Printed Circuit Design & Manufacture magazines. He holds a bachelor of science degree in electrical-engineering technology from Arizona State University (Tempe), has taught signal-integrity classes both inside and outside Intel, and enjoys the outdoors, tennis, classical guitar, skiing, and teaching.

Xiaoning Ye is currently a senior analog engineer with the Digital Enterprise Group (DEG), Intel Corporation,

Hillsboro, Oregon. He leads the simulation working group responsible for signal integrity of high speed differential interconnect in Intel Server systems. He is focused on researching and developing next generation multi-Gbps bus interfaces, and signal integrity analysis methodologies. His past experience in Intel includes research and development of Electromagnetic Compatibility solutions for high speed interconnects, and leading a cross-Intel team to define clocking strategy and solutions for future Enterprise platforms. Xiaoning Ye received his Bachelor and Master degree in electronics engineering from Tsinghua University, Beijing, China, in 1995 and 1998 respectively, and Ph.D degree in electrical engineering from University of Missouri – Rolla in 2000. He is the author or co-author of 8 IEEE journal papers, and 15 conference papers. He is also the reviewer for several IEEE journals and international conferences.

Richard Kunze is currently a senior analog engineer and Technical Lead in the Platform Validation and Enabling

(PVE) organization within the Digital Enterprise Group (DEG), Intel Corporation, DuPont, Washington. He leads the working group responsible for signal integrity of the PCIE bus interface in Intel Server systems. His past experience in Intel includes research and development of passive EM structures for high speed interconnects and advancing the development of package power delivery modeling methodology and its application to package designs for Enterprise CPU’s and chipsets. Richard Kunze received his B.S. degree in physics from the University of Rochester, Rochester, NY, in 1973 and Ph.D. in physics from SUNYAB, Buffalo, NY in 1980.

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The Intel Fiberweave Work Group was created in June of 2005 to define Intel’s short and long term strategies for dealing with the negative signal integrity effects of fiberweave in the materials which circuit boards are made of [1-4]. This document outlines the findings of that Work Group, including:

1) Quantifying the fiberweave effect – effect vs. length and frequency (answering the question “When is it a problem?”). To accomplish this, we:

a. Derived an accurate delta Er number to represent the effect, using voluminous data from test boards, and b. performed simulations using that number to assess the impact on high-speed differential eye height and

width for a variety of bus frequencies and lengths

2) Deciding on short and long term solutions for the fiberweave effect. This was accomplished by assessing the relative merits of a broad variety of possible solutions and narrowing those down to:

a. Using special layout and routing (floorplan designs for 45 degrees; require <2” orthogonal routing; or use Zig-zag or angled routing)

b. Having the designer rotate the image approximately 10 degrees c. Rotating the glass (as a long term solution)

3) Demonstrating the practical application of the proposed solutions – building test boards to test a proposed image rotation BKM and assess its effectiveness.

This paper focuses on comprehending and solving the problem for High Volume Manufacturing (HVM) systems, including defining the interconnect performance range where the effect must be considered, and suggesting practical solutions – those that are cost-effective. We also briefly mention other mitigation techniques that might be applied to lower volume applications, such as test boards (exotic materials, for instance).

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Typical printed circuit boards are constructed from various woven fiberglass fabrics (Figure 1), strengthened and bound together with epoxy resin. The glass and epoxy have relative permittivity’s (Er, aka Dielectric Constant, or Dk) of ~6 and ~3.5 [4], respectively, presenting a non-homogeneous medium for signal propagation. Traces running parallel to the board edge (and therefore the weave) are especially susceptible to this non-homogeneity (these will often be referred to as “routed orthogonally” in this paper). For instance, in Figure 2, note the fiber (weave) bundle and epoxy regions. The 2 traces in Figure 2, making up the 2 halves of a differential pair (designated “D+” and “D-“), are running over the different materials (epoxy vs. fiberglass weave), see correspondingly different Er values, and have different propagation properties (velocity and loss primarily).

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Figure 1: PCB Woven Fiberglass Fabric Constructions

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Figure 2: Inhomogeneous nature of a PCB as shown in a cross section

At high data rates the difference in propagation velocities leads to skew between the 2 traces which can amount to a substantial fraction of the transmission unit interval, resulting in an increased common mode voltage (Figure 3) and a correspondingly degraded differential signal (Figure 4) [1]. In addition, the resulting common mode signal can become a source of increased crosstalk and EMI in the system.

Figure 3: Effect of skew on differential and common mode signals

Figure 4: Effect of skew on differential eye

During the past several years, researchers both from within Intel and outside have investigated this effect [1-4]. Typical results from these studies indicate that differential pair conductor skews on the order of 1-10 ps/inch are readily attainable in typical PCB constructions. But, the effect had not been rigorously quantified, nor had an exact strategy to deal with the problem been laid out. The Work Group was formed to close these gaps. The team consisted of members from a variety of disciplines – signal integrity, materials, manufacturing, procurement, CAD (PCB layout), board design, Platform Design Guide owners, validation, and platform architecture. The focus was on finding solutions for high volume products, and any proposed solutions were required to meet the requirements of all those disciplines as they pertain to HVM (High Volume Manufacturing).

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The Work Group’s first goal was to quantify the difference in Er between 2 halves of differential pairs for typical traces and board materials. Fortunately, another internal Intel Working Group had earlier built hundreds of test boards from

Weave bundle Epoxy only D+

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various PCB vendors, and made tens of thousands of TDR measurements on PCB traces (both microstrip and stripline) to statistically quantify the phase skew due to the fiberweave effect.

A total of 9705 data points were selected of 58,800 differential trace TDR measurements (only stripline routing on FR4 material; microstrip results are expected to be similar). The distribution of the phase skew between D+ and D- of each differential pair is shown in Figure 5. A thorough analysis of the data showed that a propagation velocity skew of 60ps/4” (780ps – 720ps for 4”) was an appropriate number to use as a “representative” worst-case scenario (it was not the absolute worst-case expected, but it did represent a limit that only a very small portion of traces would exceed). This corresponds to a delta Er of approximately 0.8, as shown in Figure 6.

Extreme outliers probably due to open traces and vias

Figure 5: Skew Data from test boards

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Manual measurement of 8 boards showed a maximum skew of 50ps/4inch, validating the maximum 60ps/4inch number.

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Once armed with the Er delta number, simulations were performed to assess the impact on typical PCB topologies. The topology of the full-link Hspice simulation is shown in Figure 7. It has a transmitter with either 2-tap or 6-tap equalization. Both transmitter and receiver package/socket are based on current typical components. The major routing is 91-ohm stripline with fiberweave effect considered. There is 1” of stripline routing at both ends without any fiberweave effect. 2/6 tap buffer Tx Package LGA socket 2/6 tap buffer Tx Package LGA socket

CPU Board (Stripline)

Rx Rx Package LGA socket Rx Rx Package LGA socket

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Figure 7: Topology for system impaction simulation

Figure 8 illustrates the cross-section of the stripline routing. The dual reference stripline has a distance of 6 mils to one reference plane, and 7 mils to the other. Trace width is 5 mils; intra-pair spacing is 6 mils; and inter-pair spacing is 18 mils. The dielectric is modeled by two separate halves with a difference of 0.5 or 0.8 (nominal value is 4.0). Modeling of fiberweave effect for aggressors (left and right pairs) is not included, since we don’t have any data on where to further split the Er. Hence, crosstalk is not included in the post processing of simulation results.

Er1

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Figure 8: Cross-section of the stripline routing in the system impact simulation

In the Hspice simulation, a “typical” value for each link component was used. The buffer has a differential voltage swing of 1.1V. Four different link bit rates were simulated: 2.5GT/s, 5GT/s, 6.4GT/s, and 8GT/s. For each bit rate case, a wide range of reasonable routing lengths were considered. To be more realistic, a 2-tap buffer was used for 2.5GT/s

simulation (since 2.5GT/s PCI-express bus uses 2-tap de-empahsis), and 6-tap buffers were used for the rest of the bit rates.

An Intel in-house tool was used to identify the optimal tap coefficient for each individual case. This makes the study a little bit optimistic compared to real system application (where the tap coefficient is not adjusted to compensate for fiberweave effect). Pulse response was then obtained from Hspice simulation for the various link speeds and routing lengths mentioned above (two examples are shown in Figure 9). A few observations can summarized from those pulse responses:

• pulse response for the 2” link does not see much impact from the fiberweave, • the amplitude of the pulse response gets smaller as the link length increase,

• the higher the bit rate or the larger the Er difference, the faster the decreasing of amplitude,

• when the link exceeds certain lengths, the pulse response can be severely distorted and “split” into two peaks, which may cover the width of two UIs.

2” 8” 14” Delta Er = 0 0.5 0.8 2” 10” 18” Delta Er = 0 0.5 0.8 26”

Figure 9: Pulse response for different major routing lengths @ 2.5 & 8.0GT/s

An Intel in-house tool was then used to post-process the pulse response to get the eye-height and eye-width for the above cases. The results were consistent with the observations of the pulse responses: the eye opening of a 2” link does not see much fiberweave effect for the studied bit rates; and the faster the bit rate, or the larger the Er difference, the shorter the link that can tolerate the fiberweave effect. Another interesting observation was that Eye Height impact of fiberweave is approximately proportional to the trace length, while the Eye Width impact from fiberweave increases exponentially with the trace length.

The results are re-formatted into an easy look up table shown in Table 1. For 2.5GT/s link, fiberweave is not critical for eye opening until link is 10” or longer, while for 5GT/s or 6.4GT/s link, the impact becomes prominent for 5” length, and for 8GT/s link, a 4” length can see significant fiberweave impact.

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267 160 110 55 30 5 0 4GT 100 94 68 0 5” 305 24 12” 47 14” 124 18” 240 140 70 0 8GT 303 218 115 84 0 6.4GT 246 127 71 40 0 5GT 0 0 0 0 0 2.5GT 10” 8” 6” 4” 2” Length 267 160 110 55 30 5 0 4GT 100 94 68 0 5” 305 24 12” 47 14” 124 18” 240 140 70 0 8GT 303 218 115 84 0 6.4GT 246 127 71 40 0 5GT 0 0 0 0 0 2.5GT 10” 8” 6” 4” 2” Length

EH reduction Unit: mV

EW reduction Unit: UI

Table 1: EH and EW reduction lookup table for Er difference of 0.8

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A more subtle problem caused by the Fiberweave effect is introduction of AC Common Mode voltage on the differential pair. The ACCM effects are less straightforward to analyze than eye height and width, since ACCM will decrease at longer lengths due to conductor and dielectric losses (see Figure 10), and ACCM effects are more ambiguous. They may not directly affect system operation even though ACCM specifications are violated (for instance, if the traces are routed in stripline, the EMI effects and crosstalk may be negligible).

The ACCM effects, when the signals traverse reference plane changes (e.g., at packages, vias, connectors), may be significant and difficult to quantify. The simulation tools and models may not lend themselves to this unique analysis. Straightforward recommendations regarding ACCM are not available at this time.

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Lossy ACCM Loss Curve e-(0.11*l) Length, inches AC CM Nois e

Figure 10: ACCM vs. Channel Length

The following figures show the approximate ACCM noise introduced by the Fiberweave effect (assuming an Er delta of 0.8) occurring on various lengths of channel at various transfer rates. Note that, for PCIe rates of 2.5GT/s, the

ACCM spec. would be violated after approximately 4” of differential trace pair had run over a bundle weave (Figure 11).

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Figure 11: ACCM noise levels vs. Channel Length @ 2.5GT/s (Er delta = 0.8)

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Figure 12: ACCM noise levels vs. Channel Length @ 5GT/s (Er delta = 0.8)

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Figure 13: ACCM noise levels vs. Channel Length @ 8GT/s (Er delta = 0.8)

Below (Figure 14) is a summary of ACCM noise vs. length and transfer rate. Note that ACCM is a function of the magnitude of the voltage at the receiver, which declines w/ transfer rate, so the peak ACCM voltage induced actually decreases with higher transfer rates.

ACCM Peak Value vs. Length and Transfer Rate

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Figure 14: ACCM noise levels vs. Channel Length and Transfer Rate (Er delta = 0.8)

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The Work Group made a comprehensive list of possible techniques to mitigate the fiberweave effect, as follows (in no particular order):

1. Offset “jog” routing per weave pitch 2. offset “jog” routing per pair spacing 3. Zig-zag Routing

4. Angled Routing

5. PCB vendor rotates image 6. Designer Rotates Image

7. Rotate Glass

8. Advanced materials: Nelco – SI material (NE glass) 9. Specify tighter (or coarser) weaves

10. Adjust trace spacings for weave 11. Electric deskew

12. Random weave (matte?) 13. Subtract from margin

14. Floorplan design for 45 degrees

15. Glass-less materials: polyimide, speedboard 16. Multi-ply w/ different pitches

17. Multi-ply w/ different pitches (2)

Note: for a detailed description of each technique, see Appendix A.

Each item on the list was evaluated in terms of material cost, design engineering time, and effectiveness; most were rejected for not being reasonable options for High Volume Manufacturing products. For instance, any proposal that relied on specifying exact weave type was automatically rejected, since that was deemed unreasonable (vendors will usually have preferred weave types; specifying another weave type would have substantial cost and time impacts). The Work Group narrowed down the possible mitigation techniques to the following suggested migration techniques: 1) Determining that the effect isn't a problem at a particular bus' frequency and lengths per Table 1.

2) Absorbing the impact to eye height and width. If solution space simulations run with models that accurately include the fiberweave effect prove adequate “eye” and acceptable ACCM noise, no further mitigation techniques are necessary. This is attractive for short busses with lots of margin.

Note: The ACCM effects, when the signals traverse reference plane changes (e.g., at packages, vias, connectors), may be significant and difficult to quantify. The simulation tools and models may not lend themselves to this unique analysis. Straightforward recommendations regarding ACCM are not available at this time.

3) Special Layout and Routing

Some designs may be able to place their chips and high speed busses such that the busses don’t run parallel to board edges for extended lengths or, if/when they do, routing practices are followed that mitigate the effect. This will take careful planning and checking, but might be an attractive alternative to more all-encompassing solutions (e.g., rotating the image).

a. Floorplan Design for 45 Degrees

Some designs’ floorplan automatically forces the routing into non-orthogonal angles. High speed differential routing on some desktops, or the memory routing on some servers, automatically tend to be angled. All high-speed busses must conform to non-orthogonal layout & routing for this to be effective. Also note that 45° routing is not as effective at mitigating the effects as 13° (see Table 2), and this might not be as effective for extremely long routing lengths.

b. Require <2” orthogonal routing

Several simulations were performed to study the effect on actual product topologies. There was a consistent finding that, when the fiberweave effect was limited to 2”, the impact on eye height and width was small (though there might be significant ACCM introduced). The Work Group concluded that a valid solution is to stipulate no more than 2” of parallel routing (relative to the board edge) is allowed on a bus. This might be an especially attractive solution for platforms all high speed differential busses are rarely orthogonal to the board edges. The major caveats are that routing through pin fields BGA fields might add up to more than 2”, and all high-speed busses must conform to non-orthogonal layout & routing for this to be effective. c. Zig-Zag or Angled Routing

For some designs, these were considered options, though problematic ones. CAD tools don’t support easy routing at angles other than 0, 45, or 90 degrees. Small changes in routing (adding vias late in a design, for example) might cause very painstaking and time-consuming re-routing. These solutions might be appealing to designs that have no other option. This might become more attractive if CAD tool vendors enhance their tools to allow 10° (or other arbitrary angles) routing all.

A slight alternative that can be more attractive is to use an angle of 11.31 degrees, instead of 10. At this angle, the traces can remain on-grid during the zig-zag, as shown in Figure 15.

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Figure 15: 11.31 Degree Zig-Zag

4) Designer Rotates Image

Rotating the entire design, relative to the board edge, ensures traces normally routed at 0° and 90° will not align to the fiberweave, which is parallel to board edges, and the effect will be mitigated. A large portion of our research was spent in validating this technique, and that work is described in detail below.

5) Rotate Glass

While this currently is not an option, it might become the preferred method in the future. Intel and IPC are pursuing the enabling effort to facilitate this technology for future generations of platforms.

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It does not take much of an angle between the traces and weave to resolve the fiberweave problem – a trace merely has to cross 2 weave bundles along its length, so that the effect on the 2 adjacent traces is equalized (see Figure 16).

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Figure 16: Calculation of Angle necessary to Mitigate Fiberweave Effect

Figure 17 shows that, for trace lengths affected (>2”), only a degree or two of rotation is needed. But, measurements of boards have shown the weave itself can be skewed as much as 5° (and possibly more) relative to the edge of the board. Rotating the trace by 10° ensures all traces will be sufficiently skewed, relative to the weave, to mitigate the fiberweave effect.

Image Rotation vs. Length (to cross 2 bundles 20 mils apart)

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Figure 17: Angle vs. Line Length to cross 2 Bundles

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3 sets of test boards were designed, built, and measured (using TDR/TDT) to demonstrate mitigating the fiberweave effect by rotating the image, and perfecting a technique to perform that rotation:

1) “CV Fiberweave Test Boards” which included:

a. A “CV” (Compatibility Validation) platform stackup with microstrip and stripline routing layers (with Isola IS620 low-loss materials)

b. A design allowing quick TDR/TDT measurement of the skew between halves of several differential pairs (110 per board, see Figure 18).

c. Designs rotated to 0, 12.76, and 45 degrees (note: 12.76° was chosen since it was the largest angle the design could be rotated without forcing use of a larger panel)

d. Traces routed horizontally and vertically e. Traces of 2, 6, and 10 inch lengths

f. 10 boards of each orientation were built and measured 2) “REB3 Test Boards” which included:

a. A design allowing quick TDR/TDT measurement of the skew between halves of differential pairs b. Microstrip and stripline stackups representative of current platforms (with standard FR4 materials) c. 10” traces routed horizontally, horizontally plus 10°, vertically, and vertically plus 10°.

d. 5 boards were measured

3) “FR4 Fiberweave Test Boards” which were similar to the CV Test Boards, except the design had: a. Slightly different inter-pair spacing to try to optimize it to recreate the effect more repeatedly. b. A standard FR 4 stackup with worst-case weaves (1080, 106)

c. Rotations of 0 & 10 degrees

d. 20 boards of 0 degrees were built and measured; only a single 10 degree board was measured (since previous boards had proven 10 degrees to be effective)

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Horizontal Vertic al 10” Microstrip (L1) 10” Stripline (L16) 6” Microstrip (L1) 6” Stripline (L16) 2” Stripline (L16) 1 0 ” M ic ro s tri p (L 1 ) 1 0 ” S tr iplin e (L 16) 6” Micr o s tr ip ( L1) 6” St rip line ( L 16) 2” St rip line ( L 16) 2” M icro s tr ip (L 1) 10 samples each TDR from here TDR from here TDT site

Figure 18: “CV” and “FR4 Fiberweave” Test Board Layout

Figure 19: REB3 Test Board Layout

The test boards conclusively demonstrated the fiberweave effect and the effectiveness of image rotation to alleviate it. The data and the conclusions drawn from it are given below.

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The results of the skew measurements for the CV Test Boards is given in Table 2. Some things to note: 1. With no (0°) rotation, a 2” trace had 20ps of differential skew – 10ps per inch!

2. A rotation of ~13° is very effective at alleviating the problem 3. A 45° rotation is not as effective (the reason is shown in Figure 20)

4. The data showed a max Er delta of 0.56: 56 . 0 02 . 4 58 . 4 85 " 2 341 85 " 2 364 2 2 = − = ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎣ ⎡ _⎟ ⎠ ⎞ ⎜ ⎝ ⎛ − ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎣ ⎡ _⎟ ⎠ ⎞ ⎜ ⎝ ⎛ inch ps ps inch ps ps 0° Ro tati on 12 .76 R ota tio n 45 ° R ota tio n

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Max skew of 6" Trace 30ps 4ps 6ps

Max skew of 2" Trace 20ps 3ps 3ps

Table 2: CV Differential Skew Results

This trace runs over “knuckles” while its

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Figure 20: 45° Flaw

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The REB3 boards showed a case of 15ps/10inch skew on both stripline and microstrip without any rotation, but only 3ps/10inch skew with 10° rotation.

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The largest skew (per inch) measured on the FR4 boards w/o any image rotation was 6.3ps/inch on a 6” trace, corresponding to an Er delta of 0.28. This is much less than the 0.8 number we deduce to be a more representative value for worst case, but this isn’t surprising given the limited sample size. And, looking at the TDR waveform of the worst-case trace showed that the differential pair was aligned with weave for only a small portion of its length. For the FR4 Test Board with 10° rotation, the largest skew measured on 10” traces was 2 ps, confirming that rotating the image had eliminated the skew effect completely. Measurements were stopped after the data from the first board’s 10” traces showed essentially no skew on any of those traces (as expected).

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To test our CAD tools and HVM’s ability to rotate a design 10°, a state-of-the-art 4-way server design (see Figure 21) was rotated, boards built, and assembled. To our dismay, the first boards that came back were not rotated. The manufacturer un-rotated the design (see Figure 22) in order to fit the board on the panel, and under the assumption that the 10° rotation was an error that could be corrected without notifying the client. It highlights the difficulty in rotating a design until the process becomes more commonplace. Until then, we recommend that:

1. The intentional rotation be spelled out very clearly and unambiguously, including large notes on fab drawings and perhaps discussions with the vendor before the boards are built (see Figure 23).

2. Perhaps “Rotation Coupons” could be added to the boards (in the triangle vacated by the rotation, for instance), with the soldermask removed. These would allow the designer to quickly determine if the raw panel had been indeed rotated and would also help force the vendor to keep the design rotated (un-rotating the design would lose the coupons).

A second set of rotated product boards were built, assembled, and tested without any problem. These were verified to be properly rotated. Panel edge Pa ne l e dge Panel edge Pa ne l e dge

Figure 22: Note explaining Un-Rotated Product Design

Figure 23: Fab Drawing Highlighting Intentional Design Rotation

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The fiberweave effect must be comprehended and properly accounted for in future high speed bus designs. Table 1 shows when it will and won’t need special accommodations to alleviate its effects. Rotating the image 10° is an extremely effective means to mitigate the negative effects, if necessary. Other options are available, if image rotation is not optimum.

The Work Group has conclusively quantified the negative effects of fiberweave on high speed differential busses and proven the viability and effectiveness of proposed techniques to mitigate those effects. Future products will use these results to analyze the impact on their design, and incorporate the appropriate techniques as needed to ensure the fiberweave doesn’t catastrophically degrade signal quality on critical PCB interconnects.

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Special thanks are due Bill Alger, Subas Bastola, Richard Herrick, Jay Hildebrand, Bryce Horine, John Kelbert, Patrick Sheehan, John Tomlin, Kai Xiao, and Bin Zou for their invaluable contributions to the Work Group.

This publication was first presented at DesignCon 2007. It is posted with the kind permission of DesignCon and the consent of the authors.

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1. Howard Heck, Steve Hall, Bryce Horine, Tao Liang; “AC Common Mode Conversion in Multi-Gb/s Differential Printed Circuit Boards”; DTTC 2004 Paper

2. Dave Coleman, Scott Gardiner, Mohammad Kolbehdari, Stephen Peters; PCI Express Electrical Interconnect Design”; Intel Press Book, 2004

3. Stephen Hall; “Requirements for Multi-GHz Transmission Line Modeling”; IEEE Workshop Paper; 26-May-05 4. Scott McMorrow and Chris Heard; “The Impact of PCB Laminate Weave on the Electrical Performance of

Differential Signaling at Multi-Gigabit Data Rates”; DesignCon 2005 Paper

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The following are descriptions of the various mitigation techniques investigated by the Work Group (in no particular order).

1) Offset “jog” routing per weave pitch 2) offset “jog” routing per pair spacing 3) zig-zag routing

4) Angled routing

5) PCB vendor rotates image 6) Designer Rotates Image 7) Rotate Glass

8) Advanced materials: Nelco – SI material (NE glass) 9) Specify tighter (or coarser) weaves

10) Adjust trace spacings for weave 11) Electric deskew

12) Random weave (matte?) 13) Subtract from margin

14) Floorplan design for 45 degrees

15) Glass-less materials: polyimide, speedboard 16) Multi-ply w/ different pitches

17) Multi-ply w/ different pitches (2)

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Regardless of glass bundle pitch, occasionally offset long traces by the intra-pair spacing, forcing each trace onto the track that its neighbor was on.

But, there are instances when this doesn’t solve the problem (case C below):

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R

Introduce zig-zag when routing for an appreciable length. Angle of zig-zag has to be 10 degrees or more.

D

D

₁

D

₂

D

-D

₁

D

₂

D

D

-D

D

₁

D

₂

D

-D

₁

D

₂

4)

A

R

Rotate the trace routing; angle has to be 10 degrees or more.

5)

PCB

V

R

I

Board manufacturers rotate the board image on the board panel.

Board Edge Board Edge

6)

D

R

I

Rotate the file in CAD or CAM tools

7)

R

G

Rotate the glass before cutting it into a panel.

CircuiTree® 21

8)

A

M

:

N

–

SI

M

(NE

G

)

Materials with less variation between Er of epoxy (~3.2) and glass (6.6 for standard E-Glass, ~4.4 for NE-Glass) – Nelco N4000-13SI, which uses NE-Glass

9)

S

T

(

C

)

W

Specify a weave that has such a fine (or coarse) mesh that a differential pair can’t run over a trough and peak.

Fine Weave

Coarse Weave

10)

A

T

S

W

Knowing glass bundle pitch, specify trace spacing that keeps each half of a differential pair over the same part of the weave as its partner.

11)

E

D

Have Tx or Rx adjust for skew.

12)

R

W

(

?)

Patternless weave, or pattern that can’t align with traces.

13)

S

M

Calculate new total lengths based on worst-case alignment.

14)

F

D

45

Place parts so that routing automatically wants to be 45 degrees (or some other pronounced skew). Layout may be such that routing automatically ends up non-orthogonal.

15)

G

-

–

,

Use materials w/o glass reinforcement.

16)

M

-

/

For stripline only: use plies above and below with different pitches to minimize the “average” effect.

17)

M

-

/

(2)

For stripline only: use plies with different pitches to minimize the “average” effect.

CircuiTree® 23