WiSER: Dynamic Spectrum Access Platform and Infrastructure

WINLAB

I. Seskar, D. Grunwald, K. Le, P. Maddala, D.

Sicker, D. Raychaudhuri

Rutgers, The State University of New Jersey

University of Colorado, Boulder

Contact: Ivan Seskar

seskar (at) winlab (dot) rutgers (dot) edu

WiSER:

Dynamic Spectrum Access Platform and

Infrastructure

WINLAB

Cognitive Experiments at Scale

Urban

300 meters 500 meters

Suburban

20 meters ORBIT Radio Grid

Office

30 meters

Radio Mapping Concept for ORBIT Emulator

400-node Radio Grid Facility at WINLAB Tech Center Programmable

ORBIT radio node

URSP CR board Current ORBIT sandbox with GNU radio



ORBIT radio grid testbed currently supports ~10 USRP and

~32 USRP2 (GNU) radios, 100 low-cost spectrum sensors,

WARP and GENI CR-Kit platforms

Why (CRKIT) Framework ?

Abstract lower level design complexities from Users INNOVATION CYCLE

Live system runs

Focus on Creativity, not Engineering

Complexity :

Split Baseband in two domain spaces :

•

Dynamic

– Swappable Communication

APPs (creative problem)

•

Static

- Open-sourced System-on-Chip

(complex engineering problem)

CRKIT = make real-time and

wide-tuning radio a viable solution for large scale experiments.

WDR from Radio Technology Solutions

FSoC Features

 Access to lower level resources thru APIs  VITA radio transport protocol for radio control

 Networking capable node

 Support up to four dynamic APPs

 Library of Open-sourced Communication APPs

 Static Framework utilization level < 15% for V5SX95, even less for newer technologies, for ex. Virtex7 .

 Transparent to underlying FPGA technology.  Can be ported to future HW platforms and newer FPGA technologies.

WINLAB

What is GENI CRKIT Framework ?

Baseband Processor :

 FPGA-based off-the-shelf board

 Control up to 4 full-duplex wideband radios

 FPGA-based System-on-Chip (FSoC) implementation

Wideband Radio (WDR) Module :

 Wideband : tunable range 300MHz to 7.5GHz

 25MHz bandwidth

 50Msps 12-bit ADC, 200Msps 12-bit DAC

 50us switch between frequencies

Actual CogRadio with enclosure, 2 WDRs

CRKIT baseband with 4 stacked radios

CRKIT

HW

Platform PlatformSW IntegrationORBIT

Wideband

Radio BasebandFlexible Embedded HOST Layer Exp.PHY ScalabilityExp.

FPGA-SoC Comm.APPs RadioAPIs OMF

Spiral II GENI project: CR kit HW

Wide-tuning Digital Radio (WDR) block diagram



Range of baseband FPGA

platforms



4 (2) configurable radio

modules for phased or

smart antenna

applications with



Phase I: Each module allows

two 25 MHz bands from 300

to 6000 MHz



Phase II: Each module

allows two different 300 MHz

bands from 100 to 7500 MHz



Each module supports

independent full duplex

operation.



1 usec RF frequency

switching time



Switched antenna

diversity for both TX and

RX channels.n

WINLAB

CRKIT Programming Model

Network

HOST CRKIT Application development CRKIT development Comm. APP EmbeddedSW GUI Algorithm System

Debugging SystemTest CR DSA VerilogVHDL/ MathworksSimulink NetworkingIP ConfigurationHW CMD ParsingHost DHCP/ARP Lookup Tables/_RF ETH/VITA

APP Development Flow

MATLAB Simulink Flow CRKIT Flow APP Specification Design dynamic APP APP Validation Compile APP Link APP to Framework Compile Framework Generate FPGA bit file

Download to Hardware PCORE boots Execute CRKIT Embedded SW Xilinx ISE Flow CRKIT Embedded SW HW Config. Networking Host CMD Parsing

1. Get IP address using DHCP 2. Discover HOST

3. Configure CRKIT hardware 4. Parse HOST commands

Lookup Table Configuration RF Control dynamic Config. (ETH/VITA) initial config.

WINLAB

WiSER – NSF CRI Project



Use off-the-shelf hardware produced by

commercial OEM vendors



System integration with existing software

components



Community release of open-source software

platform and related software radio design



Tools including PHY/MAC hardware accelerators,

spectrum measurement and protocol

components.



Reference implementation on two campuses of a

WiSER Baseline Hardware



ZedBoard baseboard

(Zynq XC7Z020 device)



Dual-core ARM®

Cortex™-A9



256 KB on-chip RAM



Gigabit Ethernet, 2x

SD/SDIO, USB,CAN, SPI,

UART,I2C



512 MB DDR3, 256 Mb

QSPI Flash



85K Logic Cells, 106K FF



220 Programmable DSP

Slices (18x25 MACCs)

Zynq-7000 SoC / Analog Devices

Software-Defined Radio Kit



Analog Devices FMC RF Front-end



Software tunable across wide frequency range (400MHz to 4GHz) with

125MHz channel bandwidth (250MSPS ADC, 1GSPS DAC)



RF section bypass for baseband sampling

WINLAB

CRKit Phase II RF Front-end



Dual full duplex operation 300 - 6000 MHz

(bandwidths up to 500MHz).



Transmitter: dual 16 bit 800MSps DAC, filtering, IQ modulator, RF

filtering and power amplifier.



Receiver: LNA, selectable RF filters, IQ demodulator and dual ADC (8

bits @ 1000 MSps or 12 bits @ 640 MSps)



Features: +10dBm of output power, 50 µsec. frequency hop, carrier

lock to internal or external reference, carrier phase adjust, 32 dB gain

adjust, carrier feedthru suppression and sideband balance adjustment.



+10dBm of output power, 50 usec. frequency hop, carrier lock to

internal or external reference, carrier phase adjust, 32 dB gain adjust,

carrier feedthru suppression and sideband balance adjustment.

WiSER HW Extensions

16-core (64-core)

Adapteva

processor hosted by

the

Zedboard

motherboard,

as shown below

The Epiphany multi-core

chip daughter card

WINLAB

Future Framework Architecture

1. Dual-core ARM processors

• Linux support

• Dual AXI bus architecture • Independent Data and Control

traffic

2. Independent APP sampling rates • Support Multirate and Multi-APP

systems

• Decoupling of APP clock domains from overall Framework.

• Permits Spectrum Sensing APP + Communication APP in same architecture

3. Applications

• Reuse previously designed APPs • NC-OFDM • Spectrum Sensing 4. RF • 400MHz to 4GHz tuning range • 125MHz Channel Bandwidth (250MSPS ADC, 1GSPS DAC) • Full-duplex