nexus 7 schematic

(1)

5 4 3 2 1

D D

C C

B B

A A

Size Project Name Rev

Date: Sheet of

Title :

Engineer:

C 1 60 Friday, March 02, 2012 ASUSTeK COMPUTER INC. EPAD

01.Block Diagram

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

01.Block Diagram

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

01.Block Diagram

2.0

ME370T

Richard Lin

ELAN

PWR_I2C_1V8

Battery Gauge

OV5650

Rear

Camera module

Antenna

XTAL 12MHZ

XTAL 37.4MHz

XTAL

32.768KHz

01.Block Diagram

02.POWER TREE

03.Power On/Off&Reset Timing

04.Power Sequence map

05.T30 Core & Fuse

06.T30 SYS IF

07.T30 GMI IF

08.T30 DDR

09.T30 DSI/CSI,CAM

10.T30 LCD

11.T30 HDMI,VGA

12.T30 BB,UART

13.T30 AUDIO

14.T30 USB,HSIC,ICUSB

15.T30 SDMMC,eMMC

16.T30 PCIe

17.T30 NC

18.Boot Straps

19.DDR3L

20.LCD data EMI filter

21.LCD panel power

22.eMMC,SDIO I/F

23.Sensor

24.Debug Connector

25.Hall

28.NUVOTON NPCE795L-1

30.EC description

31.SMBus tributaries

32.I/O Connector

33.TP&IO_CON(MB)

34.Coin cell

35.Camera power

36.Camera ISP & Connector

37.Codec_ALC5631Q-VE

38.DSP_FM34

39.Audio Conn

40.HW_RF_Interface

41.WiFi+BT combo II

43.BCM4751 GPS

44.SW CON

46.HDMI Conn

47.EMC

48.Srew Hole

49.DC_JACK & BAT CON

50.Power Sequenc Logic

51.Power_Latch

52.LVDS transmitter_30

53.LCD panel connector_30

a54.TP&IO_Block Diagram

a55.TP&IO_Conn&SIM&SD

a56.TPIO_ATMXT768EXES

a57.TP&IO_TP CON

a58.TP&IO_POWER

a59.TP&IO_RST_SW

63.ALS_LSC3010

81_PW_+5VSUS_+3VSUS_TPS51125A

86_PW_2.85V&VDD_5V0_SYS

89_PW_Charger(BQ24745)

90_PW_A/D_IN

91.PMU-TPS65911 1/3

92.PMU-TPS65911 2/3

93.PMU-TPS65911 3/3

95.Force_off_recovery

96.Low_Low_BAT#

97.PWR_SW# Selection

99.HISTORY

OnSemi NCT72

JTAG_1V8

Debug Port

Broadcom BCM4751

PWR_I2C_1V8

E-COMPASS

Gyro sensor

Invensense MPU-6050

AICHI AMI304

DDC_I2C 5V0

GEN2_I2C_3V3

Gen1_I2C_1V8

UART_3_1V8

GEN1_SMB_3V3

UART_2_1V8

HDMI

Micro HDMI

PMIC

MAXIM

MAX77663

LVDS

LCD Panel

Tegra

ME370T (Nakasi)

1.0 2012/02/08

LCD_RGB_1V8

Transmitter

DDR3L x 32_1V35

DDR3L 256M x8 x4pcs

1333(667MHz)

ALC5642

I2S CODEC

I2S_1V8

MIPI_CSIB_1V2

GPS

Controls

32.768KHz

USB_3_3V3

Gen1_I2C_1V8

Aptina 1040

Power Button

Volume Up & Down

LSC3010

Light sensor

Original

Project Name

ME370T

Docking USB Port

Kai

Front

Camera module

Docking

**USB*3 , Line out ,**

Mic In , DC Jack

HSMMC x8_1V8

UART_4_1V8

Azurewave AW/NH-665

WIFI + BT

MIPI_CSIA_1V2

Thermal Sensor

EXTERNAL

SD SCOKET

eMMC 8GB

CAM_I2C_1V8

I/O Board & TP

Antenna

USB Conn.

USB_1_3V3

TI SN75LVDS83B

PWR_I2C_1V8

Internal D MIC

SDIO_1_1V8

Touch screen

HEADSET JACK

EXT MIC

Speaker

DMIC KNOWLES

SPM0423HD4H-WB

TCXO 26MHz

NUVOTON

NPCE795LA0DX

EC

GEN2_I2C_1V8

Audio DSP

FM34

HEADSET

Reset Button

Button FPC

Charger

SMB347

32.768KHz

CAM_I2C_1V8

NFC NXP PN65

Antenna

XTAL 27.12MHz

T30L

(2)

5 5 4 4 3 3 2 2 1 1 D D C C B B A A

Date: Sheet of

Title :

Engineer: Custom 2 60 Thursday, March 01, 2012

ASUSTeK COMPUTER INC. EPAD

02.POWER TREE

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

02.POWER TREE

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

02.POWER TREE

2.0

ME370T

Richard Lin

Charger

USB Conn.

SMB347

Dock Conn.

VDD_USB1_VBUS

Battery

DOCK_5V

VBATT

Power Source

VDD_AC_BAT

(VPH_PWR_CHGR)

page 49

Buck-Boost

TPS63020

page 48 EN_3V3_SYS(PMU GPIO3)

Boost

RT9276GQW

page 48 EN_5V0_SBY(T30 GMI_AD11)

PMIC

MAX77663

page 50~52 MBATT, MON, GPIO_INA & AVSD Internal Usage

SD0

SD1

SD2

SD3

VDD_1V0_GEN

VDD_1V2_SOC

+1.35V

T30 CPU 1.05V, 6.1A, Terga (Tj=90, 1.3GHz)

1.05V. 6A, PMIC

VDD_CPU

T30 CORE 1.2V, 2.5A, Terga 1.2V. 3A, PMIC

VDD_5V0_SYS

5V. 1A

LDO

S-1167

page 29

+3VSUS

3.3V. 2A

TP_3V3

for Touch Sensor

1.35V. 1.5A, PMIC

LDO4

LDO6

IN_LDO4/6 VDD_PMU_LDO4_1V2 T30 1.2V. 150mA, PMIC VDD_PMU_LDO6_3V_1V8 T30 3/1.8V. 150mA, PMIC U30 3.3V. 150mA U27 2.8V. 300mA

LDO

S-1132

page 31 U28 2.8V. 300mA

LDO

S-1132

page 31 CAM1_LDO_EN(T30 KB_ROW6) VDD_5V0_SYS enable

AVDD_CAM1 Camera AVDD

AVDD_VCM CAMERA AF VCM

CAM2_LDO_EN(T30 KB_ROW8)

VDD_SPK Codec Speaker Amp.

NFC_VBAT NFC VBAT

LDO3

LDO5

IN_LDO2

PMIC

MAX77663

page 52 IN_LDO3/5

LDO2

VDD_PMU_LDO2_2V8 T30 2.8V. 150mA, PMIC VDD_PMU_LDO3_2V8 for eMMC VCC 200mA

2.8V. 300mA, PMIC

VCORE_EMMC_S

VDD_PMU_LDO5 2.8V. 300mA, PMIC

+3VSUS_CPU

U1

Power SW

NCT352

page 5 EN_VDD_FUSE (T30 LCD_PWR1) T30 T30 T30 T30 TBD (no use)

VCC_LCD3V3

U8

Power SW

NCT352

page 21 EN_VDD_PNL (T30 LCD_M1)

VDD_PNL

U14

Power SW

NCT352

page 14

EN_AVDD_USB (MAX77663 GPIO2)

for LCD Panel

page 22 VDD_LVDS_30 VDD_LVDS_F_30 VDD_LVDS_PLL_30 page 25 VDD_ALS VDD_GYRO

for Thermal Sensor

VCORE_TEMP

for LVDS Transmitter

AVDD_ECOM

WiFi_BT_VCC_3V3

for Wifi/BT Module

page 41

GPS_VDD_BAT_3V3

page 41

for GPS

for Hall Sensor, ALS

page 26

for Gyro VDD

for E-compass AVDD

PMIC

MAX77663

page 50 GPIO_INB Internal Usage

VDD_LVDS_30

VDD_1V8_GEN_CPU

T30 T30 T30 T30 T30 T30 T30 T30 T30 T30 Q2

Load SW

PMOS

page 14 CORE_PWR_REQ

VDDIO_HSMMC

for eMMC VCCQ IOVCC_30 VCC LVDSVCC PLLVCC for LVDS Transmitter IOVCC

VDDIO_GYRO for Gyro VLOGIC

DVDD_ECOM for E-compass DVDD

WiFi_BT_VDDIO_1V8 for Wifi/BT Module

page 41

GPS_VDD_IO_1V8

for GPS

page 43

NFC_PVDD

for NFC

page 44

LDO7

LDO8

IN_LDO0/1

PMIC

MAX77663

page 52 IN_LDO7/8

LDO0

VDD_PMU_LDO0_1V0 T30 1.0V. 150mA, PMIC VDD_PMU_LDO1 VDD_PMU_LDO7_1V2 1.2V. 450mA, PMIC VDD_PMU_LDO8_1V2 1.2V. 300mA, PMIC

LDO1

No usage 150mA, PMIC T30 T30 T30 Max. 710mA

VDD_DDR3L

for DDR3L VDD

VDDQ_DDR3L

for DDR3L VDDQ

170mA x4, each DRAM chip

DRAM Chip 256Mb x8bits x4pcs

VCC_LED

page 21

VDD_CORE

VDD_RTC

VDDIO_SDMMC1

VDD_DDR_HS

AVDD_DSI_CSI

AVDD_PLLA_P_C

AVDD_PLLM

AVDD_PLLU_D

AVDD_PLLX

VDDIO_DDR

VDD_FUSE

VDD_3V3_GMI

AVDD_USB

VDDIO_PEX_CTL

VDD_DDR_RX

VDDIO_LCD

VDDIO_BB

VDDIO_UART

VDD_IO_AUDIO

VDDIO_SDMMC4

VDDIO_SDMMC3

AVDD_USB_PLL

AVDD_OSC

VDDIO_SYS

VDDIO_CAM

VDD_1V8_GEN

ME370T (Nakasi)

Power Tree

1.8V. 2.0A, PMIC page 27

VDD_1V8_CDC

DBVDD _{VDB_CDC} VCP_CDC CPVDD AVDD_CDC_F AVDD DACREF_CDC DCVDD VDD_1V8_DMIC for DMIC VDD

for Audio Codec VDDIO_CAM Camera VDDIO page 31 page 26 page 26 page 22 page 20 page 26 page 27 page 20 page 19 page 44 page 27 page 29

(3)

5 4 3 2 1

D D

C C

B B

A A

Date: Sheet of

Title :

Timing

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Timing

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Timing

2.0

ME370T

Richard Lin

1.8V

3.3V

1.8V

5V

AC_BAT_SYS

3.3V

TF300T_T3

Power On/Off

1.1V

5.0V

+1.8V

EN_VDD_1V35(EN_DDR, PMU GPIO7)

1.0V

1.35V

1.8V

System Clock(T3 26MHz)

+1.2V(for DDR3L 1.35V)

(PMU LDOs, Switched Rails)

VDD_CPU(PMU SW)

OTHERS

CPU_PWR_REQ(TERGA)

SYS_RESET#(PMU)

VDD_PEX(PMU LDO1) (EEPROM OFF)

VDD_SATA(PMU LDO2)

VDD_DDR_HS(PMU LDO8)

VCORE_eMMC_S(Q1603)

EN_3V3_EMMC(T3)

EN_3V3_SYS(PMU GPIO6)

CLK_32K_IN(PMU)

PMU to T3

T3 XTAL

+1.05VS/+1.2VS/+1.5VS

1.8V

T3 to PMU

1.2V

VDD_CORE(PMU SW1)

PMU to T3

VDD_PMU_LDO7(T3 AVDD_PLLx)

1.8V

PMU to T3

5V

VDD_RTC(PMU LDO4)

VDD_5V0_SBY(PQ9106, 2A)

AC_OK

A/D_IN

PWR_SW#

+3VA_PAL(PU8805)

AC_BAT_SYS

EN_5V0_SBY(PMU GPIO0)

VDD_1V8_PMU_VRTC(PMU VRTC)

PMU_ONKEY#

SW# to PMU

+5VSUS (PU8100)

P_+5VSO_EN_10 (Q7900)

EC to PU8100

1.8V

PMU to T3

VDD_1V8_GEN(PMU SWIO)

1.05V

1.0V

2.85V

1.8V

5.0V

T3 to Q1603

PMU to PU8100

PMU to T3

3.3V

+3VA_EC (PU8806)

(4)

5 5 4 4 3 3 2 2 1 1 D D C C B B A A

Date: Sheet of

Title :

Engineer: D 4 60 Thursday, March 01, 2012

Power on/off map 2.0

ME370T

Richard Lin

Date: Sheet of

Title :

ME370T

Richard Lin

Date: Sheet of

Title :

ME370T

Richard Lin WIFI+BT LCD panel backlight EN_VDD_BL VCC_LED P-MOS SI2305DS EN P-MOS SI2305DS EN <OFF>EN_1V8_CAM VDDIO_CAM <7>VDD_1V8_GEN LDO +3V_PAL TI TPS51125ARGER SW1 <10B>+3VSUS(+3VSO1) SW2 <3>+5VSUS(+5VSO1) EN1 EN2 < 1 0 A > E N _ 3 V 3 _ S Y S AC_BAT_SYS A/D IN Adapter Buck Boost Charger BQ24740 Battery Pack BAT LDO <4>+3VA N-MOS IRFHS8342TRPBF VDDIO_HDMI_CONN_AIO HDMI_VBUS_EN_AIO P-MOS SI2305DS EN *** VDD_5V0_SYS EN <10B>+3VSUS P-MOS SI2305DS EN <11>VCC_TCH <OFF>DOCK_IN P-MOS SI2305DS EN <OFF>+5VSUS_DOCK LDO <2B>+3VA_EC Power Latch <1>PWR_SW# Button <2A>P_+3VA_EN <2A>P_+3VA_EN < 2 C > P _ + 5 V S O _ E N _ 1 0 CAM1_LDO_EN EN AVDD_VCM CAM2_LDO_EN EN AVDD_CAM1 <6>EN_VDD_SOC P-MOS SI2305DS EN <6A>VDD_1V2_SOC T30 BAT <OFF>EN_5V0_SYS ** N-MOS IRFHS8342TRPBF <5A>VDD_5V0_SBY EN <5>EN_5V0_SBY P-MOS SI2305DS EN <10B>+3VSUS EN_3V3_COM WiFi_BT_VCC_3V3 <10B>VDD_PNL(+3VSUS) EN_VDD_PNL VCC_LCD3V3 P-MOS SI2305DS EN LCD panel <10B>+3VSUS EN_VDD_FUSE VDD_FUSE P-MOS SI2305DS EN T30

TF300T T3

power on/off map

AVDD_DSI_CSI(1.2V)

EEPROM time slot duration: 2ms

VPP_FUSE(3.3V) VDDIO_DDR HVDD_PEX VDD_FUSE <9>+1.2V VDDIO_LCD VDD_DDR_RX AVDD_USB VDDIO_GMI VDD_PEX_CTL AVDD_HDMI VDD_RTC VDD_DDR_HS VDD_SATA @ @ VDD_CPU VDD_CORE VDDIO_SDMMC1(3.3V) V5IN VCC1 VCC2 VCC7 VCCIO GPIO5 GPIO4 PWRON HOT_RST PWRDN(power down) CORE_PWR_REQ SYS_RESET_N PWR_INT_N CLK_32K_IN CPU_PWR_REQ <9>CLK_32K_IN <10>EN_3V3_SYS <9>+1.2V <OFF>VDD_PMU_LDO5 <11>VDD_DDR_HS <11>VCORE_eMMC_S(core power) <9>EN_DDR <12>SYS_RESET# <13>CPU_PWR_REQ <OFF> VDDIO_SDMMC1 <5>EN_5V0_SBY <5>VDD_1V8_PMU_VRTC <4>VDD_RTC <7>VDD_1V8_GEN <9>VDD_PMU_LDO7(T3 AVDD_PLLx) <7>VDD_1V8_GEN HOT_RST VDD_CELL_LCL <5>VDD_1V8_PMU_VRTC AP_OVERHEAT# <2D>PMU_ONKEY# <OFF>VDD_5V0_SYS*** VRTC <5A>VDD_5V0_SBY VCC3 VCC4 VCC5 VCC6 LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8 VBACKUP VDDIO GPIO0 SLEEP GPIO7 GPIO2 GPIO6 SW SW1 SW2 SWIO PWR_INT# EN2 EN1 CLK32KOUT NRESPWRON CORE_PWR_REQ PWR_INT# VDD_1V8_GEN <10B>+3VSUS <10B>+3VSUS LDO 2.85V RT9193-2HGU5 LDO 2.85V RT9193-2HGU5 AVDD_PLLx* *** HVDD_PEX(3.3V) <10B>+3VSUS <OFF>VDD_PMU_LDO6 <0FF>VDD_CPU <0FF>VDD_1V2_GEN <OFF>VDD_SD_S <6>EN_VDD_SOC <10>+3VSUS(+3VSO1) Sequence: <1>--><2>--><2A>--><2B>--><2C>--><2D>--> <3>--><4>--><5>--><6>--><6A>--><7>--><8>--> <9>--><10>--><10A>--><10B>--><11>--><12>--><13>

1201

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5 4 3 2 1 D D C C B B A A VPP_KFUSE VDD_FUSE_DISABLE GND_CPU_SENSE VDD_CPU_SENSE_T30 VDD_CPU_SENSE GND_CPU_SENSE_T30 GND_CPU_SENSE_T30 VDD_CPU_SENSE_T30 GND_CORE_SENSE_T30 VDD_CORE_SENSE_T30 GND_CORE_SENSE VDD_CORE_SENSE VDD_CORE_SENSE_T30 GND_CORE_SENSE_T30 VDD_CORE VDD_RTC VDD_CPU VDD_CORE VDD_PMU_LDO4_1V2 VDD_1V0_GEN VDD_1V2_SOC VDD_CPU VDD_RTC VDD_CORE VDD_FUSE +3VSUS_CPU VDD_FUSE VDDIO_UART VDD_RTC VDD_CPU VDD_CORE VDD_CORE VDD_CPU GND_CORE_SENSE 51 VDD_CORE_SENSE 51 GND_CPU_SENSE 51 VDD_CPU_SENSE 51 EN_VDD_FUSE 10

Date: Sheet of

Title :

Engineer:

C 5 60 Saturday, March 24, 2012 ASUSTeK COMPUTER INC. EPAD

T30 Core & Fuse

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 Core & Fuse

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 Core & Fuse

2.0

ME370T

Richard Lin

0620

Unmount

1.2V

1220 add

0.9~1.0V

BOM

需

需需

需

需需

需

需需

需

需 02004-00120000 C.S T30-R-A3 FCBGA-728

Note: Place the 0402 shunts close to Tegra side

1.0~1.2V

0906 NV add

Short Copper

0906 NV add 0720

0622

0720 default disable FUSE function

0.9~1.0V

0614 remove VDD_CPU_SENSE

Short Copper

1.0~1.2V

1.2V

MAX77663 LDO4

MAX77663 SD0(6A)

MAX77663 SD1(3A)

MAX77663 SD0 sense

MAX77663 SD1 sense

C10 4.7U6.3VX5RC2M N/A C10 4.7U6.3VX5RC2M N/A 1 2 R2 300R1F N/A R2 300R1F N/A 1 2 C12 0.1U6.3VX5RC1K N/A C12 0.1U6.3VX5RC1K N/A 1 2 C26 4.7U6.3VX5RC2MN/A C26 4.7U6.3VX5RC2MN/A 1 2 PJP3 SHORT_PIN /@ P05 PJP3 SHORT_PIN /@ P05 1 2 C16 4.7U6.3VX5RC2M N/A C16 4.7U6.3VX5RC2M N/A 1 2 C21 4.7U6.3VX5RC2M/@ C21 4.7U6.3VX5RC2M/@ 1 2 C24 0.1U6.3VX5RC1K N/A C24 0.1U6.3VX5RC1K N/A 1 2 C20 0.1U6.3VX5RC1KN/A C20 0.1U6.3VX5RC1KN/A 1 2 C9 4.7U6.3VX5RC2M N/A C9 4.7U6.3VX5RC2M N/A 1 2 PJP1 SHORT_PIN /@ P05 PJP1 SHORT_PIN /@ P05 1 2 C15 0.1U6.3VX5RC1K N/A C15 0.1U6.3VX5RC1K N/A 1 2 C5 4.7U6.3VX5RC2M N/A C5 4.7U6.3VX5RC2M N/A 1 2 R4 100KR1J N/A R4 100KR1J N/A 1 2 C8 4.7U6.3VX5RC2M N/A C8 4.7U6.3VX5RC2M N/A 1 2 C25 33P25VNPOC1JN/A C25 33P25VNPOC1JN/A 1 2 C11 8P25VNPOC1J N/A C11 8P25VNPOC1J N/A 1 2 C7 4.7U6.3VX5RC2MN/A C7 4.7U6.3VX5RC2MN/A 1 2 C6 0.1U6.3VX5RC1K N/A C6 0.1U6.3VX5RC1K N/A 1 2 R1 0R2J /@ R1 0R2J /@ 1 2 C19 4.7U6.3VX5RC2M N/A C19 4.7U6.3VX5RC2M N/A 1 2 C22 4.7U6.3VX5RC2M N/A C22 4.7U6.3VX5RC2M N/A 1 2 C29 4.7U6.3VX5RC2M /@ C29 4.7U6.3VX5RC2M /@ 1 2 C23 0.1U6.3VX5RC1K /@ C23 0.1U6.3VX5RC1K /@ 1 2 PJP2 SHORT_PIN /@ P05 PJP2 SHORT_PIN /@ P05 1 2 C18 4.7U6.3VX5RC2M N/A C18 4.7U6.3VX5RC2M N/A 1 2 C2 0.1U6.3VX5RC1K N/A C2 0.1U6.3VX5RC1K N/A 1 2 U1 NCT3521UN/A U1 NCT3521UN/A OUT 1 GND 2 EN 3 DIS 4 IN 5 C27 4.7U6.3VX5RC2M N/A C27 4.7U6.3VX5RC2M N/A 1 2 PJP4 SHORT_PIN /@ P05 PJP4 SHORT_PIN /@ P05 1 2 R6 1KR1J /@ R6 1KR1J /@ 1 2 C28 4.7U6.3VX5RC2M N/A C28 4.7U6.3VX5RC2M N/A 1 2 R5 10KR1J N/A R5 10KR1J N/A 1 2 C4 0.1U6.3VX5RC1KN/A C4 0.1U6.3VX5RC1KN/A 1 2 C1 0.1U6.3VX5RC1K N/A C1 0.1U6.3VX5RC1K N/A 1 2 C13 4.7U6.3VX5RC2MN/A C13 4.7U6.3VX5RC2MN/A 1 2 R3 100KR1J /@ R3 100KR1J /@ 1 2 C3 4.7U6.3VX5RC2M N/A C3 4.7U6.3VX5RC2M N/A 1 2 C30 0.1U6.3VX5RC1K N/A C30 0.1U6.3VX5RC1K N/A 1 2 C17 22U6.3VX5RC5M N/A C17 22U6.3VX5RC5M N/A 1 2 (1.0 ~ 1.2V) (3.3V) (3.3V) 1/22 CORE POWER (1.0 ~ 1.2V) (0.9 ~ 1.0V) U2A T30L-R-P-A3 T30 (1.0 ~ 1.2V) (3.3V) (3.3V) 1/22 CORE POWER (1.0 ~ 1.2V) (0.9 ~ 1.0V) U2A T30L-R-P-A3 T30 GND_121 Y8 GND_120 Y5 GND_119 Y29 GND_118 Y26 GND_117 Y23 GND_116 Y2 GND_115 W19 GND_114 W17 GND_113 W15 GND_112 W13 GND_111 W12V18 GND_110 GND_109 V16 GND_108 V14 GND_107 V12 GND_106 U8 GND_105 U5 GND_104 U29 GND_103 U26 GND_102 U23 GND_101 U2 GND_100 U19 GND_099 U13 GND_098 T18 GND_097 T16 GND_096 T15 GND_095 T12 GND_094 R19 GND_093 R16 GND_092 R15 GND_091 R13 GND_090 P8 GND_089 P5 GND_088 P29 GND_087 P26 GND_086 P23 GND_085 P2 GND_084 P18 GND_083 P12 GND_082 N19 GND_081 N17 GND_080 N15 GND_079 N13 GND_078 M18 GND_077 M16 GND_076 M14 GND_075 M12L8 GND_074 GND_073 L5 GND_072 L29 GND_071 L26 GND_070 L23L2 GND_069 GND_068 H8 GND_067 H5 GND_066 H29 GND_065 H26 GND_064 H23 GND_063 H20H2 GND_062 GND_061 H17 GND_060 H14 GND_059 H11 GND_058 E8 GND_057 E5 GND_056 E29 GND_055 E26 GND_054 E23 GND_053 E20 GND_052 E2 GND_051 E17 GND_050 E14 GND_049 E11 GND_048 B8 GND_047 B5 GND_046 B30 GND_045 B29 GND_044 B26 GND_043 B23 GND_042 B20 GND_041 B2 GND_040 B17 GND_039 B14 GND_038 B11 GND_037 B1 GND_036 AK29 GND_035 AK2 GND_034 AJ8 GND_033 AJ5 GND_032 AJ30 GND_031 AJ29 GND_030 AJ26 GND_029 AJ23 GND_028 AJ20AJ2 GND_027 GND_026 AJ17 GND_025 AJ14 GND_024 AJ11 GND_023 AJ1 GND_022 AF8 GND_021 AF5 GND_020 AF29 GND_019 AF26 GND_018 AF23 GND_017 AF20 GND_016 AF2 GND_015 AF17 GND_014 AF14 GND_013 AF11 GND_012 AC8 GND_011 AC5 GND_010 AC29 GND_009 AC26 GND_008 AC23 GND_007 AC20 GND_006 AC2 GND_005 AC17 GND_004 AC14 GND_003 AC11A29 GND_002 GND_001 A2 VPP_KFUSE AA4 VPP_FUSE AB8 GND_CORE_SENSE W22 VDD_CORE_SENSE W23 VGND_CORE_SENSE AA23 VVDD_CPU_SENSE AB16 GND_CPU_SENSE AB15 VDD_CPU_SENSE AB12 VDD_CORE_28 W18 VDD_CORE_27 W16 VDD_CORE_26 W14 VDD_CORE_25 V19 VDD_CORE_24 V17 VDD_CORE_23 V15 VDD_CORE_22 V13 VDD_CORE_21 U18 VDD_CORE_20 T9 VDD_CORE_19 T8 VDD_CORE_18 T19 VDD_CORE_17 T13 VDD_CORE_16 R9 VDD_CORE_15 R8 VDD_CORE_14 R7 VDD_CORE_13 R18 VDD_CORE_12 R12 VDD_CORE_11 P19 VDD_CORE_10 P13 VDD_CORE_09 N7 VDD_CORE_08 N18 VDD_CORE_07 N16 VDD_CORE_06 N14 VDD_CORE_05 N12 VDD_CORE_04 M19 VDD_CORE_03 M17 VDD_CORE_02 M15 VDD_CORE_01 M13 VDD_CPU_22 U17 VDD_CPU_21 U16 VDD_CPU_20 U15 VDD_CPU_19 U14 VDD_CPU_18 T17 VDD_CPU_17 T14 VDD_CPU_16 R17 VDD_CPU_15 R14 VDD_CPU_14 P17 VDD_CPU_13 P16 VDD_CPU_12 P15 VDD_CPU_11 P14 VDD_CPU_10 N9 VDD_CPU_09 N8 VDD_CPU_08 M9 VDD_CPU_07 M8 VDD_CPU_06 M7 VDD_CPU_05 K9 VDD_CPU_04 K8 VDD_CPU_03 J8 VDD_CPU_02 J10 VDD_CPU_01 H10 VDD_RTC_0002 V23 VDD_RTC_0001 V22 C14 22U6.3VX5RC5M N/A C14 22U6.3VX5RC5M N/A 1 2

(6)

5 5 4 4 3 3 2 2 1 1 D D C C B B A A JTAG_TMS PWR_I2C_SCL PWR_I2C_SDA PWR_INT# AVDD_PLLE_no_use PCB_ID5 PCB_ID2 PCB_ID3 THERMD_N THERMD_P TEST_MODE_EN JTAG_TRT_N XTAL_OUT XTAL_OUT_R XTAL_IN CORE_PWR_REQ CLK_32K_OUT CLK_32K_IN PCB_ID3 PCB_ID1 PCB_ID0 PCB_ID2 PCB_ID5 PCB_ID4 CAM2_LDO_EN PCB_ID1 PCB_ID4 1V8_O_LID# PCB_ID0 CAM1_LDO_EN LL_BAT_T30 JTAG_TRT_N JTAG_RTCK JTAG_TDI JTAG_TDO JTAG_TCK JTAG_TRST# SYS_RESET# CPU_PWR_REQ AVDD_PLLU_D AVDD_PLLA_P_C AVDD_PLLA_P_C AVDD_PLLU_D VDDIO_SYS VDD_1V8_GEN_CPU AVDD_OSC AVDD_OSC VDD_1V8_GEN_CPU VDD_1V8_GEN VDD_1V8_GEN_CPU AVDD_OSC AVDD_PLLA_P_C AVDD_PLLU_D VDDIO_SYS VDDIO_SYS VDDIO_SYS VDDIO_SYS VDD_PMU_LDO8_1V2_CPU VDD_PMU_LDO8_1V2 VDDIO_SYS VDD_1V8_GEN_CPU VDD_PMU_LDO8_1V2_CPU VDD_PMU_LDO8_1V2_CPU PWR_I2C_SCL 26,27,49,50 PWR_I2C_SDA 26,27,49,50 SYS_RESET# 20,32,50 PWR_INT# 50 CORE_PWR_REQ 14,50 CPU_PWR_REQ 50 CLK_32K_OUT 40,41,43 CLK_32K_IN 50 VOL_UP_BUTTON 32 VOL_DWN_BUTTON 32 PWR_SW#_BUTTON_R 33 CAM1_LDO_EN 31 KB_ROW0 32,33 CAM2_LDO_EN 31 1V8_O_LID# 25 LL_BAT_T30 33 JTAG_TCK 24 JTAG_TDI 24 JTAG_TMS 24 JTAG_TDO 24 JTAG_RTCK 24 THERMD_N 26 THERMD_P 26 JTAG_TRST# 24 TEMP_ALERT#_KAI 26 SMB347_USB51HC 33 SMB347_SUSP 33 NFC_VEN 44 NFC_GPIO4_R 44

Date: Sheet of

Title :

Engineer:

C 6 60 Thursday, March 22, 2012 ASUSTeK COMPUTER INC. EPAD

01.Block Diagram

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

01.Block Diagram

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

01.Block Diagram

2.0

ME370T

Richard Lin

COL5

COL6

COL7

ROW0

Config.

Reset

Config.

Reset

Config.

Reset

Config.

Reset

Config.

Reset

Unmount

0906 NV change

Config.

Reset

ROW1

Unmount

Config.

Reset

ROW2

Config.

Reset

ROW3

Pin to Pin

Unmount

ROW4

ROW11

ROW5

Unmount

ROW12

ROW6

ROW13

ROW7

ROW14

Config.

Reset

ROW8

1.2V

Config.

Reset

ROW9

1.2V

1.8V

Config.

Reset

ROW10

Config.

Reset

Config.

Reset

Config.

Reset

Config.

Reset

Short Copper

0802 ID5 KB_COL0 KB_COL1

Config.

Reset

KB_COL2 KB_COL3 SNN_KB_COL6 SNN_KB_COL7 SNN_KB_COL4 SNN_KB_COL5

Config.

Reset

Config.

Reset

PD

100K

PD

100K

PD

100K

PD

100K

PD

100K

Config.

Reset

100K

UP

PUPD

UP

DOWN

PinState

DOWN

50K

DOWN

50K

DOWN

50K

DOWN

50K

DOWN

50K

DOWN

100K

DOWN

100K

DOWN

100K

DOWN

50K

DOWN

50K

DOWN

PU

Config.

Reset

PU

PD

Config.

Reset

remove PLL_S_PLL_LF 0721 TXC/7V12000011

Config.

Reset

Config.

Reset

Config.

Reset

1.8V

1.2V

1.05V

PCIE&SATA USB&DSI DRAM CPU AUDIO&PERIPHERAL

1.2V

1.8V

PCBID ID1 ID0 0 0 AW-NH660 BCM4330 1 0 AW-NH665 BCM4330

Unmount

1.8V

NC

1.2V

POR

Deep Sleep

PUPD

After Wake

COL0

SNN_KB_ROW3 KB_ROW2 KB_ROW0 KB_ROW1 CAM2_LDO_EN SNN_CAM1_AF_PWDN* SNN_CAM_I2C_SEL0 SNN_CAM2_AF_PWDN* CAM3_AF_PWDN* SNN_KB_ROW12 SNN_KB_ROW13 SNN_KB_ROW14 SNN_KB_ROW15 CAM1_LDO_EN CAM3_LDO_EN SNN_CAM_I2C_SEL1

1.1V

1.2V

R1.0

R1.2

PMU

VDD_PMU_LDO7 PCBID ID2 = 0 for BCM47511 ID2 = 1 for BCM4751

ROW15

VDDIO_SYS

Unmount

0229 NV change 10k -> 100k 1227 R0732 100K -> 10K PCBID ID5 ID4 ID3

0 0 0 for ME370T SR3

1.8V

Change Change

COL1

COL2

C32 & C33 change to 12pF

COL3

COL4

Change

X1 change to 12MHz XTAL

Remove C35, C36 for AVDD_PLLX & AVDD_PLLM Remove AVDD_PLLX Remove AVDD_PLLM

Unmount

MAX77663 LDO8

MAX77663 SD2 (2A)

Power from MAX77663

MAX77663 LDO8 1.2V to T30 AVDD_PLLx

MAX77663 SD2 1.8V (VDD_1V8_PMU_DCDC2) to VDD_1V8_GEN

Signal to & from MAX77663

SYS_RESET# from MAX77663 nRSTIO, check reset circuit(p.32) and PMU side

VDD_1V8_PMU_DCDC2

PWR_INT# from MAX77663 nIRQ, check PU resister in PMU side(100k PU to VDD_1V8_GEN) CORE_PWR_REQ to MAX77663 EN1, check PU resister in PMU side(100k PU to VDD_1V8_GEN) CPU_PWR_REQ to MAX77663 EN2, check PD resister in PMU side(100k PD)

CLK_32K_IN from MAX77663 GPIO4, check PU resister in PMU side(100k PU to VDD_1V8_GEN)

TEMP_ALERT#_KAI form Thermal Sensor ROW10, 11 for charger control

CPU_PWR_REQ PD

100k in KAI design

R27 100KR1J R27 /@/PCBID/GPS 100KR1J /@/PCBID/GPS 1 2 R28 100KR1J R28 /PCBID/PROJECT 100KR1J /PCBID/PROJECT 1 2 R23 100KR1J R23 /@/PCBID/PROJECT 100KR1J /@/PCBID/PROJECT 1 2 R29 100KR1J R29 /PCBID/PROJECT 100KR1J /PCBID/PROJECT 1 2 R26 0R1J N/A R26 0R1J N/A 1 2 PJ1 SHORT_PIN /@ PJ1 SHORT_PIN /@ 1 2 X1 12MHz N/A X1 12MHz N/A 1 3 2 4 L7 30Ohm/100Mhz N/A L7 30Ohm/100Mhz N/A 2 1 R31 100KR1J R31 /@/PCBID/PROJECT 100KR1J /@/PCBID/PROJECT 1 2 R17 100KR1J R17 /PCBID/WIFI 100KR1J /PCBID/WIFI 1 2 C34 0.1U6.3VX5RC1K N/A C34 0.1U6.3VX5RC1K N/A 1 2 R18 100KR1J R18 /@/PCBID/WIFI 100KR1J /@/PCBID/WIFI 1 2 R16 1KR1J N/A R16 1KR1J N/A 1 2 C38 0.1U6.3VX5RC1K N/A C38 0.1U6.3VX5RC1K N/A 1 2 C33 12P50VNPOC2J N/A C33 12P50VNPOC2J N/A 1 2 R14 100KR1J N/A R14 100KR1J N/A 1 2 R9 2MR2J N/A R9 2MR2J N/A 1 2 C37 0.1U6.3VX5RC1K N/A C37 0.1U6.3VX5RC1K N/A 1 2 R19 100KR1J R19 /PCBID/WIFI 100KR1J /PCBID/WIFI 1 2 R22 100KR1J R22 /PCBID/GPS 100KR1J /PCBID/GPS 1 2 R24 100KR1J N/A R24 100KR1J N/A 1 2 R30 100KR1J R30 /@/PCBID/PROJECT 100KR1J /@/PCBID/PROJECT 1 2 R20 100KR1J R20 /@/PCBID/WIFI 100KR1J /@/PCBID/WIFI 1 2 R15 100KR1J N/A R15 100KR1J N/A 1 2 R10 0R1J N/A R10 0R1J N/A 1 2 R21 0R1J /@ R21 0R1J /@ 1 2 R25 100KR1J R25 /PCBID/PROJECT 100KR1J /PCBID/PROJECT 1 2 C32 12P50VNPOC2J N/A C32 12P50VNPOC2J N/A 1 2 C31 4.7U6.3VX5RC2M N/A C31 4.7U6.3VX5RC2M N/A 1 2 R11 1KR1J N/A R11 1KR1J N/A 1 2 (1.8/3.3V) 2/22 OSC, PLL & SYS

(1.8V) (1.1V) (1.1V) (1.1V) (1.1V) (1.1V) (1.05V) U2B <Value> T30L-R-P-A3 N/A (1.8/3.3V) 2/22 OSC, PLL & SYS

(1.8V) (1.1V) (1.1V) (1.1V) (1.1V) (1.1V) (1.05V) U2B <Value> T30L-R-P-A3 N/A VDDIO_SYS_2 K30 VDDIO_SYS_1 K29 AVDD_PLLE AA22 AVDD_PLLU_D2 AD7 AVDD_PLLU_D AA8 AVDD_PLLM J13 AVDD_PLLX J12 AVDD_PLLA_P_C H13 AVDD_OSC F30 TEST_MODE_EN R28 HDMI_CEC AC18 OWR N22 THERM_DP M29 THERM_DN M30 JTAG_RTCK V24 JTAG_TRST_N T22 JTAG_TMS R23 JTAG_TDO T28 JTAG_TDI R29 JTAG_TCK T27 KB_ROW15 V26 KB_ROW14 M25 KB_ROW13 V28 KB_ROW12 N23 KB_ROW11 M27 KB_ROW10 R25 KB_ROW09 M26 KB_ROW08 R27 KB_ROW07 T25 KB_ROW06 T24 KB_ROW05 N30 KB_ROW04 N24 KB_ROW03 M28 KB_ROW02 V27 KB_ROW01 M23 KB_ROW00 T26 KB_COL07 N29 KB_COL06 P27 KB_COL05 R30 KB_COL04 W26 KB_COL03 R26 KB_COL02 V25 KB_COL01 N26 KB_COL00 J30 CLK_32K_OUT U27 CLK_32K_IN R22 SYS_CLK_REQ T23 CPU_PWR_REQ R24 CORE_PWR_REQ N25 PWR_INT_N M22 SYS_RESET_N N28 PWR_I2C_SDA N27 PWR_I2C_SCL M24 NC37 H12 XTAL_OUT T29 XTAL_IN T30 R12 1KR1J N/A R12 1KR1J N/A 1 2 R8 0R3J N/A R8 0R3J N/A 1 2

(7)

5 4 3 2 1 D D C C B B A A GEN2_I2C_SDA GEN2_I2C_SCL NAND_ALE NAND_CLE NAND_D5 NAND_D6 NAND_D0 NAND_D7 NAND_D1 NAND_D2 NAND_D3 NAND_D4 TS_IRQ# TS_RESET#_3V3 LCD_BL_PWM LCD_BL_PWM NAND_RE# NAND_WE# PCB_ID6 PCB_ID7 PCB_ID8 PCB_ID7 PCB_ID6 PCB_ID8 TS_WAKEUP# FTM_MODE# FTM_MODE# VDD_3V3_GMI +3VSUS_CPU +3VSUS VDD_3V3_GMI VDD_3V3_GMI VDD_3V3_GMI VDD_3V3_GMI +3VSUS_CPU VDD_3V3_GMI VDD_3V3_GMI LCD_BL_PWM 23 TS_IRQ# 29 TS_RESET#_3V3 29 NAND_D0 18 NAND_D1 18 NAND_D2 18 NAND_D3 18 NAND_D4 18 NAND_D5 18 NAND_D6 18 NAND_D7 18 NAND_ALE 18 NAND_RE# 18 NAND_WE# 18 GEN2_I2C_SCL 29 GEN2_I2C_SDA 29 NAND_CLE 18,26 TS_WAKEUP# 29,48

Date: Sheet of

Title :

Engineer:

C 7 60 Wednesday, March 21, 2012 ASUSTeK COMPUTER INC. EPAD

T30 GMI IF

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 GMI IF

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 GMI IF

2.0

ME370T

Richard Lin

AD01

AD02

TS I2C

SNN_GMI_DQS

AD03

AD04

AD05

AD06

AD07

AD08

AD09

AD10

3.3V

NC

Unmount

PCBID ID7 ID6 0 0 ALC5631Q 0 1 WM8903 1 0 ALC5642 1 1 Reserved NC NC

POR

AD00

VDDIO_GMI

OE_N

WR_N

ADV_N

CLK

RST_N

WAIT

WP_N

IORDY

NC

3.3V

MFG_MODE_R

Boot Straps

RECOVERY_MODE* SNN_GMI_RST* EN_VDD_BL1 LCD1_BL_EN LCD1_BL_PWM TS_IRQ* TS_RESET* PWM_3D NC PCBID ID8 Reserved

Unmount

100K

None

100K

PU

1 None

PUPD

1 PinState

DOWN

100K

Config.

Hold

UP

Z

PD

None

Z

None

Z

None

Z

None

Z

None

1

0 None

Config.

Hold

None

Z

None

Z

UP

None

Z

None

Z

0 PU

100K

Config.

None

1 UP

100K

PU

Hold

UP

100K

PU

None

1 None

Z

UP

100K

Config.

Hold

DQS

Disable

Reset

Disable

Reset

Disable

Reset

AD11

Disable

Reset

AD12

Disable

Reset

PUPD

After Wake

Deep Sleep

Disable

Reset

NC

AD13

Disable

Reset

NC

Disable

Reset

AD14

AD15

Disable

Reset

A16

Disable

Reset

Disable

Reset

Disable

Reset

Disable

Reset

Disable

Reset

A17

Disable

Reset

A18

Disable

Reset

A19

Reset

Disable

Reset

Disable

Reset

Disable

Reset

CS0

CS1

SPI4_SCK SPI4_DOUT SPI4_DIN SNN_GMI_CS0 CHARGER_STAT LCD_LANDSCAPE SNN_TP_IRQ# SNN_GMI_CS6 SNN_GMI_CS2 WW_WAKE*

CS2

SPI4_CS1

CS3

NC

3.3V

Config.

CS4

Config.

CS6

Config.

Disable

Reset

Disable

Reset

Disable

Reset

Disable

Reset

Disable

Reset

Disable

Reset

Disable

Reset

Config.

Reset

Config.

CS7

NC

TPS63020 buck-boost

NAND_CLE for AP thermal shut down in KAI NAND_CLE for AP thermal shut down in KAINAND_CLE for AP thermal shut down in KAI NAND_CLE for AP thermal shut down in KAI TS_WAKEUP# for TS 5V enable (PD 1M on page.48) TS_WAKEUP# for TS 5V enable (PD 1M on page.48) TS_WAKEUP# for TS 5V enable (PD 1M on page.48) TS_WAKEUP# for TS 5V enable (PD 1M on page.48)

CARD_PEX_RST#

R44, R45 (GEN2_I2C PU) placed on P.29 R44, R45 (GEN2_I2C PU) placed on P.29 R44, R45 (GEN2_I2C PU) placed on P.29 R44, R45 (GEN2_I2C PU) placed on P.29 R35 0R3J N/A R35 0R3J N/A 1 2 R38 100KR1J R38 /PCBID/CODEC 100KR1J /PCBID/CODEC 1 2 R40 100KR1J R40 /@/PCBID 100KR1J /@/PCBID 1 2 T51 tpc40t_np_68 /@ T51 tpc40t_np_68 /@ 1 R36 100KR1J R36 /PCBID/CODEC 100KR1J /PCBID/CODEC 1 2 R316 1MR1J N/A R316 1MR1J N/A 1 2 R41 100KR1J R41 /PCBID 100KR1J /PCBID 1 2 C40 0.1U6.3VX5RC1K N/A C40 0.1U6.3VX5RC1K N/A 1 2 R43 330KR1J N/A R43 330KR1J N/A 1 2 (1.8/3.3V) 4/22 GMI U2D T30L-R-P-A3 N/A (1.8/3.3V) 4/22 GMI U2D T30L-R-P-A3 N/A VDDIO_GMI_3 D1 VDDIO_GMI_2 C2 VDDIO_GMI_1 C1 GEN2_I2C_SDA G7 GEN2_I2C_SCL G5 GMI_DQS G3 GMI_WR_N G4 GMI_OE_N F2 GMI_IORDY C3 GMI_WP_NGMI_WAIT D5 B4 GMI_RST_N D4 GMI_CLK A4 GMI_ADV_N E6 GMI_CS7_N J7 GMI_CS6_N J5 GMI_CS4_N D6 GMI_CS3_N A3 GMI_CS2_N F6 GMI_CS1_N K7 GMI_CS0_N J4 GMI_A19 J3 GMI_A18 C4 GMI_A17 J6 GMI_A16 H4 GMI_AD15 F1 GMI_AD14 J2 GMI_AD13 F7 GMI_AD12 F5 GMI_AD11 F3 GMI_AD10 E7 GMI_AD09 F4 GMI_AD08 H6 GMI_AD07 G1 GMI_AD06 B3 GMI_AD05 D2 GMI_AD04 G2 GMI_AD03 E4 GMI_AD02 D3 GMI_AD01 G6 GMI_AD00 F8 R39 100KR1J R39 /@/PCBID/CODEC 100KR1J /@/PCBID/CODEC 1 2 R37 100KR1J R37 /@/PCBID/CODEC 100KR1J /@/PCBID/CODEC 1 2 C39 10U6.3VX5RC3M N/A C39 10U6.3VX5RC3M N/A 1 2

(8)

5 5 4 4 3 3 2 2 1 1 D D C C B B A A DDR_RESET_N DDR_COMP_PU DDR_COMP_PD DDR_QUSE1 DDR_QUSE0 DDR_QUSE3 DDR_QUSE2 DDR_CKE0 DDR_CLK_R_C DDR_A10 DDR_A12 DDR_A11 DDR_A13 DDR_A14 DDR_BA0_N DDR_WE_N DDR_BA1_N DDR_CS1_N DDR_CS0_N DDR_ODT0_N DDR_CLKN DDR_BA2_N DDR_RESET_N DDR_CLKP DDR_CAS_N DDR_RAS_N DDR_DQS0N DDR_DQS0P DDR_DQS1N DDR_DQS1P DDR_DQS2N DDR_DQS2P DDR_DQS3N DDR_DQS3P DDR_DQ2 DDR_DQ1 DDR_DQ0 DDR_DQ3 DDR_DQ5 DDR_DQ6 DDR_DQ7 DDR_DQ4 DDR_DQ13 DDR_DQ10 DDR_DQ14 DDR_DQ11 DDR_DQ8 DDR_DQ15 DDR_DQ12 DDR_DQ9 DDR_DQ21 DDR_DQ18 DDR_DQ22 DDR_DQ19 DDR_DQ16 DDR_DQ23 DDR_DQ20 DDR_DQ17 DDR_DQ29 DDR_DQ26 DDR_DQ30 DDR_DQ27 DDR_DQ24 DDR_DQ31 DDR_DQ28 DDR_DQ25 DDR_A5 DDR_A2 DDR_A6 DDR_A3 DDR_A7 DDR_A4 DDR_A0 DDR_A1 DDR_A8 DDR_A9 DDR_DM2 DDR_DM3 DDR_DM0 DDR_DM1 VDD_DDR_RX VDD_DDR_HS VDDIO_DDR VDD_PMU_LDO2_2V8 VDD_PMU_LDO0_1V0 VDDIO_DDR VDD_DDR_RX VDD_DDR_HS VDD_DDR_RX VDD_DDR_HS VDDIO_DDR VDDIO_DDR VDDIO_DDR

+1.35V

VDDIO_DDR DDR_CAS_N 19 DDR_RAS_N 19 DDR_BA0_N 19 DDR_WE_N 19 DDR_BA1_N 19 DDR_BA2_N 19 DDR_ODT0_N 19 DDR_CLKP 19 DDR_CLKN 19 DDR_RESET_N 19 DDR_CS1_N 19 DDR_CS0_N 19 DDR_CKE0 19 DDR_DQ[31..0] 19 DDR_DM[3..0] 19 DDR_DQS0N 19 DDR_DQS0P 19 DDR_DQS1N 19 DDR_DQS1P 19 DDR_DQS2N 19 DDR_DQS2P 19 DDR_DQS3N 19 DDR_DQS3P 19 DDR_A[14..0] 19

Date: Sheet of

Title :

Engineer:

T30 DDR

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 DDR

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 DDR

2.0

ME370T

Richard Lin

No Use 0906 NV change to UM No Use

2.8V

1.0V

from PMIC

0620

1.35V

3.3V

1.0V

0503

Unmount

MAX77663 SD3(2A)

MAX77663 LDO2

from PMIC

MAX77663 LDO0

from PMIC

Unmount

R50 45.3R2F N/A R50 45.3R2F N/A 1 2 C46 10U6.3VX5RC3MN/A C46 10U6.3VX5RC3MN/A 1 2 C51 0.01U10VX7RC1K N/A C51 0.01U10VX7RC1K N/A 1 2 C50 4.7U6.3VX5RC2M N/A C50 4.7U6.3VX5RC2M N/A 1 2 R51 45.3R2F N/A R51 45.3R2F N/A 1 2 C45 4.7U6.3VX5RC2M N/A C45 4.7U6.3VX5RC2M N/A 1 2 C48 10U6.3VX5RC3M N/A C48 10U6.3VX5RC3M N/A 1 2 C64 4.7U6.3VX5RC2M N/A C64 4.7U6.3VX5RC2M N/A 1 2 C47 10U6.3VX5RC3M N/A C47 10U6.3VX5RC3M N/A 1 2 C44 4.7U6.3VX5RC2MN/A C44 4.7U6.3VX5RC2MN/A 1 2 (2.8/3.3V) (1.2/1.25/1.35/1.5) 3/22 DDR3/LPDDR2 (1.00V) U2C T30L-R-P-A3 N/A (2.8/3.3V) (1.2/1.25/1.35/1.5) 3/22 DDR3/LPDDR2 (1.00V) U2C T30L-R-P-A3 N/A VDD_DDR_HS_2 H9 VDD_DDR_HS_1 E10 VDD_DDR_RX A27 VDDIO_DDR_16 K23 VDDIO_DDR_15 K22 VDDIO_DDR_14 J23 VDDIO_DDR_13 J21 VDDIO_DDR_12 J19 VDDIO_DDR_11 J18 VDDIO_DDR_10 J16 VDDIO_DDR_09 J15 VDDIO_DDR_08 H22 VDDIO_DDR_07 H21 VDDIO_DDR_06 H19 VDDIO_DDR_05 H18 VDDIO_DDR_04 H16 VDDIO_DDR_03 H15 VDDIO_DDR_02 G19 VDDIO_DDR_01 G16 DDR_COMP_PD B15 DDR_COMP_PU B21 DDR_QUSE3 F9 DDR_QUSE2 E9 DDR_QUSE1 D26 DDR_QUSE0 D27 DDR_RESET C19 DDR_CLK C18 DDR_CLK_N B18 DDR_CKE1 E18 DDR_CKE0 F19 DDR_ODT1 F18 DDR_ODT0 D16 DDR_CS1_N E19 DDR_CS0_N F16 DDR_BA2 F21 DDR_BA1 E21 DDR_BA0 F15 DDR_WE_N D19 DDR_CAS_N D17 DDR_RAS_N G18 DDR_A14 B16 DDR_A13 A19 DDR_A12 E15 DDR_A11 D18 DDR_A10 E16 DDR_A09 C16 DDR_A08 D15 DDR_A07 A15 DDR_A06 C21 DDR_A05 A16 DDR_A04 B19 DDR_A03 D14 DDR_A02 A18 DDR_A01 G15 DDR_A00 D20 DDR_DQS3P D11 DDR_DQS3N E12 DDR_DQS2P D23 DDR_DQS2N E24 DDR_DQS1P A12 DDR_DQS1N B12 DDR_DQS0P C24 DDR_DQS0N B24 DDR_DM3 G12 DDR_DM2 E22 DDR_DM1 D12 DDR_DM0 C22 DDR_DQ31 F12 DDR_DQ30 D10 DDR_DQ29 F10 DDR_DQ28 G9 DDR_DQ27 D13 DDR_DQ26 G10 DDR_DQ25 G13 DDR_DQ24 F13 DDR_DQ23 F22 DDR_DQ22 F24 DDR_DQ21 E25 DDR_DQ20 G21 DDR_DQ19 F23 DDR_DQ18 D25 DDR_DQ17 D22 DDR_DQ16 G22 DDR_DQ15 C10 DDR_DQ14 B10 DDR_DQ13 A10 DDR_DQ12 C13 DDR_DQ11 B13 DDR_DQ10 C12 DDR_DQ09 A13 DDR_DQ08 C15 DDR_DQ07 B22 DDR_DQ06 A22 DDR_DQ05 A21 DDR_DQ04 A24 DDR_DQ03 D21 DDR_DQ02 A25 DDR_DQ01 B25 DDR_DQ00 D24 C60 4.7U6.3VX5RC2M N/A C60 4.7U6.3VX5RC2M N/A 1 2 C42 4.7U6.3VX5RC2M N/A C42 4.7U6.3VX5RC2M N/A 1 2 C43 0.1U6.3VX5RC1K N/A C43 0.1U6.3VX5RC1K N/A 1 2 C67 4.7U6.3VX5RC2M N/A C67 4.7U6.3VX5RC2M N/A 1 2 C49 4.7U6.3VX5RC2M N/A C49 4.7U6.3VX5RC2M N/A 1 2 R53 40.2R2F N/A R53 40.2R2F N/A 1 2 R48 10KR1J R48 /@ 10KR1J /@ 1 2 R52 0R1J /@ R52 0R1J /@ 1 2 C41 0.1U6.3VX5RC1K N/A C41 0.1U6.3VX5RC1K N/A 1 2 C61 4.7U6.3VX5RC2M N/A C61 4.7U6.3VX5RC2M N/A 1 2 R49 0R1J /@ R49 0R1J /@ 1 2 R54 40.2R2F N/A R54 40.2R2F N/A 1 2

(9)

5 4 3 2 1 D D C C B B A A PWDN_2M DSI_CSI_TEST_OUT CSI_D1BP CSI_D1BN CSI_CLKAP CSI_D1AP CSI_D1AN CSI_D2AP CSI_D2AN CSI_CLKAN DSI_CSI_RUP DSI_CSI_RDN CSI_CLKBP CSI_CLKBN PWDN_5M VI_MCLK CAM_RST_5M CAM_I2C_SCL CAM_I2C_SDA TEMP_ALERT# AVDD_DSI_CSI VDDIO_CAM_T30S VDD_1V8_GEN_CPU VDDIO_CAM_T30S AVDD_DSI_CSI VDD_PMU_LDO7_1V2 AVDD_DSI_CSI VDDIO_CAM_T30S VDD_1V8_GEN VDD_1V8_GEN AVDD_DSI_CSI PWDN_2M 31 CSI_CLKAN 31 CSI_CLKAP 31 CSI_D1AN 31 CSI_D1AP 31 CSI_D2AN 31 CSI_D2AP 31 CSI_D1BN 31 CSI_D1BP 31 CAM_I2C_SCL 25,26,31,44 CAM_I2C_SDA 25,26,31,44 CAM_MCLK 31 TEMP_ALERT#26 CSI_CLKBN 31 CSI_CLKBP 31 CAM_RST_5M 31 PWDN_5M 31

Date: Sheet of

Title :

Engineer:

C 9 60 Tuesday, March 20, 2012 ASUSTeK COMPUTER INC. EPAD

T30 DSI/CSI,CAM

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 DSI/CSI,CAM

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 DSI/CSI,CAM

2.0

ME370T

Richard Lin

NC

T30S pin

AA1 W5 W5 AA3 V4 AC11 AF6 AA9 AP18 AM14 AG33 V8 AM36 X AM16 D36 BB LCD AUDIO BB BB BB BB BB

Deep Sleep

PUPD

After Wake

BB

PUPD

PinState

POR

VDDIO_VI

D00

BB

D01

D02

D03

D04

D05

D06

D07

BB UART UART XX

D08

D09

D10

D11

MCLK

PCLK

HSYNC

VSYNC

0620

Camera 1 (Rear)

Camera 2 (Front)

1.2V

0626

DOWN

PD

15K

0626

DOWN

PD

15K

DOWN

PD

15K

0626

1.8V

DOWN

PD

15K

1.8V

Disable

Hold

Disable

Hold

Disable

Hold

Config.

Hold

Disable

Hold

Disable

Hold

Deep Sleep

PUPD

After Wake

Config.

Hold

PUPD

PinState

POR

Disable

Hold

VDDIO_CAM

Disable

Hold

Disable

Hold

Disable

Hold

Disable

CAM

Hold

CAM

Disable

Hold

Disable

Hold

GPIO

Disable

Hold

Disable

Hold

Disable

Hold

PBB0

PBB3

PBB4

PBB5

PBB6

PBB7

PCC1

PCC2

Unmount

0502

None

Z

None

UP

Z

PU

50K

None

Config.

Hold

Config.

Reset

CAM2_PWDN 12/23 RF add 33P FRONT_SEL

0626

CW/0228 Check SI VI_MCLK VI_PCLK VI_HSYNC VI_VSYNC VI_DO0 VI_DO1 VI_DO2 VI_DO3 VI_DO4 VI_DO5 VI_DO6 VI_DO7 VI_DO8 VI_DO9 VI_DO10 VI_DO11

T30 VI

PRO_RST# HDMI_VBUS_EN_OC# EN_VDDIO_SD EN_VDD_MC BAT_IN_CPU# COMPASS_DRDY ALS_INT#_MB GS_INT LVDS_SHTDN# CAM_RST_2M EN_VDD_PNL DSP_RST# EN_VDD_FUSE EN_HVDD_PEX DSP_PWDN# SDMMC1_WP

T30 GPIO

MAX77663 LDO7

C54 0.1U6.3VX5RC1K N/A C54 0.1U6.3VX5RC1K N/A 1 2 C56 33P25VNPOC1J /@ C56 33P25VNPOC1J /@ 1 2 C55 4.7U6.3VX5RC2M N/A C55 4.7U6.3VX5RC2M N/A 1 2 R59 2.2KR1J N/A R59 2.2KR1J N/A 1 2 C52 0.1U6.3VX5RC1K N/A C52 0.1U6.3VX5RC1K N/A 1 2 (1.2V) 7/22 DSI & CSI

U2H

T30L-R-P-A3 N/A

(1.2V) 7/22 DSI & CSI

U2H T30L-R-P-A3 N/A AVDD_DSI_CSI AB6 DSI_CSI_TEST_OUT AB4 DSI_CSI_RDN AJ3 DSI_CSI_RUP AG4 DSI_D2AP AA3 DSI_D2AN AA2 DSI_D1AP AB3 DSI_D1AN AB2 DSI_CLKAP AB1 DSI_CLKAN AA1 CSI_D2BP AH1 CSI_D2BN AH2 CSI_D1BP AE1 CSI_D1BN AD1 CSI_CLKBP AG2 CSI_CLKBN AG3 CSI_D2AP AE3 CSI_D2AN AE2 CSI_D1AP AD2 CSI_D1AN AD3 CSI_CLKAP AD4 CSI_CLKAN AC4 18/22 CAM (1.8/2.8 ~ 3.3V) U2G T30L-R-P-A3 N/A 18/22 CAM (1.8/2.8 ~ 3.3V) U2G T30L-R-P-A3 N/A VDDIO_CAM AD9 GPIO_PCC2 AG6 GPIO_PCC1 AC6 GPIO_PBB7 AE7 GPIO_PBB6 AE6 GPIO_PBB5 AE5 GPIO_PBB4 AG7 GPIO_PBB3 AD6 GPIO_PBB0 AF6 CAM_MCLK AD5 CAM_I2C_SDACAM_I2C_SCL AH7 AG5 R58 49.9R2F N/A R58 49.9R2F N/A 1 2 R61 33R2J N/A R61 33R2J N/A 1 2 R57 49.9R2F N/A R57 49.9R2F N/A 1 2 C53 4.7U6.3VX5RC2M N/A C53 4.7U6.3VX5RC2M N/A 1 2 R60 2.2KR1J N/A R60 2.2KR1J N/A 1 2 R56 453R2F N/A R56 453R2F N/A 1 2

(10)

5 5 4 4 3 3 2 2 1 1 D D C C B B A A LCD_D5 LCD_D2 LCD_D6 LCD_D3 LCD_D0 LCD_D7 LCD_D4 LCD_D1 LCD_D13 LCD_D10 LCD_D14 LCD_D11 LCD_D8 LCD_D15 LCD_D12 LCD_D9 LCD_D16 LCD_D17 EN_VDD_PNL EN_VDD_FUSE COMPASS_DRDY ALS_INT#_MB LCD_PCLK LCD_DE LCD_HSYNC LCD_VSYNC LVDS_SHTDN# VDD_1V8_GEN_CPU VDDIO_LCD VDDIO_LCD VDDIO_LCD LCD_PCLK 22 LCD_DE 22 LCD_HSYNC 22 LCD_VSYNC 22 LCD_D[17..0] 22 COMPASS_DRDY 26 ALS_INT#_MB 25 EN_VDD_PNL 21,48 EN_VDD_FUSE 5 LVDS_SHTDN# 22

Date: Sheet of

Title :

Engineer:

T30 LCD

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 LCD

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 LCD

2.0

ME370T

Richard Lin

NC NC NC SNN_CRT_HSYNC SNN_CRT_VSYNC NC EN_3V3_FUSE SNN_LCD_PWR2 SDMMC_WP* BAT_DET* COMPASS_DRDY SNN_LCD_SDOUT ALS_IRQ*

0621

SNN_LCD_PWR0 EN_VDD_PNL1 NC

LCD_SDIN

LCD_DC0

LCD_DC1

DOWN

100K

PD

DOWN

100K

PD

DOWN

100K

PD

DOWN

100K

PD

UP

100K

PU

UP

100K

PU

UP

100K

PU

DOWN

100K

DOWN

100K

UP

100K

PU

UP

100K

PU

PD

Disable

Deep Sleep

PUPD

After Wake

Hold

PUPD

PinState

POR

VDDIO_LCD

LCD_M1

LCD_PWR0

LCD_PWR1

LCD_PWR2

LCD_SCK

LCD_CS0_N

LCD_CS1_N

LCD_SDOUT

Disable

Hold

Disable

Hold

0502

Disable

Hold

Disable

Hold

Disable

Hold

NC SNN_LCD_ER#

1.8V

NC

0721

LVDS1_SHTDN* SNN_LCD_DC1 NC

1.8V

8/22 LCD (1.8 ~ 3.3V) U2I T30L-R-P-A3 N/A 8/22 LCD (1.8 ~ 3.3V) U2I T30L-R-P-A3 N/A VDDIO_LCD_2 AC13 VDDIO_LCD_1 AB13 HDMI_INT AG13 DDC_SDADDC_SCL AJ10 AG14 CRT_VSYNC AJ16 CRT_HSYNC AD13 LCD_DC1 AE12 LCD_DC0 AE15 LCD_SDIN AH10 LCD_SDOUT AJ13 LCD_CS1_N AC10 LCD_CS0_N AJ15 LCD_SCK AG15 LCD_PWR2 AH12 LCD_PWR1 AG10 LCD_PWR0 AJ9 LCD_M1 AG12 LCD_D23 AK13 LCD_D22 AE13 LCD_D21 AH9 LCD_D20 AH13 LCD_D19 AE10 LCD_D18 AE9 LCD_D17 AH15 LCD_D16 AF13 LCD_D15 AE18 LCD_D14 AD12 LCD_D13 AC12 LCD_D12 AF9 LCD_D11 AJ12 LCD_D10 AK9 LCD_D09 AD15 LCD_D08 AG8 LCD_D07 AG16 LCD_D06 AK12 LCD_D05 AK10 LCD_D04 AK16 LCD_D03 AK15 LCD_D02 AD10 LCD_D01 AF12 LCD_D00 AE8 LCD_VSYNC AF10 LCD_HSYNCLCD_DE AF16 AG9 LCD_WR_N AH16 LCD_PCLK AG11 C58 0.1U6.3VX5RC1K N/A C58 0.1U6.3VX5RC1K N/A 1 2 C57 0.1U6.3VX5RC1KN/A C57 0.1U6.3VX5RC1KN/A 1 2 C59 0.1U6.3VX5RC1K N/A C59 0.1U6.3VX5RC1K N/A 1 2

(11)

5 4 3 2 1

D D

C C

B B

A A

Date: Sheet of

Title :

Engineer:

T30 HDMI,VGA

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 HDMI,VGA

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 HDMI,VGA

2.0

ME370T

Richard Lin

3.3V

1.8V

0818 NC son't support CEC

CEC

HDMI Conn.

3.3V

1.8V

All HDMI pins & powers leave NC when HDMI is not be used.

All VDAC pins & powers leave NC

9/22 VDAC (2.8V) U2J T30L-R-P-A3 9/22 VDAC (2.8V) U2J T30L-R-P-A3 VDAC_RSET AA6 VDAC_VREF AA5 VDAC_B AA7

VDAC_GVDAC_R AA9 AB7 AVDD_VDAC AK6 10/22 HDMI (3.3V) (1.8V) U2K T30L-R-P-A3 10/22 HDMI (3.3V) (1.8V) U2K T30L-R-P-A3 AVDD_HDMI_PLL AF7 AVDD_HDMI_2 AF4 AVDD_HDMI_1 AE4 HDMI_RSET AH3 HDMI_PROBE AG1 HDMI_TXD2P AJ7 HDMI_TXD2N AK7 HDMI_TXD1P AJ6 HDMI_TXD1N AH6 HDMI_TXD0P AH4 HDMI_TXD0N AJ4 HDMI_TXCP AK4 HDMI_TXCN AK3

(12)

5 5 4 4 3 3 2 2 1 1 D D C C B B A A BT_EN BT_IRQ# BT_WAKEUP GPS_PWRON GEN1_I2C_SDA GEN1_I2C_SCL UART1_TXD UART1_RXD CDC_LDO1_EN WLAN_MAC_WAKEN UART1_TXD UART1_RXD CAM_RST_2M GPS_UART2_TXD GPS_UART2_RXD GPS_UART2_RTS# GPS_UART2_CTS# DAP4_DOUT DAP4_FS DAP4_SCLK DAP4_DIN UART4_TXD BT_UART3_TXD BT_UART3_RXD BT_UART3_RTS# BT_UART3_CTS# AP_ACOK# AP_ONKEY# UART4_TXD UART4_RXD UART4_RXD AP_CHARGING# DOCK_IN# VDDIO_UART VDDIO_BB VDD_1V8_GEN_CPU VDDIO_UART VDD_1V8_GEN_CPU VDDIO_BB VDDIO_UART +3VSUS_CPU +3VSUS_CPU VDDIO_BB VDD_1V8_GEN_CPU CDC_LDO1_EN 27 UART_DEBUG_TXD 24,28 UART_DEBUG_RXD 24,28 WLAN_MAC_WAKEN 41 AP_ACOK# 33 AP_ONKEY# 33 GEN1_I2C_SCL GEN1_I2C_SDA GPS_UART2_TXD43 GPS_UART2_RXD 43 GPS_UART2_RTS# 43 GPS_UART2_CTS# 43 BT_UART3_TXD41 BT_UART3_RXD 41 BT_UART3_RTS#41 BT_UART3_CTS# 41 BT_WAKEUP 40,41 GPS_PWRON 40,43 BT_IRQ# 41 BT_EN 40,41 DAP4_DIN 41 DAP4_DOUT 41 DAP4_FS 41 DAP4_SCLK 41 CAM_RST_2M 31 AP_CHARGING# 33 DOCK_IN# 28

Date: Sheet of

Title :

Engineer:

T30 BB,UART

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 BB,UART

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 BB,UART

2.0

ME370T

Richard Lin

0906 NV change 2.2K -> 4.7K DSP_1V8_EN -> CODEC_1V8_EN BT_IRQ* GPS_RST* MB_DET_DOCK* BT_EN BT_WAKEUP

GPIO

GPS_IRQ# GPS_PWRON Cardhu use 4.7K NC

1.8V

DOCK_IN# -> MAX8903B_CHG#_1V8 EN_VDD_SDMMC1 EN_VDDIO_VID_OC* EN_3V3_MODEN SNN_DAP3_SCLK SNN_ULPI_DATA5 SNN_ULPI_DATA6 SNN_ULPI_DATA7 Note: 'EN_VDD_SDMMC1' reserved for power gating

Debug??

GPIO

DEBUG_GPIO0 DEBUG_GPIO1 DBG_IRQ# WF_WAKEUP ACC_IRQ*

Z

No Use

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

PV0

PV1

UP

100K

UP

100K

UP

100K

UP

100K

UP

100K

UP

100K

UP

100K

PU

Disable

Hold

Config.

Hold

Config.

Hold

None

Z

None

Z

Deep Sleep

PUPD

After Wake

Disable

Config.

Hold

PUPD

PinState

POR

VDDIO_BB

DATA0

UP

PU

100K

Config.

Hold

GPS UART

williams 0602

BT PCM

Unmount

0902

1.8V

CLK3_OUT CLK3_REQ

Unmount

DAP3_DOUT

DAP3_FS

DAP3_SCLK

100K

DOWN 100K

PD

Disable

Deep Sleep

PUPD

After Wake

Disable

Hold

PUPD

PinState

POR

VDDIO_BB

DAP3_DIN

DOWN

1.8V

BT UART

JTAG 不

不

不不

不

不不

不

不不

不

不, 需

需

需需

需

需TX/RX GND

需

SNN_D_AP_ACOK# SNN_D_AP_ONKEY#

GPI : Disable SD card write protection

Debug??

Deep Sleep

PUPD

After Wake

Disable

Hold

PUPD

PinState

POR

VDDIO_UART

PU0

None

Z

None

Z

None

Config.

Hold

NC

PU1

PU2

PU3

PU4

PU5

PU6

None

Z

Disable

1.8V

Disable

NC GEN1_I2C no use

KAI -- ALS, Compass, Gyro, NFC I2C connect to GEN1 I2C Current connect to CAM_I2C

R69 0R1J R69 /@ 0R1J /@ 1 2 R72 0R1J R72 N/A 0R1J N/A 1 2 R70 0R1J R70 /@ 0R1J /@ 1 2 C70 0.1U6.3VX5RC1K N/A C70 0.1U6.3VX5RC1K N/A 1 2 R76 4.7KR1J N/A R76 4.7KR1J N/A 1 2 C71 0.1U6.3VX5RC1K N/A C71 0.1U6.3VX5RC1K N/A 1 2 R73 0R1J R73 N/A 0R1J N/A 1 2 R75 4.7KR1J N/A R75 4.7KR1J N/A 1 2 R74 1MR1J N/A R74 1MR1J N/A 1 2 R71 1MR1J /@ R71 1MR1J /@ 1 2 C69 1U6.3VX5RC2KN/A C69 1U6.3VX5RC2KN/A 1 2 12/22 BB (1.8/3.3V) U2S T30L-R-P-A3 N/A 12/22 BB (1.8/3.3V) U2S T30L-R-P-A3 N/A VDDIO_BB W1 GPIO_PV1 R2 GPIO_PV0 R1 DAP3_SCLK R6 DAP3_FS R4 DAP3_DOUT M3 DAP3_DIN N3 ULPI_STP N4 ULPI_NXTULPI_DIR N2 M4 ULPI_CLK M2 ULPI_DATA7 T2 ULPI_DATA6 T1 ULPI_DATA5 T4 ULPI_DATA4 P4 ULPI_DATA3 T3 ULPI_DATA2 N1 ULPI_DATA1 V1 ULPI_DATA0 R3 14/22 UART (1.8/3.3V) U2R T30L-R-P-A3 N/A 14/22 UART (1.8/3.3V) U2R T30L-R-P-A3 N/A VDDIO_UART AA30 CLK3_REQ W24 CLK3_OUT Y27 DAP4_SCLK AA26 DAP4_FS AA24 DAP4_DOUT W28 DAP4_DIN AA29 GPIO_PU6 AA27 GPIO_PU5 W30 GPIO_PU4 AC25 GPIO_PU3 AB27 GPIO_PU2 AB30 GPIO_PU1 V30 GPIO_PU0 AA28 UART3_CTS_N W29 UART3_RTS_NUART3_RXD AB29 W27

UART3_TXD AC27 UART2_CTS_N AA25 UART2_RTS_NUART2_RXD AB26 AB28

UART2_TXD W25 GEN1_I2C_SDA V29 GEN1_I2C_SCL AB25

(13)

5 4 3 2 1 D D C C B B A A HOOK_DET#_CPU DAP_MCLK1_H GYRO_INT HEAD_DET# DAP2_DOUT DAP2_DIN DAP2_SCLK_H DAP2_FS_H LINOUT_DET CDC_IRQ# HOOK_DET#_CPU VDD_IO_AUDIO VDD_IO_AUDIO VDD_1V8_GEN_CPU VDD_IO_AUDIO DAP_MCLK1 27 DAP2_SCLK 27 DAP2_FS 27 DAP2_DOUT 27 DAP2_DIN 27 GYRO_INT 26 HEAD_DET# 28 NFC_IRQ_R 44 LINOUT_DET 28 CDC_IRQ# 27 HOOK_DET# 28

Date: Sheet of

Title :

Engineer:

T30 AUDIO

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 AUDIO

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 AUDIO

2.0

ME370T

Richard Lin

1.8V

Deep Sleep

PUPD

After Wake

Disable

Config.

Reset

Hold

PUPD

PinState

POR

VDD_IO_AUDIO

SPI2_SCK

SPI2_CS0_N

SPI2_MOSI

SPI2_MISO

Hold

SPI2_CS1_N

Change

SPI2_CS2_N

Unmount

DOWN

100K

DOWN

100K

UP

100K

UP

100K

UP

100K

UP

100K

SNN_MODEM_AUDIO_CLK SNN_MODEM_AUDIO_CS SNN_MODEM_AUDIO_DI SNN_MODEM_AUDIO_DOUT

PU

PD

Disable

Reset

NC NC NC NC

REMOVE FM I2S 0609

HP_DET* GYRO_IRQ* SNN_DIS_5V_SWITCH SNN_SATA_DET*

GPIO

CDC_IRQ* NFC_IRQ* NC

Unmount

1.8V

SNN_SPDIF_IN SNN_SPDIF_OUT

CODEC

Unmount

0229 EMI add

R234 0R1J N/A 0R1J R234 N/A1 2 C76 27P25VNPOC1J /@ C76 27P25VNPOC1J /@ 1 2 C89 27P25VNPOC1J /@ C89 27P25VNPOC1J /@ 1 2 R78 33R1J N/A R78 133R1J 2N/A C72 0.1U6.3VX5RC1K N/A C72 0.1U6.3VX5RC1K N/A 1 2 C73 33P25VNPOC1J N/A C73 33P25VNPOC1J N/A 1 2 R79 33R1J N/A R79 133R1J 2N/A C75 27P25VNPOC1J /@ C75 27P25VNPOC1J /@ 1 2 13/22 AUDIO (1.8/3.3V) U2Q T30L-R-P-A3 N/A 13/22 AUDIO (1.8/3.3V) U2Q T30L-R-P-A3 N/A VDDIO_AUDIO C30 SPI2_MISO D30 SPI2_MOSI B27 SPI2_CS2_N E27 SPI2_CS1_N F25 SPI2_CS0_N G28 SPI2_SCK D29 SPI1_MISO F28 SPI1_MOSI F29 SPI1_CS0_N J24 SPI1_SCK B28 SPDIF_OUT A28 SPDIF_IN H27 DAP2_DIN F27 DAP2_DOUT G27 DAP2_FS C29 DAP2_SCLK C28 DAP1_DIN G25 DAP1_DOUT G26 DAP1_FS D28 DAP1_SCLK G29 CLK1_REQ F26 CLK1_OUT C27 C74 33P25VNPOC1J /@ C74 33P25VNPOC1J /@ 1 2 R77 0R1J 09002-00050000 N/A R77 0R1J 09002-00050000 N/A 1 2

(14)

5 5 4 4 3 3 2 2 1 1 D D C C B B A A USB1_VBUS USB1_DN USB1_DP USB1_ID ACOK_DOCKOK_2 USB_RSET ACOK_DOCKOK_3 AVDD_USB_DISCHARGE EN_AVDD_USB_PLL__SWITCH_1 EN_AVDD_USB_PLL_SWITCH_3 EN_AVDD_USB_PLL__SWITCH_2 USB1_VBUS USB1_VBUS AVDD_USB_PLL AVDD_USB AVDD_USB_PLL AVDD_USB AVDD_USB AVDD_USB USB1_VBUS VDD_USB1_VBUS +3VSUS AVDD_USB VDD_1V8_GEN AVDD_USB_PLL AVDD_USB_PLL_1 USB1_VBUS USB1_DP 28,49 USB1_DN 28,49 EN_AVDD_USB 50 CORE_PWR_REQ 6,50 USB1_ID 28

Date: Sheet of

Title :

Engineer:

T30 USB,HSIC,ICUSB

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 USB,HSIC,ICUSB

2.0

ME370T

Richard Lin

Date: Sheet of

Title :

Engineer:

T30 USB,HSIC,ICUSB

2.0

ME370T

Richard Lin

Unmount

Note:

1. once USB1 is connected and USB1_VBUS is a wake source, our EMC, CPU would run at max frequency and voltage. 2. USB1_VBUS must be powered when force recovery mode.

3. USB1_VBUS is powered with USB_DP/N data transition, SW will recognize that a HOST PC is plugged in.

SNN_USB2_ID SNN_USB2_VUS

3G Module

USB Conn.(OTG)

3.3V

1.8V

0620

SNN_IC_USB_DN SNN_AVDD_IC_USB SNN_IC_USB_REXT HSIC_STROBE HSIC_DATA SNN_IC_USB_DP

Unmount

Dock USB HUB

SNN_USB3_ID SNN_USB3_VUS

3.3V

1.8V

1014 TF201 add 0720

MAX77663 GPIO2

Unmount

T30 AVDD_USB_PLL 1.8V

Vth=1.5V

From T30

TPS63020 buck-boost

USB VBUS

EN_AVDD_USB from MAX77663 GPIO2, check PU resister in PMU side(100k PU to VPH_PWR_CHGR)

Signal from MAX77663

0229 EMI add

Close to CPU

0229 EMI add

Close to CPU

Unmount

SI2305DS 2nd Source

07G005C69010 P-MOSFET EMF44P02J SOT-23

07G005051130 P-MOSFET SI2305DS-T1-E3 SOT-2

07G005051310 P-MOSFET NTR2101PT1G SOT-23

07G00538101L P-MOSFET AP2305GN SOT-23

SI2305DS 2nd Source

07G005C69010 P-MOSFET EMF44P02J SOT-23

07G005051130 P-MOSFET SI2305DS-T1-E3 SOT-2

07G005051310 P-MOSFET NTR2101PT1G SOT-23

07G00538101L P-MOSFET AP2305GN SOT-23

R68 0R2J /@ R68 0R2J /@ 1 2 R83 100KR1J /@ R83 100KR1J /@ 1 2 R84 1KR1F N/A R84 1KR1F N/A 1 2 (1.8V) (3.3V) 11/22 USB U2L T30L-R-P-A3 N/A (1.8V) (3.3V) 11/22 USB U2L T30L-R-P-A3 N/A AVDD_USB_PLL U4 AVDD_USB U12 USB_REXT Y4 ACC3_DETECT V4 USB3_DP V2 USB3_DN V3 USB3_VBUS R5 ACC2_DETECT W4 USB2_DP T5 USB2_DN T6 USB2_VBUS V5 ACC1_DETECT T7 USB1_DP W2 USB1_DN W3 USB1_VBUS W5 16/22 IC_USB (1.8V) U2N T30L-R-P-A3 N/A 16/22 IC_USB (1.8V) U2N T30L-R-P-A3 N/A IC_USB_REXT V8 IC_USB_DP W9 IC_USB_DN W8 AVDD_IC_USB V9 15/22 HSIC (1.2V) U2M T30L-R-P-A3 N/A 15/22 HSIC (1.2V) U2M T30L-R-P-A3 N/A HSIC_REXT W6 HSIC_STROBE V7 HSIC_DATA V6 VDDIO_HSIC W7 C80 0.1U6.3VX5RC1K /@ C80 0.1U6.3VX5RC1K /@ 1 2 C63 100P25VNPOC1J /@ C63 100P25VNPOC1J /@ 1 2 R62 330R1J N/A R62 330R1J N/A 1 2 Q5A UM6K1N N/A Q5A UM6K1N N/A 2 6 1 R80 30Ohm/100Mhz N/A R80 30Ohm/100Mhz N/A 2 1 D S G 1 2 3 Q6 SI2305DS N/A D S G 1 2 3 Q6 SI2305DS N/A 1 2 3 D S G 1 2 3 Q2 SI2305DS N/A D S G 1 2 3 Q2 SI2305DS N/A 1 2 3 C77 4.7U6.3VX5RC2M N/A C77 4.7U6.3VX5RC2M N/A 1 2 Q3A UM6K1N N/A Q3A UM6K1N N/A 2 6 1 R63 100KR1J N/A R63 100KR1J N/A 1 2 C78 0.1U6.3VX5RC1K N/A C78 0.1U6.3VX5RC1K N/A 1 2 R82 100KR1J N/A R82 100KR1J N/A 1 2 R64 10KR1J N/A R64 10KR1J N/A 1 2 C62 0.1U6.3VX5RC1K N/A C62 0.1U6.3VX5RC1K N/A 1 2 U14 NCT3521U N/A U14 NCT3521U N/A OUT 1 GND 2 EN 3 DIS 4 IN 5 R66 330R1J N/A R66 330R1J N/A 1 2 C156 0.1U6.3VX5RC1K /@ C156 0.1U6.3VX5RC1K /@ 1 2 Q3B UM6K1N N/A Q3B UM6K1N N/A 5 3 4 C79 0.1U6.3VX5RC1K N/A C79 0.1U6.3VX5RC1K N/A 1 2 C90 0.1U6.3VX5RC1K /@ C90 0.1U6.3VX5RC1K /@ 1 2 R81 1MR1J N/A R81 1MR1J N/A 1 2 C81 4.7U6.3VX5RC2M N/A C81 4.7U6.3VX5RC2M N/A 1 2