Sequential Circuits. Combinational Circuits Outputs depend on the current inputs

Sequential Circuits

Combinational Circuits

Outputs depend on the current inputs

Sequential Circuits

„ Outputs depend on current and previous inputs „ Requires separating previous, current and future „ Called states or tokens

„ Example: Finite State Machines (FSMs), Pipelines

CL clk in out clk clk clk CL CL Pipeline Finite State Machine

Sequential Circuits

If tokens moved through pipeline at constant speed, no sequencing elements will be needed Ex: Fibre-optic cable, called wave pipelining in circuits

However, dispersion is high in most circuits

We need to delay fast tokens, so that they don't catch up with slow tokens

Use flip-flops to delay fast tokens so that they move through exactly one stage per cycle Inevitably adds some delay to slow tokens

Makes circuit slower than just the logic delay Called sequencing overhead

Sometimes called clocking overhead

But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence

Sequential Elements Latch Level sensitive Transparent latch D latch Flip-Flop Edge triggered Master-slave flip-flop D flip-flop, D register D Flo p La tc h Q c lk c lk D Q clk D Q (latch)

Sequential Elements: Latch

Pass Transistor Latch

Pros:

„ Tiny

„ Low clock loads Cons:

‰ V_t drop

‰ nonrestoring ‰ backdriving

‰ output noise sensitivity ‰ dynamic

D

Q

Sequential Elements: Latch

Transmission Gate Latch

„ No V_t drop

‰ Requires inverted clock

Inverting Buffer

Pros:

„ Restoring

„ No backdriving „ Fixes either:

output noise sensitivity Or diffusion input Cons: ‰ Inverted output D Q φ φ D φ φ X Q D Q φ φ

Sequential Elements: Latch

Tristate feedback

„ Static

‰ Backdriving risk

Static latches are now essential

Buffered Input

„ Fixes diffusion input „Noninverting φ φ φ φ Q D X φ φ Q D X φ φ

Sequential Elements: Latch

Buffered Output

„ Non backdriving

Widely used in standard cells

„ Very robust (important feature) ‰ Rather large

‰ Rather slow (1.5 - 2 FO4 delays) ‰ High clock loading

Datapath Latch „ Smaller, faster ‰ Unbuffered input φ φ Q D X φ φ φ φ φ φ Q D X

Sequential Elements: Flip-Flop

Flip-Flop

Built as a pair of back-to-back latches

D Q φ φ φ φ X D φ φ φ φ X Q Q φ φ φ φ

Sequential Elements

Enable

Ignore clock when enable is inactive Mux: increase latch D-Q delay

Clock-gating: increase enable setup time, skew

D Q Lat c h D Q en φ φ Lat c h D Q φ 0 1 en Lat c h D Q φ en D Q φ 0 1 en D Q φ en Flop Flo p Flop

Sequential Elements

Reset

Force output low when reset is asserted Synchronous vs. asynchronous D φ φ φ φ Q Q φ φ φ φ reset D φ φ φ φ φ Q φ φ D reset φ Q φ φ D reset reset φ φ reset S y nc h ro nou s Re s e t A s y nc h ron ou s Re s e t S y m bol Flop D Q La tc h D Q reset reset φ φ φ Q reset

Sequential Elements

Set / Reset

Set forces output high when asserted Flip-Flop with asynchronous set and reset

D

φ

φ

φ

φ

φ

φ

Q

φ

φ

reset

set

reset

set

Timing Diagrams Flop A Y t_pd Combinational Logic A Y D Q clk clk D Q Lat c h D Q clk clk D Q t_cd t_setup t_hold t_ccq t_pcq t_ccq t_setup t_hold t_pcq t_pdq t_cdq

Latch/Flop Setup Time

t_setup

Latch D-Q Cont. Delay

t_pcq

Latch D-Q Prop Delay

t_pdq

Latch/Flop Clk-Q Cont. Delay

t_ccq

Latch/Flop Clk-Q Prop Delay

t_pcq

Logic Cont. Delay

t_cd

Logic Prop. Delay

t_pd

Latch/Flop Setup Time

t_setup

Latch D-Q Cont. Delay

t_pcq

Latch D-Q Prop Delay

t_pdq

Latch/Flop Clk-Q Cont. Delay

t_ccq

Latch/Flop Clk-Q Prop Delay

t_pcq

Logic Cont. Delay

t_cd

Logic Prop. Delay

t_pd

Contamination propogation delaysand

Sequencing Methods  Flip-Flops  2-Phase latches  Pulsed latches F lip-F lo ps Flop La tc h Flop clk φ₁ φ₂ φ_p clk clk La tc h La tc h φ_p φ_p φ₁ φ₂ φ₁ 2 -P h as e T ran s p are n t La tc h e s P ul s e d L a tc h e s Combinational Logic Combinational Logic Combinational Logic Combinational Logic La tc h La tc h T_c T_c/2 t_nonoverlap t_nonoverlap t_pw Half-Cycle 1 Half-Cycle 1

Max-Delay: Flip-Flops F1 F2 clk clk clk Combinational Logic T_c Q1 D2 Q1 D2 t_pd t_setup t_pcq TC tpcq tpd tsetup= + + tpd TC tsetup tpcq≤ − ( + ) sequencing delay

Max-Delay: 2-Phase Latches T_c Q1 L1 φ₁ φ₂ L2 L3 φ₁ φ₂ φ₁ Combinational Logic 1 Combinational Logic 2 Q2 Q3 D1 D2 D3 Q1 D2 Q2 D3 D1 t_pd1 t_pdq1 t_pd2 t_pdq2 tpd tpd1 tpd2= + ≤ _{Tc 2tpdq}− ( ) Tc tpdq1 tpd1 tpdq2 tpd2≥ + + + sequencing delay

Max-Delay: Pulsed Latches T_c Q1 Q2 D1 D2 Q1 D2 D1 φ_p φ_p φ_p Combinational Logic L1 L2 t_pw (a) t_pw > t_setup Q1 D2 (b) t_pw < t_setup T_c t_pd t_pdq t_pcq t_pd t_setup TC max tpdq tpd tpcq tpd tsetup tpw≥ ( + , + + − ) tpd TC max tpdq tpcq tsetup tpw≤ − ( , + − ) sequencing delay

Min-Delay: Flip-Flops CL clk Q1 D2 F1 clk Q1 F2 clk D2 t_cd t_hold t_ccq tcd thold tccq≥ −

Min-Delay: 2 Phase Latches CL Q1 D2 D2 Q1 φ₁ L1 φ₂ L2 φ₁ φ₂ t_nonoverlap t_cd t t_ccq tcd1 tcd2, ≥ thold tccq tnonoverlap− −

Hold time reduced by nonoverlap

Paradox: Hold applies twice each cycle vs. only once for flops

Min-Delay: Pulsed Latches CL Q1 D2 Q1 D2 φ_p t_pw φ_p L1 φ_p L2 t_cd t_hold t_ccq tcd thold tccq tpw≥ − +

Time Borrowing

In a flip-flop based system

„ Data launches on one rising/falling edge „ Must setup before next rising/falling edge „ If it arrives late, system fails

„ If it arrives early, time is wasted „ Flops have hard edges

In a latch-based system

„ Data can pass through latch when transperent

„ Long cycle of logic can borrow time into the next cycle „ As long as each loop completes in one cycle

Time Borrowing Lat c h Lat c h Lat c h

Combinational Logic Combinational

Logic

Borrowing time across half-cycle boundary

Borrowing time across pipeline stage boundary (a) (b) Lat c h Lat c h

Combinational Logic Combinational_Logic

Loops may borrow time internally but must complete within the cycle φ₁ φ₂ φ₁ φ₁ φ₁ φ₂ φ₂

Time Borrowing Q1 L1 φ₁ φ₂ L2 φ₁ φ₂ Combinational Logic 1 Q2 D1 D2 D2 T_c T_c/2

Nominal Half-Cycle 1 Delay

t_borrow

t_nonoverlap

t_setup

How much borrowing? 2 phased latches: pulsed latches:

tborrow ≤ TC---₂ − (tsetup tnonoverlap+ )

Clock Skew F1 F2 clk clk clk Combinational Logic T_c Q1 D2 Q1 D2 t_skew CL Q1 F1 clk Q1 F2 clk D2 clk t_skew t_setup t_pcq t_pdq t_hold t_ccq

We have assumed zero clock skew

Clock really have uncertainty in arrival time decrease max-delay

increases min-delay

decreases time borrowing

Clock Skew: Flip-flops

tpd TC tpcq tsetup tskew≤ − ( − − )

Clock Skew: Latches Q 1 L1 φ₁ φ₂ L2 L3 φ₁ φ₂ φ₁ C om binational Logic 1 C om binational Logic 2 Q 2 Q 3 D 1 D 2 D 3 2 phased latches

tcd1 tcd2, ≥ thold tccq tnonoverlap tskew− − +

tpd Tc 2tpdq≤ − ( )

tborrow ≤ TC---₂ − (tsetup tnonoverlap tskew+ + )

pulsed latches

tpd TC max tpdq tpcq tsetup tpw≤ − ( , + − + _tskew)

tcd thold tccq tpw tskew≥ − + +