A Global Search Algorithm Combined With SIFT Algorithm For Optimization Of MUX BDD Switching Circuits

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A Global Search Algorithm Combined with SIFT

Algorithm for Optimization of MUX BDD

Switching Circuits

M Balal Siddiqui, M Tariq Beg, S. Naseem Ahmad

Abstract— Binary Decision Diagrams are data structure used in different electronic EDA tools for representing switching functions. MUX based Shared BDD are data structures used in modern electronics CAD tools for modelling of different digital circuits. The size of Binary Decision Diagrams is very sensitive for the variable ordering of input variables used in construction of BDDs. Finding an optimal shape of MUX-BDD based design of switching circuits results in optimization of different design parameters including chip area. Here in this paper we have proposed a global search algorithm combined with SIFT algorithm for optimization of area of MUX-BDD circuits. SIFT algorithm is used as second level of optimization in each generation of global search algorithm. The proposed hybrid approach is implemented for different benchmark circuits available for calculation of number of MUX used in each circuit. The results have been compared with different existing other MUX-BDD optimization design techniques for different benchmark circuits and shows a good improvement.

Index Terms: Binary Decision Diagrams, BDD Ordering, MUX BDD Circuits, Data Structure, EDA Tool, Digital Circuit, Switching Circuits, Boolean Optimization, MUX BDD Circuits.

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IN modern VLSI design, designing a digital circuit requires an effective data structure for VLSI CAD tools. The data structure should be able to handle different circuit level manipulations and should be effective enough to produce an optimized circuit design. MUX based BDDs are data structures used in modern electronics CAD tools for modelling of digital circuits. This design style provides lot of flexibility and ease in manipulation using different VLSI CAD tools. The Binary Decision Diagrams were first proposed by Bryant [1] and was based upon the famous Binary Decision Tree proposed by Lee in 1950s [2] and Shannon‟s expansion method [3]. Bryant first showed the use of Binary Decision Diagram as a data structure for representation of Digital circuits. He proposed different reduction techniques for Lee‟s Binary Decision Tree and termed it Reduced and Ordered Binary Decision Diagram or simply ROBDD. This ROBDD or BDD is a data structure which contains one root node, two terminal nodes labeled as „Zero‟ node for Low and „One‟ node for High. In between the root node and terminal nodes there are many non-terminal nodes or internal nodes [4]. The ordered means that in every path from root node to terminal node the ordering of the input variables is same. Different rules were proposed by Bryant for reduction of Binary Decision Diagrams (BDDs). These rules produced the compact decision diagram which is canonical in nature and for an ordered set of input variable it produces a unique representation of Boolean Circuits. The Binary

Decision Diagrams are popular for various reasons like ease in manipulation, compact representation, ease in verification and testing and can be easily incorporated in different VLSI CAD tools [5], [6], [7], [8], [9]. Mux based design style using Field Programmable Gate Arrays (FPGAs) is proposed by many authors and different optimization techniques has been applied for optimization of different design parameters for switching circuits. An efficient algorithm with Binary Decision Diagram optimization is proposed for FPGA [10]. MUX based BDD design of switching circuits are proposed by many researchers [11], [12], [13]. The use of Binary Decision Diagrams with MUX based design gives different computational flexibilities in designing using Computer Aided Design tools. In this paper we have proposed a population based global search algorithm incorporated with SIFT Algorithm for variable reordering of MUX-BDD circuits. The results have been compared with the different existing other MUX-BDD optimization design techniques for different benchmark circuits and shows good improvement. The organization of this paper is as follows: In Sect. 2, the basics of Binary Decision Diagrams (BDDs), variable ordering and MUX based Design of BDDs are discussed. Section 3 discusses the implementation of proposed method on BDDs. Section 4 discusses experimentation and results. Section 5 covers conclusion and future scope.

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2.1 Binary Decision Diagrams

Binary Decision Diagrams are data structures used to represent different Boolean circuits. It is widely used in different Electronic Design Automation (EDA) tools to represent different Boolean circuits. Binary Decision Diagram

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 M. Balal Siddiqui is currently pursuing Ph.D. in Electronics and

Communication Engineering in Jamia Millia Islamia, New Delhi, India-110025. E-mail: [email protected]

 M. T. Beg is currently professor and head of the department of Electronics

and Communication Engineering, Jamia Millia Islamia, New Delhi, India-110025.

 S. N. Ahmad has recently retired as a professor from department of

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is a directed, acyclic, multi rooted graph which is used as a data structure for representation of different switching functions [14]. In this directed acyclic graph, there is one root node, two terminal nodes and some multiple internal nodes. The high terminal node represents the constant functions „1‟ and the low terminal node represents the constant function „0‟. The root node represents the function „F‟ and each of the internal node represents a sub-function of the original function of „F‟. Each internal node and root node has two output branches, labeled as „zero‟ and „one‟, which points to some other internal node (or terminal nodes). Shannon first proposed the Shannon‟s expansion of Binary Decision Tree [3] and later Bryant proposed different rules to reduce and decompose the Binary decision tree into compact decision diagram [4]. Bryant also restricted the same ordering of input variables in all the paths which starts from root node and ends at either of the terminal nodes. This reduced and ordered binary decision diagram was termed as ROBDD, which represents a Reduced and Ordered Binary Decision Diagram. The three rules proposed by Bryant for reduction from Lee‟s Binary Tree to ROBDD are removal of duplicate leaf (terminal) nodes, removal of duplicate internal non-terminal nodes and removal of redundant nodes. These rules are applied on ordered Binary decision tree and results in Reduced and Ordered Binary Decision Diagrams or ROBDDs, which are simply known as BDDs. Fig. 1 shows construction of a Reduced and Ordered Binary Decision Diagram from Ordered Binary Decision Tree for a Boolean function as shown in (1).

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Here we can observe that all the “Zero” terminal nodes are merged to a single “Zero” terminal node and all the high “One” terminal node are merged to single “One” node. For circuit having high number of input variables, this representation gives very compact decision diagram.

Different variants of Binary Decision Diagrams are also proposed in many published works [15], [16], [17], [18]. This includes ZBDD, which is Zero-suppressed Binary Decision Diagram, in which instead of reduction rule for BDD, where if both the high and low edge of a parent node points to the same child node then the parent node in BDD is removed, but

in ZDDs, if the high edge of the parent node points to the low node (i.e. Constant „0‟ node) then the parent node is removed from the decision diagram [15].

2.2 MUX BDD Switching Circuits

MUX BDD Switching circuits are designed by implementing each node of BDDs by a single 2:1 MUX. Fig. 2 shows a MUX BDD switching circuit for implementation of Binary Decision Diagram of the function F(x1,x2,x3,x4) shown in (1) with ordering of variables as ['x1', 'x2', 'x3', 'x4'].

2.3 Effect of Variable Ordering on BDD MUX Circuits

The ordering of Input variables has very strong effect on the overall size of the Binary Decision Diagram [19]. Fig. 3 shows the BDD of the single function as given in equation (1) with six different variable ordering. We can easily observe that the size of Binary Decision Diagram, which is the total number of nodes, varies with the change in input variable ordering. For big digital circuits, having large number of input variables, the large size, which may arise due to a bad ordering of input variables, causes many problems such as consumption of more chip area, more power dissipation and high evaluation time etc. So, to find an optimum variable ordering which enhances different circuit qualities is desired. Different methods proposed by many researchers tend to find out optimal ordering of input variables. These methods can be broadly classified into two categories: static methods and dynamic methods [20], [21], [22], [23], [24], [25], [26]. In static methods of variable reordering, the variable order is determined first and then Decision Diagram is constructed [20], [21], [22]. Relation between different variables is observed initially and then related variables are kept close together. In this static method once a variable ordering is determined for few variables, then these variables are kept at the same order.

Fig. 1. Construction of ROBDD from Ordered Binary Decision Tree for the function shown in (1) with ordering ['x1', 'x2', 'x4', 'x3'].

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In dynamic methods there are many iterative processes which keeps on updating the positions of different variables using different approaches [23], [24], [25], [26]. In these categories of methods, at the end of each iteration, the positions of some of the variables or all or none may change. Dynamic methods are proved to be more time efficient than static methods. They are also uniformly applicable for all type of circuits. SIFT Algorithm proposed by Ruddel is one of the most efficient dynamic methods [26]. On the other hand, many new global search-based algorithms have been implemented for different engineering problems and are very time efficient. Global search-based algorithm is also suitable for problems having very large solution space as they have measures to explore the different sections of search space and they don‟t lock in local solutions [27].

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A Population based global search algorithms are class of algorithms which have potential of exploring new regions in solution space [27]. They have different measures to explore the different regions of search space and escaping the local optima [28]. In this work a GA based global search algorithm is combined with SIFT Algorithm method of variable reordering [26]. The formulation of solution using GA for any problem requires the efficient encoding chromosomes representing solutions. It also needs a cost function which evaluate the fitness of the solutions in each generation. The effective representation of cost function as well as solution space ensures the good set of final solutions. In our proposed approach the solution is represented by a single chromosome, which is a string of variables kept is some order. In a population of „M‟ chromosomes there are „M‟ different ordering of variables shown by each of the chromosome. This representation of solution by chromosome in a population is shown in Fig. 4. The proposed GA initially starts with set of random solutions known as chromosome in first generation This set of chromosomes evolves in further generations using two operators: known as Mutation and Crossover. Mutation is applied to generate new offspring using previous generation chromosome as parent. For each of the offspring SIFT Algorithm is applied and the fitness of the offspring is evaluated. The SIFT Algorithm is famous variable reordering method which is based on regular swapping of variables in chromosome [26]. The current offspring is updated in the node table if it shows better fitness than previous. The proposed hybrid approach is shown in algorithmic form in Fig. 5 as Algorithm 1. In this way the set of best solutions are keep updating and the process terminates using given termination criteria. The mutation operator is used to explore the global search space. It shows the effectiveness in finding the good variable order.

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‘M’ chromosomes.

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The different operators and fitness function used in the proposed algorithm are as follows.

3.1 Fitness Function

In our proposed work fitness function is defined as the total number of MUX used for construction of Binary Decision Diagram mapped Boolean circuit. Minimum the number of MUX used; more fit the solution is. Fitness function is calculated using BuDDY-2.4, which is a Binary Decision Diagram manipulation tool used for calculating different parameters of Decision Diagram. Based on the fitness functions, new generated chromosomes are updated in size table, depending upon the fitness criteria.

3.2 Size Table

We have used a 2-D array of size “[i+1][M]”, where „i‟ is the Size of the solution (ie. Size of the chromosome) and „M‟ is the total no of solutions in a single generation. the last bit (i+1)th _{is used to}

store the fitness of the chromosome. This is for every solution in a population. Further, as the solutions evolved, the Size Table is updated by the respective good solution and fitness against the solution „M‟.

3.3 SIFT Operator as Crossover Operator

The crossover operator is used in different global search algorithms for generation of new solutions from previous solutions. In our proposed work, we have used the SIFT operator used in SIFT algorithm instead of crossover operator. The SIFT method uses variable swap and generate new chromosomes. The SIFT Algorithm method of variable swap is shown in Fig. 6.

3.4 Mutation Operator

Mutation is use to divers the current local solution space. Mutation ensures that the solution does not stuck in local optima. Here we have used the 4-bit swap operator as mutation operator, which swap the window of two four bits with another randomly chosen window of four bits. This selection of windows is set by randomly generated mutation probability in the interval [0,1].

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The proposed global search-based method is executed on a Unix based Ubuntu platform having 2.2 GHz Core i7 processor with 8-GB of RAM. The proposed global search-based algorithm and hybridization with SIFT algorithm as crossover operation is written in Unix-C language. Different manipulation of Binary Decision Diagram including variable swapping and calculation of number of mux in BDD is done using standard BDD library Buddy-2.4 [29]. LgSynth91, which is a standard benchmark package for different digital benchmark circuit is used for testing of our proposed method. Fig. 7 shows the results for proposed method using bar diagram. The results generated using proposed method is compared with the results generated from other previous methods, i.e. INITIAL MUX COUNT, WIN2 and WIN2ite. INITIAL MUX COUNT method is number of MUX calculated using simple variable ordering while WIN2 is method based on Window of two variable and WIN2ite is iterative method with window of two variables. These BuDDy-2.4 inbuild functions are initialized with a simple randomly generated ordering. The Result shows a very good improvement in number of MUX used for different circuits. As shown in Fig. 7, the improvement for circuit misex1 is 14.89%, 6.38%, 4.26% when compared to the methods INITIAL MUX COUNT, WIN2 and WIN2ite respectively. Similarly, improvement for circuit misex2 is 32.14%, 24.60%, and 12.70%. For circuit misex3c, improvement is 23.81%, 14.27% and 10.57%. For circuit sao2 improvement is 38.96%, 36.91%, 13.76%. For circuit squar5, improvement is 2.63%, 2.63%, 2.63%. For circuit clip, improvement is 61.02%, 44.38% and 8.33%.

Fig. 6. Generation of new solutions using SIFT operator.

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Global search-based Algorithms are extensive search algorithms in which the solution search space is distributed in entire solution space. This algorithm is hybridized with famous SIFT algorithm for variable reordering of Binary Decision Diagrams. These global search algorithms have shown itsl effectiveness in variety of engineering optimization problems. In this work, a global search algorithm is hybridized with SIFT algorithm where SIFT operator is used instead of crossover operator. This hybrid approach has reduced the number of computational cycle and show a compact number of MUX circuit for different benchmark digital functions. For future work this proposed method can be modified with hybridization with different other operators.

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