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Integrity and Integration Issues for Nano -Tube Based Interconnect Systems


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Integrity and Integration Issues for Nano -Tube Based

Interconnect Systems

Tulin Mangir, Ph.D.

Electrical Engineering Department

College of Engineering

CSU- Long Beach

Long Beach Ca, 90840-8303



As we continue miniaturization of circuits into nano-scale, interconnects have been recognized as the limiting factor for next generation of computing structures. To increase the density of integration many approaches have been proposed such as System on Chip (SoC), System in Package (SIP), and Networks on Chip (NoC)- which all must address the interconnect issue address. Current approaches to SoC has its limitations as they introduce multiple system limits as architecture, switching energy, heat removal, clock frequency, chip size leave very limited alternatives in the design space. In the long term, the impact of size effects on interconnect structures must be mitigated. In terms of interconnect structures, activated bonding, air gap, carbon nano-tubes, molecular wires, optical interconnects, and spin-wave buses have been proposed. For long distance interconnect, biometric and communications-based schemes are being investigated.

In this paper, we discuss carbon nano-tube based interconnects and our current understanding of the limitations for interconnects for future computing systems.


Nano-technology, interconnect, nano-tubes, SoC, NoC


As we progress into higher throughput and higher density computing circuits the issues of interconnect dominance of not only yield (defect tolerance) [23,24,33], but also performance (delay, crosstalk), and power to drive interconnects have been recognized as the limiting factor [13,26,27]. This has resulted in many conferences and symposiums where interconnect at different levels is the only topic of discussion. [37]

To increase the density of integration many approaches have been proposed such as System on Chip (SoC), System in Package (SIP), and Networks on Chip (NoC). Current approaches to SoC has its limitations as they introduce multiple system limits as architecture, switching energy, heat removal, clock frequency, chip size leave very limited alternatives in the design space. These all imply that we can not design the circuits and keep shrinking them as we have done during the Moore’s Law years[13]. In the long term, the impact of size effects on interconnect structures must be mitigated and newer structures, groupings, and ways of designing computational circuits and interconnects need to be explored. In terms of interconnect structures, activated bonding, air gap, carbon nano-tubes, molecular wires, optical interconnects, and spin-wave buses have been proposed. For long distance interconnect, biometric and communications-based schemes are being investigated.


In the nano-computing realm we are finding that we need to be clever in exploiting the properties that has received attention in nano-technology projects. Nano-technology is concerned with materials and systems whose structures and components exhibit novel and significantly improved physical, chemical, and biological properties, phenomena, and processes due to their nano-scale size[1-5].The aim is to exploit these properties by gaining control of structures and devices at atomic, molecular, and supramolecular levels and to learn to efficiently manufacture and use these devices. Maintaining the stability of interfaces and the integration of these nano-structures at the micron-length scale and macroscopic scale is another important component of nano-science. In recent years there has been a rapid increase in the pace and breadth of research in the area of nano-technology in the hope that that this academic investment will lead to dramatic changes in the ways that nano-materials, devices, and systems are understood and created [3, 5-8]. On the technological side, there are issues in integrating the newer technologies into existing semiconductor and circuit processing lines. Scaling down current technology has limitations [9-15]. As CMOS technology is scaled into the deep submicron regime, tighter and tighter tolerances are required, but unfortunately a wide range of physical effects are working against this need, giving rise to increasing variability. These sources of randomness in circuit characteristics include systematic variations, chip-to-chip process variations, fundamental lithographic difficulties, parameter shifts that occur over the chip-to-chip lifetime, and random atomistic effects. Particular emphasis need to be placed on threshold voltage variation due to discrete dopant fluctuations, and thin film effects. These do not only affect Si technologies, they also have implications for non-Si based technologies such as nano-tubes [15-21]. For example, in principle, both active devices (transistors) and interconnects can be made out of semi conducting and metallic nano-tubes, respectively. However, finding ways to effectively exploit these properties remains a challenge. This has given more momentum and interest in defect tolerant architectures [33].


There are several research efforts exploring architectures for nano computing. Some of these are grouped in Table 1 [35]. It is clear that to increase the density we need to use multidimensional (3-D) interconnect, as well as a combination of technologies from local computational structures all the way to system level integration. Most of the studies regarding interconnect modeling at the functional scale as well as design approaches to computing architectures are based on calculating the interconnect


requirements based on what is known as the Rent’s Rule. Based on those calculations it is clear that we need different interconnect architectures so the interconnect defects, as well as delay and crosstalk in high density circuits will not result in non-functional devices. Recently, researchers presented several futuristic technologies to solve the interconnect bottleneck in chip design. Activated bonding, air gap, carbon nano-tubes, molecular wires, optical interconnects and spin-wave buses were among the technologies proposed. In addition, for long interconnects biometric and communications-based schemes for chip designs are being investigated [6].

Researchers at the Georgia Institute of Technology have developed a CMOS-compatible approach for fabricating on-chip micro-fluidic cooling channels using a spin-on sacrificial polymer material at the wafer level as a way to deal with the heating effects of high density integration [11]. There are also other efforts on developing silicon-based building blocks for on-chip optical interconnects as another potential solution. An all-silicon, on-chip optical interconnect is a candidate to overcome the electrical inter-connect bottleneck (Figure 1). Along those lines, new approaches to designing waveguides In general, interconnects are designed and manufactured top down technologies. One conceptual interconnect methodology is the so-called "bottom-up" or biometric approach [29]. It is appealing to translate the example of the highly connected central nervous system, which performs chemically-assembled guided growth, and provides a 3D functionally-assembled network. Other interconnects technologies have also been proposed include carbon nano-tubes [14, 23]. Multi-walled carbon nano-tubes could offer low resistance in interconnects vias for next-generation chip designs. that can be integrated into the CMOS process has been demonstrated [38-39].

Researchers at UCLA have pro-posed three technologies for the nanotechnology era:

i) Molecular

wires, ii) resonant tunneling

diodes, iii) and a spin-wave bus.

Molecular wires can be

self-assembled onto an under-lying

structure and have "the potential to

operate at the single-molecule level

(Figure 2).

The use of tunneling structures demonstrates another possible solution to the interconnect problem by constructing homogenous cellular automata-like structures, where all local interconnect ions are achieved via the tunneling between the nearest nanodevices.

Figure 2: “Crossbar" array of nanowires with molecular devices at junctions. Figure 1: LED Manufacture with a CNT.


Optics and Photonics for Interconnects

These studies aim to realize optical micro/nano-network systems by way of O-PCBs and VLSI photonic circuits of generic and application-specific functions that are compact, high-speed, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs, VLSI electronic circuits (VLSI-ICs) and the electrical network systems. O-PCBs, VLSI-PICs and O-MNNs process optical signals through optical wires while the E-PCBs, VLSI-ICs, and electrical networks process electrical signals through electrical wires. The new optical systems consist of 2-dimensional planar arrays of optical wires, circuits, and devices of micro/nano-scale to perform the functions of sensing, storing, transporting, processing, switching, routing, and distributing optical signals on flat modular boards or substrates. The integrated optical components include micro/nano-scale light sources, waveguides, detectors, switches, modulators, sensors, directional couplers, multi-mode interference devices, AWGs, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. Some molecular devices are also considered. [37-39]

Neuromorphic Interconnects

The exponential, Moore's Law, progress of electronics may be continued beyond the 10-nm frontier if the currently dominant CMOS technology is replaced by hybrid CMOL circuits combining a silicon MOSFET stack and a few layers of parallel nanowires connected by self-assembled molecular electronic devices. Such hybrids promise unparalleled performance for advanced information processing, but require special architectures to compensate for specific features of the molecular devices, including low voltage gain and possible high fraction of faulty components. Neuromorphic networks with their defect tolerance seem the most natural way to address these problems. Such circuits may be trained to perform advanced information processing including (at least) effective pattern recognition and classification. Researchers are exploring how to develop a family of distributed crossbar network such as Cross Net [28] architectures that permit the combination of high connectivity neuromorphic circuits with high component density. Preliminary estimates show that this approach may eventually allow us to place a cortex-scale circuit with about 1010 neurons and about 1014 synapses on an approximately 10 x 10 cm2 silicon wafer. Such systems

may provide an average cell-to-cell latency of about 20 ns and, thus, perform information processing and system training (possibly including self-evolution after initial training) at a speed that is approximately six orders of magnitude higher than in its biological prototype and at acceptable power dissipation.

Ultrahigh-Density Nano-wire Circuits

In the case of ultrahigh-density nano-wire circuits, research studies have been made with devices such as demultiplexers. A demultiplexer is an electronic circuit designed to separate two or more combined signals. In [36] a technique is reported on demultiplexer architecture for bridging from the sub micrometer dimensions of lithographic patterning to the nanometer-scale dimensions that can be achieved through nanofabrication methods for the selective addressing of ultrahigh-density nanowire circuits. Order log2(N)

large wires are required to address N nanowires, and the demultiplexer architecture is tolerant of low-precision manufacturing. This concept is experimentally demonstrated on sub micrometer wires and on an array of 150 silicon nanowires patterned at nanowire widths of 13 nanometers and a pitch of 34 nanometers .

Carbon Nano-tubes (CNTs)

Carbon Nano-tubes (CNTs) are new materials with outstanding electrical properties. The high conductivity and exceptional stability of metallic nano-tubes makes them excellent candidates for future


use as interconnects in nano-devices and circuits. A Single Walled Carbon Nanotube (SWCNT) behaving as a one dimension metal has a Fermi velocity of vf = 8x105 m/s which is comparable to regular metals

such as copper with 1.57 x 106 or gold 1.40 x 106. Field Effect Transistors (FETs) using semi conducting

CNTs have operating characteristics that are as good as or better than state-of-the-art silicon devices Field Effect Transistors (FETs) using semiconducting CNTs have operating characteristics that are as good as or better than state-of-the-art silicon devices, and significant improvements should be expected in the near future. However, while CNTs are one of the most promising materials for molecular electronics, many challenges remain before they can become a successful technology.

3. Carbon Nano-tubes (CNTs)

In the case of CNT there still is lack of a method that produces a single type of CNT, and the biggest challenges are the materials issues. In this respect, seeded growth techniques are a possibility and need to be explored. Another possible solution involves the development of efficient separation techniques, and work is pursued in this direction with encouraging initial results. The sensitivity of the electrical properties of CNTs and CNT devices to the nature of the CNT–metal contacts and the ambient environment shows that better understanding and control of these problems is absolutely essential. For CNT device integration, new fabrication techniques that are based on self-assembly of CNTs are highly desirable. While our current interest is in computer electronics, it is likely that the initial applications of CNT devices will be in less integrated systems such as sensors, or in special applications where devices of exceptional miniaturization and performance are needed. Apart from their technological importance, CNTs are ideal model systems for the study and understanding of transport in 1-D systems and for the development of molecular fabrication technologies.

Another problem that must be overcome is the ability to control the length of the nano-tubes. Nano-tubes are typically synthesized with poly-disperse micrometer lengths where they are bound into macroscopic entangled ropes (figure 3).

Many applications, however, will require short undamaged individual nano-tubes 20 – 100 nm in length. The availability of single-walled carbon nano-tube samples of uniform length is essential to many specialized applications. One such application is molecular electronics, in which a nano-tube of precise length and specific band gap will need to be placed in a well-defined location. Specific length nano-tubes are also essential for biological imaging and sensing where shorter nano-tube lengths will be required to penetrate cells and to serve as biological markers. To achieve these short length nano-tubes, cutting strategies have been developed. These processes can be viewed as a two-step process: (i) introduction of sidewall damage; and (ii) consumption or cutting of damaged sites.

We can use laser scissors to study the length variation effects, and regularity of nano-tubes [17]. Room temperature piranha solutions (sulphuric acid/hydrogen peroxide) have recently been shown to cut nano-tubes with minimal carbon loss and little sidewall damage. While these processes yield shorter length SWNTs they often still have significant poly-dispersity. Therefore, bulk-scale length-based separation processes are being explored that will yield monodisperse nano-tube length fractions.

Figure 3: SEM Picture of a sample CNT rope taken at CSULB.


One of the applications that are being developed is to use the carbon nano-tubes as three dimensional interconnects, much like the vias. The uniformity of the carbon tubes becomes even more important as controlling the electronic and mechanical properties still remains the challenge.

Due to their inherently small size (a few nanometers in diameter) and their interesting electronic and mechanical properties, CNTs have found a vast set of applications [16]. Creating large numbers of CNT devices has enabled us to rapidly explore their properties and potential applications in different environments and experimental geometries. A well-established approach employs photolithography and lift-off to define catalyst pads and gold electrodes, with CNT growth using a chemical-vapor deposition method in between these two lithographic steps. This method allows the production of large number (hundreds) of CNT devices with 1-3 nm separation between source and drain contact. The problem is that these device geometries, yields, location and regularity are not well controlled.

Following fabrication, we can use an atomic force microscope (AFM) to manipulate nano-tube devices individually. AFM enables us to push, nick and cut nano-tubes [17] so as to eliminate superfluous tubes and create unusual or artificial nano-tube device geometries (figure 4a & 4b). This manipulation can be monitored readily and easily on the AFM through advanced scanned probe techniques like scanned gate microscopy and electric force microscopy.

Figure 4a: IBM Research Illustration using AFM to manipulate CNT.

It has also been documented [15-18,21] that strain causes shifts and differences in the electrical behavior of CNTs. To study the interplay of electrical and mechanical degrees of freedom, we can suspend CNTs over a trench between sources and drain contacts.

Operating as field effect transistors (FETs), CNTs outperform current silicon MOSFET devices significantly. To this end, CNT FETs have been studied in solution using the electrolyte as a gate [19] and collaborated to integrate thin Zirconium oxide as gate oxide with high dielectric constant in a top gate device geometry. In experiments, CNT FETs exhibited very high carrier mobility and transconductance with sub threshold swings approaching the theoretical limit [20, 11, 13]. However, quality and uniformity of these devices and implications of defects in the thin film areas need to be further studied.

4. Issues with CNT interconnect

The major issue after the right kinds of CNTs are grown is interconnecting them. The tubes need to be placed relative to the lithography pattern features of the substrate in order to create an electronic device.


Even though major advancements have been made for the placement of the tubes, such techniques are far from being optimal for the creation of mass production devices. CNT need to be interconnected with electrodes and gates which really pose a challenge in the creation of the devices. Another problem is that once the SWCNT are placed between the electrodes or gates, they are held by weak van der Waals Forces. One technique being developed to improve the contacts between the SWCNT laid on the substrate, is making the source and the drain electrodes with metals that are compatible with silicon technology such as Ti (titanium) or Co (Cobalt) and then fabricate those in the top of the SWCNT. By thermal annealing of the contacts the Ti electrode will produced TiC, which generate a stronger coupling between the SWCNT and the metal even reducing the contact resistance as much as 30kΩ, increasing the

current in the µA range, and a trans-conductance of gm=0.34µS about 200 times greater than the van der

Waals bonded device [21]. Also, using an AFM tip to mechanically stretch the CNTs while electrically monitoring the device resistance, it has been found that the electrical properties of CNTs are very sensitive to strain [18]. While this relationship makes CNT devices a potential candidate for high sensitivity force sensing, its variability and sensitivity may cause problems in other applications for nanoelectronics where these devices have been proposed as candidates as “vias” between multiple layers in 3-D IC integration [11].


Scaling limitation does not only affect Si technologies, they also have implications for non-Si based technologies such as nano-tubes. For the implementation as future interconnects, CNTs have to fulfill the requirements of high current carrying capability and resistances comparable to or better than copper in vias or tungsten in contact holes. CNTs can withstand current densities exceeding copper by a factor of 1000. However, the integrity of the structures at that current density is being questioned at present. In addition, recently observed self-heating in conducting CNTs is also under investigation as another factor impacting the integrity.

With respect to resistance, CNTs are favorable in high aspect ratio structure like vias, where also the highest current densities are expected. Depending on the diameter, a via can be filled with a single MWCNT, a densely packed array of MWCNTs or densely packed arrays of SWCNTs.

In principle, both active devices (transistors) and interconnects can be made out of semi conducting and metallic nano-tubes, respectively. However, finding ways to effectively exploit these properties remains a challenge. This has given more momentum and interest in defect tolerant architectures [33]. The possibility of fabricating nanometer-scale elements that probably will not satisfy the tolerance and reliability requirements typical of larger-scale systems creates the need for defect-tolerant designs. Systems consisting of molecular-size components are likely to have many imperfections, and a computing system designed on a conventional zero-defect basis would not work. For a conventional integrated circuit, designers describe the chip function, and then they construct the hardware. The general idea behind defect-tolerant architectures is conceptually the opposite: Designers fabricate a generic set of wires and switches, to be configured by setting switches that link them together to obtain the desired functionality. A cornerstone of defect-tolerant systems is redundancy of hardware resources—switches, memory cells, and wires—which implies very high integration density.[23-26,33] Fabrication could potentially be very inexpensive if researchers can actualize a chemical self-assembly and attach global interconnects. However, such a circuit would require a laborious testing process, implying a significant overhead cost. It is important to differentiate between defect-tolerant and fault-tolerant architectures. Fault-tolerant systems are designed to deal with faults and usually require some form of redundancy checking. Both defect-tolerant and fault-tolerant systems have an upper limit to the number of defects or faults they can handle before the correction process dominates the overall calculation efficiency. The numerical limit appears to be 20 to 25 percent bad elements or defective calculations.



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