Advanced video compression using H.264

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459,ISO 9001:2008 Certified Journal, Volume 3, Issue 1, January 2013)

745

Advanced video compression using H.264

Pradeep kumar B.P.1, Dhanushree.M.C.2

1,2

Department of Electronics & Communication Engineering, Akshaya Institute of Technology, Tumkur, Karnataka, India

Abstract- Transmission of a video takes a lot of Bandwidth. This bandwidth constraint becomes important especially in military communication applications, because of which only audio and data are transmitted usually. The transmission of video is not possible because of its large size and availability of constrained bandwidth. That is, if a channel supports transmission of 1.5 Mbps, it is not possible to send a video of 4 Mbps. Thus to transmit video it need to be compressed before it is being transmitted. The newest and advanced video coding technique named H.264 is used for this purpose to achieve greater compression. The main goals of the H.264/AVC standardization has been, enhanced compression performance and provision of a “network-friendly” video representation addressing “conversational” (video telephony) and “non-conversational” (storage, broadcast, or streaming) applications. The project is intended to compress PAL video signals by using H.264 video coding standard and produce compressed output in the form of Ethernet packets.

I

.

I

NTRODUCTION

Video compression is a process of converting digital video in to a format that takes up less capacity when it is stored or transmitted. The predecessors of H.264 or MPEG4 part 10 are MPEG4, MPEG3, MPEG2, and MJPEG. H.264 is a newest video coding technique; it builds on the concepts of earlier standards such as MPEG2 and MPEG-4 Visual and offers the potential for better compression efficiency (i.e. better-quality compressed video) and greater flexibility in compressing, transmitting and storing video.

Compression is necessary to transmit of to store a video because of the bandwidth constrains, lossy compression only can give high com pression ratio. While transmitting care to be taken in such a way that, the trade of between quality and compression should be maintained. This requirement is effectively achieved by H.264.

II. H

ARDWARE

I

MPLEMENTATION

F

UNCTIONALITY

This paper is intended to produce a compressed video in the form of Ethernet packets. The block diagram is as shown in figure(a). An analog video PAL format is the input to the system, the analog video is digitized and is converted to YCbCr format by a video decoder. The video decoder output is the input for the DMSOC(Digital Media System on Chip), which is a media processor which supports H.264 video processing and also other various video codacs. It consists of two video image co processors on which H.264 encoder is implemented. DDR2-SD ram is used to speed up the operation. Nand Flash memory is used for storage purpose. The processor consists of inbuilt ethernet controller which is responsible to produce Ethernet packets. The blocks are explained in next section A,B,C,D and E. H.264 encoder and decoder are discussed in software implementation section.

III. B

LOCK

D

ESCRIPTION

A. CAMERA

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International Journal of Emerging Technology and Advanced Engineering

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Figure 1. Block diagram

B. VIDEO DECODER

The video decoder used is used to convert analog composite video from camera to component video. It accepts PAL/NTSC video formats (composite video formats) and converts to YUV 4:2:2 (component video format) digital 8-bit video.

C. DMSOC (TMS320DM365)

This is a high performance, 32-bit, ARM9 based processor which supports a range of video encode and decode operations such as H.264, MPEG4, MPEG2, MJPEG, JPEG and WMV9/VC1. These codecs are driven from video accelerators offloading compression needs from the ARM core so that developers can utilize the most performance from the ARM for their application. Video surveillance designers achieve greater compression efficiency providing more storage without straining the network bandwidth. The DM365 also offers a high level of integration with HD display support including, 3 built-in 10-bit HD Analog Video Digital to Analog Converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, Host Port Interface (HPI), Analog to Digital Converter, and many more features saving developers on overall system costs as well as real estate on their circuit boards allowing for a slimmer, sleeker design.

The processor receives 8-bit digital YUV 4:2:2 composite video format as input. It consists of two video image co-processors on which H.264 compression technique is implemented. The output video format is converted into Ethernet packets by Ethernet MAC controller present in DM365 device.

D. DDR2-SDRAM

The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n -prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one clock- cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.

E. NAND FLASH MEMORY

Nand flash memory is mainly used for storage purpose. It is a non-volatile storage chip that can be electrically erased and reprogrammed. It is programmed to read in page based options and erased in block based options.

IV.

S

OFTWARE

I

MPLEMENTATION

A. H.264 ENCODER

[image:2.612.50.284.148.320.2]

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International Journal of Emerging Technology and Advanced Engineering

[image:3.612.81.537.200.433.2]

747 however, the prediction for each macroblock may be formed from one or two past or future frames (in time order) that have already been encoded and reconstructed.

Figure 2 H.264 encoder

The prediction P is subtracted from the current macroblock to produce a residual or difference macroblock Dn. This is transformed (using a block transform) and quantized to give X, a set of quantized transform coefficients. These coefficients are re-ordered and entropy encoded. The entropy-encoded coefficients, together with side information required to decode the macroblock (such as the macroblock prediction mode, quantizer step size, motion vector information describing how the macroblock was motion compensated, etc) form the compressed bitstream. This is passed to a Network Abstraction Layer (NAL) for transmission or storage.

B. H.264 DECODER

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International Journal of Emerging Technology and Advanced Engineering

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If

Figure3. Decoder(reconstruction path)

If this is not the case, then predictions P in encoder and decoder will not be identical, leading to an increasing error or “drift” between the encoder and decoder.

V. RESULTS

[image:4.612.75.530.171.329.2]

The following snapshots wil show the results of H.264 video compression. Using H.264 more than 50% compression is achieved.

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International Journal of Emerging Technology and Advanced Engineering

[image:5.595.76.253.133.318.2]

749 Figure 5. Snapshot of decoded video bitrates

[image:5.595.83.245.355.496.2]

Figure 6. Snapshot of decoded video

Figure 7. Snapshot of decoded video resolution

VII. CONCLUSION

H.264 provides mechanisms for coding video that are optimized for compression efficiency and aim to meet the needs of practical multimedia communication applications. Using H.264 video coding technique it is possible to achieve bit rate saving of around 50% against other any other standard for the same perceptual quality.

VIII.FUTURE WORK

The encoded video has transmitted and received at the other end and decoded successfully and the movement can be detected. In future, this motion can be detected automatically and whenever the motion is detected, the design can be modified to send a command signal to the control room.

REFERENCES

[1] Thomas Wiegand, Gary J. Sullivan ,Ajay Luthra ,“Overview of the H.264/AVC Video Coding Standard”, IEEE transactions on circuits and systems for video technology, vol. 13, no. 7, july 2003.

[2] Iain E. G. Richardson, Vcodex white paper on “A Technical Introduction to H.264 / AVC”, Vcodex Ltd 2002-2011.

[3] Iain E. G. Richardson, Vcodex white paper on “H.264 / AVC Intra Prediction” Vcodex Ltd 2002-2011.

[4] Hung-wei cheng , a thesis on “Mode decision of H.264/AVC Motion Estimation with RDO”, National Cheng Kung University, july 2005 [5] Iain E. G. Richardson, Vcodex white paper on

“H.264 / AVC Inter Prediction” Vcodex Ltd 2002-2011.

[6]. Iain E. G. Richardson, Vcodex white paper on “H.264 / AVC Transform and Quantization” Vcodex Ltd 2002-2011.

[7]. Iain E. G. Richardson, Vcodex white paper on “H.264 / AVC CABAC entropy coding”, Vcodex Ltd 2002-2011.