Low Power and Area Efficient Design of 1-Bit CMOS Comparator Using Different Foundry

Low Power and Area Efficient Design of 1-Bit CMOS Comparator Using Different Foundry

Pranay Kumar Rahi

¹

, Shashi Dewangan

²

, Sanjay Mirania

³

and Md Muzaherul Haque

⁴

1,3,4

ME Scholar,

²

Assistant Professor, Department of Electronics & Communication Engineering

4

Department of Electrical Engineering, National Institute of Technical Teachers’ Training & Research, Chandigarh, UT, India

2

Department of Physics

Kamala Nehru College, Korba, Chhattisgarh, India [email protected]

ABSTRACT

Comparator is one of the basic functions used for sorting in Microprocessor and Digital Signal Processing (DSP), so a high performance and effective comparator is required.Comparator is one of the fundamental building blocks in most analog to digital converters. The main objective of this paper is to provide new low power and area solution for Very Large Scale Integration (VLSI) designers

.

The comparative analysis performed in terms of the silicon surface area and the power consumption in the designed circuit using different CMOS foundries such as 90nm, 70nm and 50nm.In this paper, both the surface are and power consumption are significantly reduced. The analysis has been presented for different CMOS technologies and finally a proposed designed has been given where surface area has been reduced 13.8µm² and power dissipation has been reduced to 516 µw. The design and simulation are performed of 1-bit Comparator using DSCH and MICROWIND tools.

Keywords: CMOS, VLSI, Comparator, Power consumption, CMOS technology.

1. INTRODUCTION

The comparator is a circuit that compares one analog signal with another analog signal or a reference voltage and outputs a binary signal based on the comparison. Comparator is the

“Heart” of the Analog to digital converter. The comparator is basically a 1-bit analog-to-digital converter[3]. In general, a comparator is a device, which compares two currents or voltages and produces the digital output based on the comparison. Many applications, such as analog to digital converters (ADCs), memory sensing circuits and recently also on chip transceivers are widely using comparators. In the last years, most of the researches focus on the comparator with low power consumption, simple thermal management and high efficiency. The growth of the portable electronic devices makes the power consumption is critical issue to circuit designers because the low power and high speed comparators are the main building block in the front end of the radio

frequency receiver in the most of the modern telecommunications system [1].The comparator is basically 1- bit analog-to digital convertor [2]. In digital system the comparator is a very useful and basic arithmetic component. A compact, good cost benefit, high-performance ratio comparator plays an important role in almost all hardware sorters. One of the most important problems in computer science is sorting. Many fundamental processes in communication and computing systems require data sorting.

Sorting network play a key role in the areas of parallel computing, multiprocessing and multi-access memories [4].

Converter architectures that incorporate a large number of comparators in parallel to obtain a high throughput rate impose stringent constraints on the delay, resolution, power dissipation, input voltage range, input impedance, and area of those circuits. Moreover, the relatively large device mismatch

and limited voltage range that accompany the integration of comparator circuits in low-voltage scaled VLSI technologies [5].

Fig. 1 shows general block diagram and Fig. 2 shows symbol of comparator.

Fig 1: Block diagram of a Comparator

Fig 2: Symbol of a Comparator

2. 1-Bit COMPARATOR

A comparator is a hardware electronic device that takes two numbers as input in binary form and determines whether one number is greater than, less than or equal to the other number [4]. Magnitude comparator is basically a combinational circuit that compares two numbers, X and Y and determines their relative magnitude i.e., X=Y, X. Here we want comparison between two variables and producing an output when any of the above three conditions are achieved. There are different approaches to design CMOS comparator, each with different speed, power consumption and area. The following study gives an overview of the basic 1-bit comparator performance in designing with different techniques in terms of power consumption and area using CMOS technology. First of all we have to design a 1-bit comparator. X and Y are two inputs and three outputs X and only one of the three outputs would be high accordingly if X is greater than or equal to or less than Y. The truth table and the logic diagram for the 1-bit comparator is shown in fig.3 [2].

Table1- Truth Table of 1-Bit Comparator

INPUT OUTPUT

X Y X>Y X=Y X<Y

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0

Three outputs are provided: “X greater than Y” (X>Y), “X less than Y” (X<Y) and “X equal to Y” (X=Y) [4].

3. LAYOUT SIMULATION

In this section, the functional and post-layout simulation results of 1-bit comparator have been presented. There are two parts of result. First, functional simulation of comparator is using CMOS technology in different foundry. Then, post- layout simulation of comparator is done in Microwind 3.1 using 90nm, 70nm and 50nm CMOS technology. Figure 5 is the schematic logic design built on DSCH and layout design in figure 6 on Microwind 3.1.

Fig. 4 DSCH schematic design of 1-bit Comparator

The designs are implemented using Microwind tool version 3.1. This paper aims the design to reduce the overall surface area and power consumption such that the design becomes better applicable for the low power applications. To continue with this, the design is first modified by creating the semi custom layout of design with pre-defined transistors layout on Microwind platform.

Fig. 5MICROWIND Layout design of 1-bit Comparator

4. RESULTS

In this section, the functional and post-layout simulation results of comparator have been presented. The proposed 1-bit Comparators are compared based on the performance parameters viz surface area and power dissipation. The circuits are designed using CMOS process by Microwind 3.1 in 90nm, 70nm and 50nm technology to achieve better performance.

Proposed circuit was designed optimally for speed, power, accuracy and surface area.

The proposed 1-bit Comparator circuit shown in figure 4, uses one 2-bit X-OR, two 2-bit AND and two NOT logic gates.

The timing diagram results of proposed 1bit comparator using 90nm,70nm and 50nm CMOS fabrication technology shown in Figure 6-8.

Fig. 6 : Output of 1-bit Comparator using 90 nm CMOS Technology

Fig. 7: Output of 1-bit Comparator using 70 nm CMOS Technology

Fig. 8: Output of 1-bit Comparator using 50 nm CMOS Technology

The comparative results for proposed 1-bit Comparator for 90nm, 70nm and 50 nm CMOS design technology are given in Table-2.

Table 2. Power and surface area analysis of 1-bit Comparator in different CMOS technologies

CMOS Technology

Parameters

90 nm 70 nm 50 nm

Power

(in µW) 4.956 2.108 0.516

Surface Area

(in µm²) 55.2 27.0 13.8

Fig.9: Graphical Comparison of Power and Area

5. CONCLUSION

In this paper, a comparator circuit is proposed. It describes three different designs for CMOS 1-bit comparator and their simulation. Low power architecture for a 1-bit CMOS comparator is presented using 50nm technology. The proposed comparator design can achieve very low power dissipation and efficient surface area compared with 70nm and 90nm foundry.

This method can reduce power consumption as well as uses smaller silicon surface area. In high density and high- performance VLSI design, a great deal of effort has been made to explore low-power and area design options without sacrificing performance. The power dissipated by the circuit in 90nm, 70nm and 50nm CMOS technologies are 4.956 µW, 2.108 µW and 0.516 µW respectively. The surface area required for the comparator circuit in 90nm,70nm and 50nm CMOS technologies are 55.2 µm², 27.0 µm², and 13.8µm² respectively.

REFERENCES

[1] Raja Mohd. Noor Hafizi Raja Daud, Mamun Bin Ibne Reaz, and Labonnah Farzana Rahman , “Design and Analysis of Low Power and High Speed Dynamic Latch Comparator in 0.18 μm CMOS Process”, International Journal of Information and Electronics Engineering (IJIEE) , Volume-2, Number-6, pp. 944-947, Nov- 2012.

[2] Mehmood ul Hassan, Rajesh Mehra, “Design Analysis of 1-bit CMOS comparator”, International Journal of Scientific Research Engineering & Technology

[3] Dharmendra B. Mavani, Arun B. Nandurbarkar, “ Study and Implementation of Comparator in CMOS 50 NM Technology” International Journal of Research in Engineering and Technology(IJRET), ) ISSN: 2321- 7308, Volume-3,Issue-2, pp. 252-255, Feb- 2014.

[4] Geetanjali Sharma, Uma Nirmal, Yogesh Misra, “ A Low Power 8-bit Magnitude Comparator with Small Transistor Count using Hybrid PTL/CMOS Logic”, International Journal of Computational Engineering &

Management (IJCEM) ISSN: 2230-7893, Volume-2, pp. 110-115,April 2011.

[5] Behzad Razavi, Member, IEEE, and Bruce A. Wooley, Fellow, IEEE, “Design Techniques for High-Speed, High-Resolution Comparators”, IEEE Journals of Solid- State Circuits ,Volume 27, Number-12, pp. 1916-1926, DEC-1999 .

AUTHORS

Pranay Kumar Rahi received the Bachelors of Technology degree in Electronics and Telecommunication Engi- neering from Government Engineering College, Guru Gasidas University, Bilaspur, Chhattisgarh, India in 2004, and pursuing Masters of Engineering in Electronics and Communication Engineering from National Institute of Technical Teacher’s Training & Research, Punjab University, Chandigarh, India. His current research and teaching interests are in Signal and Communications Processing, Communication System. He has authored more than 8 research publications.

Shashi Dewangan received the Bachelors of Science degree from Agrasen Girls College, Korba, Chhattisgarh, India in 2007 and the Masters of Science degree in Physics from Government Science College, Guru Ghasidas University, Bilaspur, India in 2010.

She is an Assistant Professor in the Department of Physics, Kamala Nehru College, Korba, India. She has authored more than 4 research publications.

Sanjay Mirania received the Bachelors of Technology degree in Electronics and Telecommunication Engineering from Raipur Institute of Technology, Ravishankar University, Raipur, Chhattisgarh, India in 2003, and pursuing Masters of Engineering in Electronics and Communication Engineering from National Institute of Technical Teacher’s Training & Research, Punjab University, Chandigarh, India. His current research and teaching interests are in Signal and Communications Processing, Analog Electronics.

Md. Muzaherul Haque received the Bachelors of Technology degree in Electrical Engineering from Government Engineering College, Guru Gasidas University, Bilaspur, Chhattisgarh, India in 2007, and pursuing Masters of Engineering in Instrumentation and Control Engineering from National Institute of Technical Teacher’s Training &

Research, Punjab University, Chandigarh, India. His current research and teaching interests are in Control and Power system.