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A Reliable Adder Circuit with Voter Element for Fault Detection and Correction using Reversible Gates

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Figure

Fig 2. Reversible logic gates
Fig 4. Reversible Voter Gate
Fig. 7 Fault Free Output (CF1, CF2,SF1, SF2 = 0)
Fig. 10 Fault in carry ckt of 3rd module   (SF1, SF2=0 & CF2= 1& CF1 = 1)

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