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High voltage nanosecond pulse switching circuit based on avalanche transistor

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Figure

Figure 1: Schem atic diagram o f high voltage avalanche transistor trigger circuit.
Figure 2: The schem atic diagram o f experim ental setup
Figure 4: Typical result o f nanosecond pulse sw itching in high voltage regim e.
Figure 5: Experim ental sw itching signals for various o f voltages (a) 3.42 kV , (b) 3.12 kV, (c) 2.84 kV (d) 2.56 kV , (e) 2.24 kV and (f) 1.86 kV with a rise tim e o f 93.96 ^is.

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