A COMPARISON OF L25 GRA AND L25 TAGUCHI STATISTICAL
METHOD FOR OPTIMIZING 16 NM DG-FINFET ON OUTPUT
VARIATION
Ameer F. Roslan
1, F. Salehuddin
1, A. S. M. Zain
1, K. E. Kaharudin
1and I. Ahmad
21
Micro and Nanoelectronics Research Group, Centre for Telecommunication Research and Innovation (CeTRI), Universiti Teknikal Malaysia Melaka (UTeM), Durian Tunggal, Melaka, Malaysia
2Centre for Micro and Nano Engineering (CeMNE), College of Engineering, Universiti Tenaga Nasional (UNITEN),
Kajang, Selangor, Malaysia E-Mail: [email protected]
ABSTRACT
The repercussions of a 16 nm double-gate FinFET (DG-FinFET) design against two different optimization methods are investigated and examined. The drive current (ION) and leakage current (IOFF) ramifications towards the
adjustment of six process parameter that incorporates polysilicon doping dose, polysilicon doping tilt, Source/Drain doping dose, Source/Drain doping tilt, VTH doping dose and VTH doping tilt for both L25 Orthogonal Array (OA) Grey Relational
Analysis (GRA) as well as an L25 OA of Taguchi Statistical Method (TSM). However, with TSM, a consideration of noise
factor in gate oxidation temperature and polysilicon oxidation temperature is included. The utilization of ATLAS and ATHENA modules enables respective design simulation as well as characterizations of device’s electrical attributes to be performed. Subsequent to the initial responses from the design simulation, implementation of both TSM and GRA have been implemented separately to assist in process parameter optimization in view to optimize the output responses. The factor percentage of Signal-to-noise ratio determined the process parameter’s effectivity. The most prominent factor is similar for both TSM and TSM-based GRA for which is the polysilicon doping tilt, whereby for L25 OA TSM, the ION and
IOFF obtained after the optimization are 1559.97 μA/μmand 33.03 pA/μm that brings the ION/IOFF ratio to 47.23 106 as
opposed to more insignificant 32.49 106 on pre-optimized simulation. Meanwhile small increment of ratio at 48.01 x 106 from respective values of 1656.27μA/μm and 34.49 pA/μm for the TSM-based GRA proves that both optimization techniques have met the predictions of International Technology Roadmap for Semiconductors (ITRS) 2013.
Keywords: DG-FinFET, grey relational analysis, taguchi statistical method, and optimization.
INTRODUCTION
The application of electronic devices has been widely cohesive in terms of consumerism and with the evolution of smart electrical appliances, would mean that the implementation of CMOS technology has become a necessity in order to perform the required tasks with an instance to the Google Home smart speaker that uses a 28 nm dual-core ARM Cortex-A7 Marvell chip. This shows changes in CMOS technology demand compared to conventional electrical appliances in the past 100 years. The prime example of a CMOS component being the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with numerous types of MOSFETs available due to numerous researches made throughout years [1-7]. The Silicon-on-insulator, Trigate and Fin-shaped field effect Transistor (FinFET) are amongst the numbers of multi-gate FET (MuGFET) used in order to fulfill the requirement as well as demand in producing much smaller devices with great performance through scaling validation process while conformed to the observation made in Moore’s Law [8]. The scaling for tinier chips has been highly doable due to cost-reduced technology, faster in speed as well as smaller in physical attributes.
Nevertheless, increment in process parameter variation against the fabrication of wafer has caused disadvantage in the transistor downscaling. That said, challenges might be prevailed in overcoming the downscaling disadvantage as well as other concerns for
instance, the short channel effect (SCE), threshold voltage (VTH) roll-off as well as drain induced barrier leakage
(DIBL). The performance of the transistor can be heightened as the downscaling process is proceeded by opting for FinFET as it allows the SCEs issues to be bettered with while also reducing the leakage current and subthreshold swing (SS) [9-10].
The comprehension of process variation as well as its manufacturing modeling are imperative in enabling the device characteristics prediction with the fabrication processes performances to permits enough information towards the minimization impacts to the parameters as well as maximizing the yield in performance [11-12]. In this Double-gate FinFET (DG-FinFET) design, reduction has been made to the depth of the silicon depletion as the gate oxide thickness has been considered based of the gate length. Additionally, with the influence of the parameter variation pertinent towards the VTH value, the parameters
of process variation can be controlled to optimize both the off-state leakage current (IOFF) and SS performances.
Outlining the electrical characterization from the process parameters has proven to be perplexing [13]. In order to enhance the robustness of the transistor designs, numerous statistical methods have been tested to further optimize different types of designs particularly for Polysilicon/Silicon Dioxide (PolySi/SiO2)-based
studies while it is less conventional in terms of its application in optimizing CMOS devices [20-21]. In this work, the verification of the implementation of GRA towards the 16 nm DG-FinFET design has been made with a comparative study against Taguchi method that is applied to the same device. The setup allows the order of grey relationship to be ranked based on the magnitude of significance for each factor. While Taguchi statistical method (TSM) is widely used in micro and nano-electronics optimization, the number of experiments required is higher for TSM as opposed to GRA due to consideration of noise factor. In this case, two levels of noise factor with two process parameters applied in the factor which are deliberated in L25 OA of Taguchi. These
bring the total of experiment runs to 100 as opposed to 25 experiments for the L25 TSM-based GRA. However, the
higher number of experiments with high number of combinations have allowed better setting combination to be achieved. Despite that, the TSM-based GRA enables all the output responses to be achieved simultaneously whereby TSM requires each ION, IOFF, SS and VTH to be
run separately and thus requires more time for these results to be acquired, in addition to more experiments required [22].
PROCESS AND DEVICE SIMULATION OF 16NM DG-FINFET
The simulation of 16 nm DG-FinFET device have been realized by commissioning both ATHENA and ATLAS modules from Silvaco International for each of modules allows physical construction and also electrical properties to be extracted for analysis to be done prior to the actual fabrication. This technique permits more cost effective construction to be realized due to possibilities in small alterations to be made multiple times for every parameter until a desired design with a desired output responses are achieved. Five geometrical properties are chosen as its propensity in triggering effects on output responses as small variations in amendment is done as shown in Table 1. Since the process parameters are fluctuated against local parameter variations for which, studies had proved to be 30% from overall, for which ultimately initiating variation [15].
Table-1. Value of the geometrical parameters set.
Parameters Value (nm)
Gate Length, LG 16
SiO2 Thickness, TOX 3.25
Main substrate (silicon) length, LC 35
Polysilicon Length, LDM 17.3
Silicon Thickness, TFIN 18.7
The physical construction of the device begins with a P-type main substrate that act as oxide layer with silicon bulk with <100> orientated as this functions as mask following the implantation of P-well. An infusion of
1x1017 atom/cm3 of Boron is then allowed into the silicon substrate prior to the dry oxygen applied to the gate oxygen for 875oC to a Hydrochloric acid (HCl) of 3%. VTH value meanwhile has been managed by 1.95x1013
atom/cm3 dose of Boron that is implemented with 5keV of energy. The changes with dosage have been done in small amount as this is due to the significance in changes can occurred across the gate concentration despite small modifications being made. The parameter variations are chosen based on the most significant variations acquired with small modifications being made. The adaptation of Polysilicon meanwhile followed the deposition of polycrystalline silicon as the multi-layered structure is formed.
Following to the implantation of indium that is doped at 1.17x1013 atom/cm3 with 1 keV of energy, the sidewall spacer is constructed on the surface of silicon and polysilicon by a layer of Silicon Nitride (Si3N4). With the
sidewall spacer constructed, the SCEs in return are minimized after an n-type S/D areas doped to the sides of the p-type substrate. The minimizations of the side capacitance have been due to the compensate implantation, along with the implantation of 22x1018 atom/cm3 of Arsenic for the implantation towards the S/D. The device fabrication is finalized with the metallization process. Aluminum was deposited and later patterned from the contact window’s initial formation within the S/D region. The device’s structure is later mirrored prior to the electrode definition to complete the fabrication process as shown in Figure-1.
Figure-1. Simulated structure of the PolySi/SiO2-based
DG-FinFET.
DESIGN OF EXPERIMENT WITH L25
ORTHOGONAL ARRAY OF TAGUCHI METHOD The implementation of Taguchi method in this study is done due to its capability in considering noise factor as the best setting combination are dependent to the value of signal-to-noise ratio in order to obtain the desired output responses towards ION, IOFF and SS. The L25
parameter and its levels as well as the table of responses for the L25 OA is presented in Table-2 and Table-3
respectively.
Table-2. Process parameter and its levels for PolySi/SiO2Based DG-FinFET.
Symbol Process Level Level 1 Level 2 Level 3 Level 4 Level 5
A VTH Doping Dose (atom/cm-3) 4.465E+13 4.485E+13 4.505E+13 4.525E+13 4.545E+13
B VTH Doping Tilt (o) 5 7 9 11 13
C Polysilicon Doping Dose (atom/cm-3) 3.58E+14 3.60E+14 3.62E+14 3.64E+14 3.66E+14 D Polysilicon Doping Tilt (o) -22 -20 -18 -16 -14 E S/D Doping Dose (atom/cm-3) 1.20E+18 1.22E+18 1.24E+18 1.26E+18 1.28E+18
F S/D Doping Tilt (o) 72 74 76 78 80
Table-3. L25 Orthogonal Array with signal-to-noise ratio by Taguchi method PolySi/SiO2Based DG-FinFET.
Exp. No Parameter Level Signal-to-noise ratio
A B C D E F ION IOFF
1 1 1 1 1 1 1 63.8 -30.91
2 1 2 2 2 2 2 64.63 -35.94
3 1 3 3 3 3 3 64.98 -39.54
4 1 4 4 4 4 4 65.26 -43.1
5 1 5 5 5 5 5 51.45 -50.78
6 2 1 2 3 4 5 64.92 -38.24
7 2 2 3 4 5 1 65.2 -41.68
8 2 3 4 5 1 2 65.69 -49.2
9 2 4 5 1 2 3 63.81 -30.76
10 2 5 1 2 3 4 64.62 -35.86
11 3 1 3 5 2 4 65.63 -47.89
12 3 2 4 1 3 5 63.75 -29.37
13 3 3 5 2 4 1 64.56 -34.41
14 3 4 1 3 5 2 64.91 -37.94
15 3 5 2 4 1 3 65.19 -41.6
16 4 1 4 2 5 3 64.5 -33.14
17 4 2 5 3 1 4 64.85 -36.65
18 4 3 1 4 2 5 65.13 -40.04
19 4 4 2 5 3 1 65.62 -47.57
20 4 5 3 1 4 2 63.73 -29.29
21 5 1 5 4 3 2 65.08 -38.87
22 5 2 1 5 4 3 66.63 -46.16
23 5 3 2 1 5 4 63.66 -27.79
24 5 4 3 2 1 5 64.49 -32.85
GREY RELATIONAL ANALYSIS AS STATISTICAL METHOD OPTIMIZATION
The Grey relational analysis (GRA) method comprises three main steps consisting the data pre-processing, locating the grey relational coefficient and data normalization. The original data (x) firstly is represented as reference (x0) and comparative series (x1)
followed by data normalization. In this paper, the drive current (ION) and leakage current (IOFF) have been chosen
as the output responses to the corresponding six parameters in threshold voltage (VTH) doping dose, VTH
doping tilt, polysilicon doping dose, polysilicon doping tilt, Source and drain (S/D) doping dose and S/D doping tilt. A maximized value for ION and minimized value for
IOFF and SS are objectively aimed as these subsequently
produces a better ION/IOFF ratio for more efficient power
consumption. Therefore, the ION is characterized as
higher-the-better in data normalization as in equation (1) [23-24]:
) ( min ) ( max ) ( min ) ( ) (
* 0 0
0 0 k x k x k x k x k x i i i i
(1)
In contrary to that, lower-the-better is used for obtaining the smaller values in IOFF with following
expression [25-27] ) ( min ) ( max ) ( ) ( max ) (
* 0 0
0 0 k x k x k x k x k x i i i i
(2)
Where m represents the number of experimental data items and n as the parameter numbers. The largest and smallest value for the
x
i0(
k
)
are represented by therespective max
x
i0(
k
)
and minx
i0(
k
)
. Hypothetically, thegrey relational grade (GRG) is greater for the higher-the-better does equates to that of robust affiliation for both comparative and reference series. With reference (x*0(k)) and comparability sequence ( *( )
k
xi ) both have its deviation sequences (0i), and that the
) ( ) ( * 0 * ,
0j x k xi k
, the grey relational coefficient (GRC) can be defined by
)
(
min
)
(
max
)
(
0min max 0k
x
k
x
k
x
i i i
(3)That said, the identification coefficient is symbolized as
where the] 1 , 0 [
is adjustable to distinguish the normalized values in between reference and comparative series. Since
0.5 is proven to be more stable as well as capable in contributing towards restrained distinguishing effect, with the addition of eachvalues of 0 and 1 replacing both respective min and max, the GRC location can also be obtained with following equation
5
.
0
)
(
5
.
0
)
1
(
)
(
)
1
(
0
)
(
0 , 0 0 ,0
k
k
k
x
j j i
(4)The reason to this is due to that mathematical evidence only the magnitude of relational coefficient will output differences with the altercation made on
, whereby the grey relational grade (GRG) rank will not be affected by the modification of
. In conjunction to the identification coefficient, the GRG can be acquired by calculating the GRC average subsequent to the derivation of GRC. The distribution of the GRG in between reference and comparative series that is between 0 and 1 has allowed the acquisition of GRG as in equation (5)
n k i i k n k1 ( )
1 )
(
(5)
The implementation of GRA is furthered by predicting the GRG via the optimal level based from the optimal level with number of process parameter defined as q
qi i m
m
1
(
)
ˆ
(6)RESULT AND DISCUSSIONS
Based from the L25 OA of Taguchi method
acquired the implementation of equation (1) and (2) for the ION and also IOFF for larger-the-best (LTB) and
smaller-the-best (STB) is done after all of the responses is normalized as in Table-4, with the deviation sequences. The employment of equation (3) has been made later for the conversion of GRC before these GRC values were averaged for each ION and IOFF to achieve the GRG and
ranked as in Table-5. The highest ranked in GRG order denotes the quality towards the multi-response characteristics where the experiment row no. 5 and 23 both equalled in its GRG rank. However, the higher value of ION is prioritized due to the reason that the IOFF achieved
for both have far exceeded the prediction made by the ITRS 2013 for the year 2015. The other orthogonal array characteristic is benefited by splitting the levels of GRG. This allows GRG to be averaged for the allocated factors based on the array that is row 1 to 5 for level 1, given that the average of GRG for VTH doping dose for factor A is to
Table-4. Normalized Responses, Deviation Sequence with GRC and GRG along with its level for L25 GRA.
Exp. No
Normalized Response Deviation Sequences GRC
GRG Rank
ION IOFF 0i(1), ION 0i(2), IOFF ION
i(1) IOFF
i(2)1 0.06638 0.96789 0.93362 0.03211 0.34877 0.93965 0.64421 13
2 0.36951 0.89091 0.63049 0.10909 0.44229 0.82089 0.63159 18
3 0.53173 0.79931 0.46827 0.20069 0.51639 0.71358 0.61499 23
4 0.68469 0.65611 0.31531 0.34389 0.61327 0.59249 0.60288 25
5 1 0 0 1 1.00000 0.33333 0.66667 1
6 0.50322 0.83647 0.49678 0.16353 0.50162 0.75355 0.62758 21
7 0.65392 0.71683 0.34608 0.28317 0.59096 0.63843 0.61470 24
8 0.96370 0.17179 0.03630 0.82821 0.93231 0.37645 0.65438 7
9 0.06708 0.97025 0.93292 0.02975 0.34894 0.94384 0.64639 10
10 0.36565 0.89328 0.63435 0.10672 0.44078 0.82410 0.63244 17
11 0.93265 0.29456 0.06735 0.70544 0.88128 0.41479 0.64803 8
12 0.03755 0.98523 0.96245 0.01477 0.34189 0.97131 0.65660 6
13 0.33762 0.92030 0.66238 0.07970 0.43015 0.86251 0.64633 11
14 0.49526 0.84524 0.50474 0.15476 0.49764 0.76364 0.63064 19
15 0.65038 0.72208 0.34962 0.27792 0.58850 0.64274 0.61562 22
16 0.30926 0.94079 0.69074 0.05921 0.41991 0.89412 0.65701 5
17 0.46916 0.87576 0.53084 0.12424 0.48504 0.80097 0.64301 15
18 0.61627 0.77784 0.38373 0.22216 0.56578 0.69237 0.62908 20
19 0.92401 0.32456 0.07599 0.67544 0.86806 0.42537 0.64672 9
20 0.03264 0.98633 0.96736 0.01367 0.34075 0.97338 0.65706 4
21 0.59219 0.81371 0.40781 0.18629 0.55078 0.72855 0.63966 16
22 0.89081 0.43300 0.10919 0.56700 0.82077 0.46860 0.64469 12
23 0.00000 1.00000 1.00000 0.00000 0.33333 1.00000 0.66667 2
24 0.30139 0.94559 0.69861 0.05441 0.41715 0.90185 0.65950 3
25 0.46602 0.87855 0.53398 0.12145 0.48357 0.80457 0.64407 14
Table-5. Process parameter and GRG levels for PolySi/SiO2Based DG-FinFET.
Symbol Process Level Grey Relational Grade
Level 1 Level 2 Level 3 Level 4 Level 5
A VTH Doping Dose (atom/cm-3) 0.632066 0.635097 0.639445 0.646576 0.650917
B VTH Doping Tilt (o) 0.643301 0.638115 0.642287 0.637225 0.643172
C Polysilicon Doping Dose (atom/cm-3) 0.636211 0.637635 0.638857 0.642987 0.648412 D Polysilicon Doping Tilt (o) 0.654186 0.645375 0.632057 0.620387 0.652096 E S/D Doping Dose (atom/cm-3) 0.643343 0.639831 0.638082 0.635709 0.647136 F S/D Doping Tilt (o) 0.639205 0.642667 0.635738 0.638606 0.647885
Based from the GRG performed by each level, the optimum values can be interpreted for every level of process parameters through a factor effect graph plotted in Figure-2. The plot represents the combination for best
Figure-2. Factor effect plot of GRGs for Multiple response of PolySi/SiO2Based DG-FinFET.
The analysis of variance is then carried out subsequent to the combination succeeded from the factor effect plot to examine the significance of process parameters on GRG. The calculation of sum of squares (SSQ), degree of freedom (DF), mean square (MS),
F-value as well as the percentage contribution (ρ) to the
effectiveness of every process parameter, with mean square is the variance of the GRG, have all been examined to obtain the analysis of variance (ANOVA) as in Table-7.
Table-6. Optimal Level of Process Parameters of PolySi/SiO2Based DG-FinFET.
Symbol Process Parameter Units Level Optimal Value
A VTH Doping Dose atom/cm-3 A1 4.465x1013
B VTH Doping Tilt degree B5 13
C Polysilicon Doping Dose atom/cm-3 C1 3.58x10 14
D Polysilicon Doping Tilt degree D1 -22
E S/D Doping Dose atom/cm-3 E2 1.22x1018
F S/D Doping Tilt degree F3 76
The largest GRG value obtained denotes that the multiple responses are nearer to the anticipated values. By comparing the ION from the pre-optimized and the
post-optimized results, it is observed that the ION is better
before the optimization, by 7.34% and 1.62% against both respective Taguchi statistical method (TSM) and TSM-based GRA, while both scores lesser ION while still
achieving higher reading than the prediction from ITRS 2013. The IOFF however shows that the values achieved
after the optimization decreases significantly by 35.03%
and 32.14% against the value achieved before the result is optimized. While the prediction of obtaining less than 100
nA/μm for the IOFF have all been favorably achieved, the
high percentage of decrement after the optimization shows significant impact towards the ION/IOFF ratio afterwards.
48.0113x106 is acquired for the ION/IOFF ratio after the
responses are optimized via L25 TSM-based GRA for
which is the highest ratio by 31.02% amongst the other experiment runs, with L25 OA TSM achieving slightly less
Table-7. Comparisons of L25 Taguchi method, the L25 Taguchi-based GRA, and Pre-Optimized Results with
Improvements in GRG Output Responses on Optimum Level Process Parameter.
Output Response
Before Optimization
After Optimization
ITRS 2013 prediction for year 2015 [28] L25 Taguchi
L25 Taguchi- based GRA Combination
level A1B1C1D1E1F1 A1B1C2D1E2F2 A5B1C5D1E5F5 N/A
ION(μA/ μm) 1683.51 1559.96 1656.27 ≥1480
IOFF(pA/ μm) 50.84 33.03 34.49 ≤100000
ION/ IOFF Ratio 33.12 x 106 47.23 x 106 48.01 x 106 ≥14.8x103
SS (mV/dec) 96.27 96.93 96.74 N/A
GRG 0.64421061 N/A 0.6877355 N/A
Improvement in GRG = 6.328%
CONCLUSIONS
The L25 orthogonal array (OA) of Taguchi
Statistical Method (TSM) based Grey Relational Analysis has been implemented towards a 16nm PolySi/SiO2Based
DG-FinFET in simultaneous condition involving both ION
and IOFF for the respective larger-the-best (LTB) and
smaller-the-best (STB). The Polysilicon Doping Tilt for which is factor D is proven to be significant towards the variability of the output responses with staggering 70.12% factor effect based from the GRG tabulation. Subsequent to that, the impact is secondarily affected the ION/IOFF ratio,
with the highest ratio acquired at 48.01x106 from the TSM-based GRA method. Despite the reduction in ION,
both optimized responses have managed to achieve higher ION characteristic than the prediction in that of ITRS 2013.
That being said, with insignificant drop of ION of 7.34%
and 1.62% for each TSM and TSM-based GRA does not majorly affecting the ratio of ION/IOFF. As a matter of fact,
the increment in the ratio is due to a significant decrement of 35.03% and 32.14% for which ultimately reduces the power consumption of the 16 nm DG-FinFET device with better ION/IOFF ratio achieved. The results have proved that
the L25 OA Taguchi method and L25 Taguchi-based GRA
are capable in optimizing the responses, with the L25
Taguchi-based GRA able to simultaneously achieving the optimization for multiple responses with both ION and IOFF
characteristics within the range predicted by the ITRS 2013 for the year 2015.
ACKNOWLEDGEMENT
The authors would like to thank the Ministry of Higher Education (MOHE) for sponsoring this work under project (FRGS/1/2017/TK04/FKEKK-CeTRI/F00335) and MiNE, CeTRI, Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM) for laboratory facilities and financial assistance throughout the project.
REFERENCES
[1] Beale M. H., Hagan M. T. and Dewuth H. B. 2006. Fundamentals of machine and machine tools. 2nd Ed. Marcel Dekker Inc. New York, USA. pp. 160-168.
[2] R. Guduri, A. V. Rajulu and A. S. Luyt. 2008. Effect of alkali treatment on the flexural properties of hildegardia fabric. Journal of Applied Polymer Science. 10(2): 127-134.
[3] Caldas L. G. and Norford L. K. 1994. Screws, motors and wrenches that cannot be bought in a hardware store. In: Robotics Research: The First International Symposium. M. Brady and R. Paul (Eds.). pp. 679-693.
[4] Zeng K., Sasaki K., Kuramata A., Masui T. & Singisetti U. 2016. Depletion and enhancement mode
fl-Ga2O3 MOSFETs with ALD SiO2 gate and near 400 V breakdown voltage. In: 2016 74th Annual Device Research Conference (DRC).
[5] Ma J. and Matioli E. 2017. High Performance Tri-Gate GaN Power MOSHEMTs on Silicon Substrate. IEEE Electron Device Letters 38(3), 367-370 (2017).
[6] Li X., Jiang J., Huang A. Q., Guo S., Deng X., Zhang B. and She X. 2017. A SiC Power MOSFET Loss Model Suitable for High-Frequency Applications. IEEE Transactions on Industrial Electronics. 64(10): 8268-8276.
[8] Luc Q. H., Yang K. S., Lin J. W., Chang C. C., Do H. B., Huynh S. H. and Chang E. Y. 2018. In0.53Ga0.47As FinFET and GAA-FET with Remote-Plasma Treatment. IEEE Electron Device Letters. 39(3): 339-342.
[9] Xu Y., Sun H., Shin E. Y., Lin Y. F., Li W. and Noh Y.Y. 2016. Planar-Processed Polymer Transistors. Advanced Materials. 28(38): 8531-8537.
[10]Ahmed M. Dinar, Mohd Zain A. S. and Salehuddin F. 2018. Utilizing of CMOS ISFET sensors in DNA applications detection: A systematic review, Jour of Adv Research in Dynamical & Control Systems. 10(4): 569-583.
[11]Mallik A., Ryckaert J., Mercha A., Verkest D., Ronse K. and Thean A. 2015. Maintaining Moore’s law: enabling cost-friendly dimensional scaling. In: Proc. SPIE 9422, Extreme Ultraviolet (EUV) Lithography VI, 94221N.
[12]Nagy D., Indalecio G., Garcia-Loureiro A. J., Elmessary M.A., Kalna K. and Seoane N. 2018. FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability. IEEE Journal of the Electron Devices Society. 6, 332-340.
[13]Gill A., Madhu C. and Kaur P. 2015. Investigation of short channel effects in Bulk MOSFET and SOI FinFET at 20nm node technology. In: 2015 Annual IEEE India Conference (INDICON).
[14]Saxena S., Member S., Hess C., Karbasi H., Rossoni A., Tonello S., Mcnamara P., Lucherini S., Minehane S., Dolainski C. and Quarantelli M. 2008. Variation in Transistor Performance and Leakage in Nano-scale Technologies, î IEEE Trans. Electron Devices. 55, 131-144.
[15]Chang R. D. and Lin P. H. 2016. Simulation Study of Implantation Angle Variation and Its Impact on Device Performance. In: 21st International Conference on Ion Implantation Technology (IIT).
[16]Elgomati H. A., Burhanuddin Yeop Majlis, Ahmad I., Salehuddin F., Hamid F. A., Azami Zaharim, Mohamad T. Z. and Apte P. R. 2011. Statistical Optimization for Process Parameters to Reduce Variability of 32 nm PMOS transistor Threshold Voltage. International Journal of the Physical Science. 6, 2372-2379.
[17]Kaharudin K. E., Salehuddin F., Zain A. S. M. and Aziz M.N.I.A. 2016. Taguchi Modelling with the Interaction Test for Higher Drive Current in WSIx/TIO2 Channel Vertical Double Gate NMOS Device. Journal of Theoretical and Applied Information Technology. 90, 185-193.
[18]Kaharudin K. E., Hamidon A. H. and Salehuddin F. 2014. Design and Optimization Approaches in Double Gate Device Architecture. International Journal of Engineering and Technology (IJET) 6.
[19]Mei S., Raghavan N., Bosman M. and Pey K. L. 2018. Stochastic Modeling of FinFET Degradation Based on a Resistor Network Embedded Metropolis Monte Carlo Method. IEEE Transactions on Electron Devices. 65, 440-447.
[20]Abdul Hamid A. H., Menon P. S., Ahmad I. and Shaari S. 2014. Optimisation of Process Parameters for Lower Leakage Current in 22 nm n-type MOSFET Device using Taguchi Method. Jurnal Teknologi. 68(4).
[21]Chaudhuri S., Mishra P. and Jha N. K. 2012. Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology. In: 25th International Conference on VLSI Design.
[22]Donetti L., Sampedro C., Ruiz F. G., Godoy A. and Gamiz F. 2018. Multi-Subband Ensemble Monte Carlo simulations of scaled GAA MOSFETs. Solid-State Electronics. 143, 49-55.
[23]Kaharudin K. E., Salehuddin F., Zain A. S. M., Aziz M. N. I. A., Manap Z., Salam N. A. A. and Saad W. H. M. 2016. Multi-response optimization in vertical double gate PMOS device using Taguchi method and grey relational analysis. In: IEEE International Conference on Semiconductor Electronics (ICSE).
[24]Durairaj M., Sudharsun D. and Swamynathan N. 2013. Analysis of Process Parameters in Wire EDM with Stainless Steel Using Single Objective Taguchi Method and Multi Objective Grey Relational Grade. Procedia Engineering. 64, 868-877.
[26]Sarikaya M. and Güllü A. 2015. Multi-response optimization of minimum quantity lubrication parameters using Taguchi-based grey relational analysis in turning of difficult-to-cut alloy Haynes 25. Journal of Cleaner Production. 91, 347-357.
[27]Zhou S., Zhou L., Yu L., Liu S., Luo Q., Sun P. and Wu J. 2016. Monitoring chip fatigue in an IGBT module based on grey relational analysis. Microelectronics Reliability. 56, 49-52.
