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Keerthi Heragu Vishwani D. Agrawal Michael L. Bushnell

Dept. of Electrical & Computer Eng. AT&T Bell Laboratories Dept. of Electrical & Computer Eng.

Rutgers University 600 Mountain Avenue Rutgers University

Piscataway, NJ 08855-0909 Murray Hill, NJ 07974 Piscataway, NJ 08855-0909

Abstract|We develop new statistical techniques for de- lay fault analysis. True value simulation is performed us- ing a multi-value logic system describing signal states of two consecutive vectors. Signal statistics are used to es- timate transition probabilities and observabilities. These allow us to estimate detection probabilities and the cover- age for transition faults. For path delay faults, recognizing that the total number of possible paths can be exponential in circuit size, we devise an implicit random path sampling procedure to obtain a linear-time estimate of the coverage for all faults. We further derive a longest path theorem to estimate coverages with respect to longest paths through primary inputs and a selected set of fanout branches. Cov- erages are estimated for a minimal set of longest paths such that each signal lead is included in at least one target path whose propagation delay is no less than the delay of any path containing the lead. The fault coverage estimates closely agree with those obtained from delay fault simula- tion while giving a signi cant speedup.

I.INTRODUCTION

We propose a statistical analysis technique to compute delay fault coverage with respect to a given test vector set.

Our method involves fault-free simulation and collection of data for circuit leads. Using these data, a few passes over the circuit are sucient to compute controllabilities and observabilities of all signals. All techniques have linear complexity in the number of lines in the circuit, irrespec- tive of the number of faults considered. This is because our methods add only a small overhead to true-value sim- ulation. Results on benchmark circuits are presented to demonstrate the accuracy in our estimation of fault cover- ages.

II.STATISTICAL ANALYSIS

Some concepts of statistical analysis have appeared in our paper on vector sampling [5]. They are repeated here for completeness. We de ne the following parameters:

 Cr(l) (Cf(l)) or rising (falling) controllability of a linelis the probability of linelhaving a rising (falling) transition on a randomly selected vector pair.

 OLr(l) (OLf(l)) or local rising (falling) observability of a linelis the conditional probability of observing a

rising (falling) transition on linelat the gate output (lbeing one of the inputs of the gate) on a randomly selected vector pair, given thatlhas a rising (falling) transition.

 Sr(l) (Sf(l)) or rising (falling) sensitization proba- bility of a linelis the probability of a rising (falling) transition on linelbeing propagated at the gate out- put (lbeing one of the inputs of the gate) on a ran- domly selected vector pair.

A. Statistical Data Collection

We simulate the circuit for subsets ofN vector pairs.

We have a set of counters for each line. All counters are initialized to 0 at the beginning of simulation of any subset ofN vector pairs. The rising (falling) transition counter of linelis incremented whenever the line has a rising (falling) transition on a vector pair. The rising (falling) sensitiza- tion counter oflis incremented whenever the output of the gate withlas an input has a robustly (non-robustly) propa- gated transition on it andlhas a rising (falling) transition.

After the simulation ofN vector pairs, we calculate:

 Cr(l) = (rising transition counter) /N

 Sr(l) = (rising sensitization counter) /N

A similar calculation is done for falling transitions. The above de nitions apply to both (transition and path) delay faults. However, observabilities must be computed sepa- rately for each type of fault.

B. Detection Probabilities of Transition Delay Faults For transition faults, we deal with signal correlation as in STAFAN [6]. Consider the observability computation for a linel, which is the input of an AND gate with output o. Sr(l) is the joint probability of two events: (a) Linel has a rising transition, and (b) Its value is observable at o. Since the probability of linelhaving a rising transition is Cr(l), the probability of observing the state of lat o, given that lhas a rising transition, equalsSr(l) = Cr(l).

The rising observability of line l with respect to a PO, OPOr(l), is given by:

OPOr(l) = OPOr(o)OLr(l)

= OPOr(o)Sr(l)= Cr(l)

The observabilities of POs are set to 1.0 and a backward pass from the POs computes all observabilities. Fanouts

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require special consideration. Suppose a stem line l fans out to lines a and b. A transition on lcan be observed either throughaorb. If the paths fromaandbto POs were independent, then observability of line lis the probability of theunionof the two events whose probabilities are the observabilities ofaandb. If they were totally dependent, then we assume the other extreme and the observability of linelis taken to be the maximum of the observabilities ofa andb. Experiments show that we can assume either of the two cases at fanout stems without signi cantly a ecting the estimation of fault coverage. A similar analysis holds for falling transitions.

We consider rising and falling transition faults. The ris- ing (falling) detection probability of a transition fault on a line is the product of the rising (falling) observability and rising (falling) controllability of that line.

C. Detection Probabilities of Path Delay Faults

We devise an implicit sampling procedure, which con- siders a random sample of all paths for fault coverage es- timation. Implicit sampling here means that we do not sample from a list of all paths but the random sampling process is included in observability calculation. The sam- ple size can be xed depending on the desired accuracy of the estimate [2].

For every fanout branch, we have a flagthat indicates whether or not the branch has been included in a path fault considered for fault coverage computation. Allflags are initially set to 1 indicating that the branches have not been part of any path fault. We also maintain an indicator, new-path, for every line. This indicates whether or not the path segment being sampled from the line to a PO is part of some path previously considered for the fault coverage computation. All new-path indicators are initially set to false.

Following true-value simulation of N vector pairs, we make backward passes over the circuit for observability calculation. The observabilities of POs are set to 1.0 and observability calculation proceeds backward from POs. A fanout stem assumes the observabilities (rising and falling) of a fanout branch picked randomly from among branches that have their flag as 1. If none of the flags on the branches at a fanout stem have 1, we randomly pick a fanout branch for observability propagation. The new- pathindicator of the stem is set totrueif:

 Theflagof the fanout branch picked is 1, or

 Thenew-pathindicator of the fanout branch selected for observability propagation istrue.

Once the observabilities are computed at the fanout stem, theflagof the fanout branch selected for stem observabil- ities is set to 0. The observability computation for a linel that is an input of a gate is similar to that for transition faults. The new-path indicator of l is set to true if the new-pathindicator of the gate output istrue.

After a backward pass at every primary input (PI) p (or fanout branchp of a PI, if the PI fans out), we have

controllabilities and observabilities of transitions from p to a PO through a randomly selected path. We consider the path fault for fault coverage computation only if the new-pathindicator ofpistrue. The product of the rising (falling) controllability and rising (falling) observability of linepgives the rising (falling) fault detection probability of a path fault originating atp. We initially set the number of paths,F, which is required to be sampled for computa- tion of the fault coverage. This depends on our accuracy requirements. We make backward passes over the circuit until the number of faults considered is equal to or greater thanF. Note that at a PI, we may end up with the ob- servability of a path previously considered for fault cover- age computation. However, these paths are not considered again for determining fault coverages. Thenew-path in- dicators on all lines are set to falseafter each backward pass. For computing the fault coverages, we consider ris- ing and falling transitions on PIs or their fanout branches if they fan out.

D. Detection Probabilities of Longest Delay Path Faults We propose a method to compute fault coverages with respect to a subset of all paths. We choose a minimum set of paths [7] such that, each signal lead is included in at least one target path whose propagation delay is no less than the delay of any path containing the lead. Note that a path can be the longest path through more than one line in a circuit. Hence, we need to consider the longest paths through only a few lines to cover the entire set of longest paths satisfying the above conditions. To avoid duplication of longest paths picked for fault coverage computation, we present the following theorem.

Longest Path Theorem:

In a circuit, the minimum set of paths from inputs to outputs such that each circuit lead is included in at least one path whose propagation de- lay is not less than the delay of any path containing the lead comprises the longest paths through

 All PIs and

 All fanout branches except the ones having the highest level number (with respect to a PO) at their fanout stem.

Although the circuit nodes considered are checkpoints, this theorem should not be confused with the checkpoint theorem that deals with fault equivalence of stuck-at faults by considering faults at all PIs and fanout branches [1].

Proof:

A path is uniquely represented by specifying the PI where it originates and the fanout branches, if any, along the path. Hence, the longest path through the lines that are not fanout branches will be one of the following:

 The longest path through some PI, or

 The longest path through some fanout branch.

Consider fanout branches in the circuit of Figure 1. Lines are given level numbers to indicate their maximum dis- tance from POs. For example, the label l(4) means that the maximum distance of linelfrom POs is 4. We write

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dist-PO(l) = 4. For a lineiwhich is the output of a gate, we label all inputs of that gate as (dist-PO(i) + 1). For every fanout stem iwith branches i1,i2, ..., ik, we label line i as maximum1jk(dist-PO(ij)). In practice, the distance can be weighted according to any given delays of circuit elements. Consider the analysis at fanout stem r. The longest path through fanout branchohaving the highest level number is also the longest path through PIs k anda. This is because at fanout stems, the branch hav- ing the highest level number is selected for determining longest paths through PIs. Therefore, we must avoid such paths when considering additional paths through fanout branches. At all fanout stems, the path through the fanout branch having the highest level number has already been selected as the longest path through some PI and hence we avoid choosing the path corresponding to that fanout branch while adding to the set of longest paths. We con- sider all the longest paths through other fanout branches to meet the requirement that every lead should be included in at least one selected path. Thus, the longest paths through all PIs and a selected set of fanout branches comprise the entire set of longest paths that satisfy our requirements.

Q.E.D.

The selection of paths is based on the assumption that the paths most likely to fail are those with longest delay.

We de ne additional parameters for each line:

 OIr(l) (OIf(l)) or rising (falling) PI-observability of a line lis the conditional probability of observing a rising (falling) transition on a PI at linelthrough the longest segment from a PI to line l on a randomly selected vector pair, given that the PI has a rising (falling) transition.

 OOr(l) (OOf(l)) or rising (falling) PO-observability of a linelis the conditional probability of observing a rising (falling) transition on linelat a PO through the longest segment from linelto a PO on a randomly selected vector pair, given thatlhas a rising (falling) transition.

Following the fault-free simulation of a set of N vector pairs, we make two passes over the circuit. Observability propagation, as accomplished by these passes, is illustrated next by an example. In Figure 1, we make a backward pass over the circuit where lines have level numbers (in parentheses) to indicate their maximum distance from POs as explained above. The rising (falling) observability of a line l computed during the backward pass is denoted by OOr(l) (OOf(l)). The observability computation for a line l, which is not a fanout stem, is similar to that for the transition faults. However, at a fanout point, the stem assumes the observability of the branch having the highest level number (with respect to a PO). If there are two or more branches with identical level numbers, any one is selected tominimizethe set of longest paths. In Figure 1, the rising PO-observability of line lwith respect to a PO through the longest segment,OOr(l), is given by:

j(1)

i(2) p(2)

o(3)

x(2)

y(1) f(2) e(3)

m(3) l(4)

b(5) d(5)

k(6) a(6)

n(4) g(3)

h(3)

q(3) r(3)

c(4)

Figure1: Backwardpassoverthecircuit

OOr(l) =OOr(r)OLr(l) =OOr(r)Sr(l)= Cr(l) Since at fanout stemr, the fanout branchohas a higher weight (level number in this case) than branchp, the rising PO-observability ofr is given by:

OOr(r) =OOr(o)

After the backward pass, the rising PO-observability of linelwill be:

OOr(l) = OLr(o)OLr(x)OLr(y)OLr(l) (1) The backward pass is then followed by a forwardpass over the circuit during which local line observabilities are multiplied. Referring to Figure 2, level numbers (in paren- theses) are reassigned to gates to indicate their maximum distance from PIs. Labeling can be done analogous to the

g(1) h(1)

i(2)

k(1) a(1)

b(2) d(1)

l(3) n(1)

m(3)

e(1) f(4)

o(4)

x(5) q(1)

y(6) p(4) j(5) r(4)

c(3)

Figure2: Forwardpassoverthecircuit

backward level numbering scheme explained above. The rising (falling) observability of a line l computed during the forward pass is denoted byOIr(l) (OIf(l)). At the output of every gate, the observability corresponding to the input with the largest level number (with respect to a PI) is chosen for propagation. If there are two or more

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inputs with identical level numbers, only one is selected to minimize the set of longest paths. The observabilities of all fanout branches are assumed to be the same as that of the corresponding fanout stems. Controllabilities of the corresponding PIs are also carried along in a similar man- ner. Consider a rising transition on lin Figure 2. The rising PI-observability equals:

OIr(l) = OLr(a)OLr(b)OLr(l) (2) The observability of line b is chosen over that of d for propagation due to its higher level number (with respect to PIs).

During the forward pass, for every line, we obtain the nal rising (falling) observability by multiplying the rising (falling) PI-observability and PO-observability and divid- ing this product by the local observability of the line. From equations (1) and (2), for line l, we have the nal rising observability of the longest path through it as:

OPOr(l) = OIr(l)OOr(l)= OLr(l)

= OLr(a)OLr(b)OLr(l)OLr(o)

OLr(x)OLr(y)OLr(l)= OLr(l) OPOr(l) = OLr(a)OLr(b)OLr(l)OLr(o)

OLr(x)OLr(y)

This exactly equals the product of observabilities of lines on the longest path through l. Since the controllability information carried along tolis the controllability ofa(a PI), the product of the rising (falling) controllability and rising (falling) observability calculated atlgives the rising (falling) detection probability of the fault corresponding to the longest path throughl. After the two passes, every line will have the rising and falling path delay fault detection probabilities of the longest path through it.

To compute the fault coverage, we consider rising (falling) detection probabilities of longest paths through all PIs and a selected set of fanout stems, as determined by the longest path theorem.

E. Determining Fault Coverage

Once we determine fault detection probabilities for any type of fault model, we compute the corresponding fault coverage as explained below. If the detection probability of a fault isx, the probability of this fault being detected by a set of Nvector pairs isX(N) = 1?(1?x)N. Since we use a statistical estimate for x,X(N) is also a random variable whose values become exact as N ! 1. With niteN, the detection probability may contain a random error, which is biased [6]. The unbiased estimate is given by:

X(N) = 1?(1?x)N= W(x)

where W(x) = 1 + 2x(N?1) = (6(1?x)) and is a constant determined empirically. We obtained good results

with ( 2=6 = 10) while simulating in blocks of 20 vector pairs (N = 20).

We divide the vector set intonsubsets ofNvector pairs each. Note that we simulate the circuit in sets ofN vector pairs only for the transition and longest path fault models.

For the all path delay fault model, we simulate the entire vector set before computing controllabilities and observ- abilities. This is because we pick path faults randomly, and it is not possible to correlate the detection probabilities ob- tained from various subsets if the test set is divided. For the ith fault, if the detection probabilities for the vector subsets arexi1,xi2, ..., xin, the probability of detecting this fault by thenvector subsets is:

di(V) = 1?Yn

k =1

(1?xik)N= W(xik)

where V is the total test vector count. The cumulative fault coverage forF faults is:

D(V) = 1F

F

X

i=1

di(V)

III.RESULTS

We consider the full-scan versions of the ISCAS-89 benchmark circuits. We demonstrate the e ectiveness of our method by comparing our results with those from two existing fault simulators [3, 8]. The test vectors were algo- rithmically generated. The execution times in Table 1 are for a SUN 4/280 workstation. Table 1 shows non-robust coverages for both transition and all path delay faults. The method can also be used to nd robust fault coverages by considering robustly propagated transitions for statistical estimation. For path delay faults, we xed the number of backward passes following true-value simulation atfive. We expect the speedup in CPU time to be even higher for larger circuits. Table 2 shows non-robust coverages for the longest path faults. We have not given a comparison with fault simulation results due to the unavailability of a longest path fault simulator. Based on our results for the transition and all path delay faults, we expect the cover- age estimates for longest paths to be good. To examine the performance of our method on large circuits, we es- timated path delay fault coverages using 30,000 random patterns. As seen from Table 3, the time for estimation is linear in circuit size [4]. Results from fault simulators were not available for these large circuits.

IV.CONCLUSION

The linear complexity statistical alternatives to fault simulation of delay faults appear practical. Results show that the methods are useful in predicting transition and path delay fault coverages (either for all or longest paths) with good accuracy, while adding only a small overhead to true-value simulation. However, the question whether or

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Table1: Non-robustcoverage-transitionandallpathdelayfaults

Circuit Total Transition Faults Path Delay Faults

Name # Statistical Fault Statistical Fault

Vect. Estimator Simulator[8] Estimator Simulator[3]

Cov% CPU(s) Cov% CPU(s) Cov% CPU(s) Cov% CPU(s)

s208 580 100.0 1.0 100.0 1.9 97.1 1.3 100.0 5.0

s344 1286 99.7 2.7 99.9 4.1 92.7 3.2 90.6 20.4

s349 1286 98.9 2.8 98.7 4.1 91.0 3.4 88.1 21.1

s382 1408 100.0 3.4 100.0 5.5 90.0 3.9 88.0 20.2

s510 1476 100.0 4.2 100.0 5.9 98.5 5.0 100.0 23.1

s526 1416 100.0 4.6 100.0 6.2 84.1 5.6 86.3 22.6

s820 1968 100.0 9.6 100.0 14.0 97.6 13.1 100.0 38.2

s832 1992 99.9 10.3 99.9 14.4 98.0 14.4 98.4 38.9

s953 4152 100.0 24.1 100.0 30.0 97.1 32.1 97.0 111.8

s1488 3832 98.2 39.6 96.7 54.8 96.8 50.1 99.6 145.0

s1494 3852 98.2 40.1 98.2 55.9 95.7 52.1 98.7 148.3

Table 2: Non-robust coverage - longest path delay

faults

Circuit # Longest Path Name Vect. Delay Faults

Cov% CPU(s)

s208 580 83.8 1.0

s344 1286 69.4 2.8

s349 1286 62.3 2.8

s382 1408 84.6 3.3

s510 1476 83.2 4.1

s526 1416 87.4 4.6

s820 1968 90.0 9.6

s832 1992 89.1 10.5

s953 4152 88.2 24.6

s1488 3832 71.7 39.3

s1494 3852 73.6 41.1

Table3: Non-robustcoverage-allpathdelayfaults

Circuit # Path

Name Vect. Delay Faults Cov% CPU(s) s13207 30,000 59.1 4116.5 s35932 30,000 74.4 13337.2 s38417 30,000 56.4 13703.8

not a fault is detected by the given vectors is answered only in a probabilistic sense. This may still be useful forfault droppingby a delay fault test pattern generator. Only full- scan circuits were considered but the methods can be ex- tended to non-scan synchronous circuits. We should men- tion that our methods provide two-sided estimates of fault coverage. That is, the error can either increase or decrease the fault coverage. We believe that such estimates are use- ful as long as we can keep the magnitude of the error small.

This is because even theso-called exactcoverage, as deter- mined by a fault simulator, is based upon numerous as- sumptions underlying the fault model and the simulation algorithm. The usefulness of an algorithm or the result it produces, whether exact, statistical (two-sided approx- imation), or pessimistic (one-sided approximation), must be based on practical experience.

References

[1] M. Abramovici, M. A. Breuer, and A. D. Friedman.Digital Systems Testing and Testable Design. Computer Science Press, New York, 1990.

[2] V.D. Agrawal. Sampling Techniques for Determining Fault Coverage in LSI Circuits. Jour. Digital Syst., V:189{202, 1981.

[3] S. Bose, P. Agrawal, and V. D. Agrawal. Path Delay Fault Simulation of Sequential Circuits. Trans. VLSI Systems, 1(4), Dec. 1993.

[4] K. Heragu. Approximate and Statistical Methods to Com- pute Delay Fault Coverage.MS Thesis, ECE Dept., Rutgers University, May. 1994.

[5] K. Heragu, V. D. Agrawal, and M. Bushnell. FACTS: Fault Coverage Estimation by Test Vector Sampling. In Proc.

VLSI Test Symp., Apr. 1994.

[6] S. K. Jain and V. D. Agrawal. Statistical Fault Analysis.

IEEE Design & Test of Computers, 2(1):38{44, Feb. 1985.

[7] W. Li, S. M. Reddy, and S. K. Sahni. On Path Selection in Combinational Logic Circuits.IEEE Trans. CAD, 8(1):56{

63, Jan. 1989.

[8] I. Shaik. A Robust Delay Fault BIST Model. MS Thesis, ECE Dept., Rutgers University, Oct. 1992.

References

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