16-bit ALU, Register File and Memory Write Interface

CS M152B – Fall 2002

Project 2

16-bit ALU, Register File and Memory Write

Interface

Suggested Due Date: Monday, October 21, 2002

Actual Due Date determined by your Lab TA

This project will take much longer time than the previous one. The three components you are building in the project will be put all together and program to the board to be tested. The three components do not depend on each other. Therefore, I suggest you to start them in parallel. The only thing that prevents you from fully parallelizing the work is because there is only one workstation for each group. So, you should consider how to fully utilizing your resources (your team members and the workstation) to finish this project soon. However, keep in mind that you should know how to build each component even if you are not participating in building some of the components.

PART 0

In project 1, the & and | functions are specified as “logical”, they should be “bitwise”. They are meant to be bitwise if you look at the expected test results. Sorry for the confusion.

Now, do a modification to the 4-bit ALU built in project 1. Add the complement (bitwise NOT) operation. The control signal is “110” for NOT. Make sure your 4-bit ALU is built with minimum area. The chip area is measured in SLICEs. The chip has 768 SLICEs available. You can check the number of SLICEs used in your design from the Place & Route Report. The TA’s implementation used 10 SLICEs for the 4-bit ALU.

PART 1 – 16-Bit ALU

Design

You are asked to build a 16-bit asynchronous ALU that can do addition, subtraction, bitwise AND, bitwise OR, increment, decrement, bitwise NOT, shifting, and comparison. The top level schematic is shown in the following figure.

The following is the functional truth table.

ALU Ctrl Function

0000

S = A + B

0001

S = A – B

0010

S = A & B (bitwise AND)

0011

S = A | B (bitwise OR)

0100

S = A + 1

0101

S = A – 1

0110

S = ~A (complement)

1100

S = A << B(3:0) (logical shift)

1110

S = A >> B(3:0) (logical shift)

1000

S = A << B(3:0) (arithmetic shift)

1010

S = A >> B(3:0) (arithmetic shift)

1001

If (A < B) S = 1 else S = 0

* The output zero is ‘1’ when S is 0, otherwise zero is ‘0’. * Be aware that the control signal is now 4 bits wide.

* The shifting must be asynchronous (i.e. can’t use shift register); the shifting distance range is between 0 and 15.

* The ripple-carry is used between the 4-bit ALUs.

* Your first priority is to minimize the area of your design; second priority is performance (delay)

* You are welcome to use

• Schematic

• VHDL

• CORE IP

• Your previous project

• or any combination of the above

S(15:0)

zero

Cout

ALUctrl(3:0)

A(15:0)

B(15:0)

Hint: You can’t put 4 copies your project 1 together plus some other components to build this 16-bit ALU. You can use it as the least significant 4-16-bit of the ALU but it requires some modifications for the most significant 12-bit of the ALU. Think about the A+1 and A-1 cases.

One of the design choices of the shifting is barrel shifter. The (A < B) comparator can be done by a subtraction with the ALU.

Simulation

With ModelSim, simulate each function with some numbers for A and B of your choice just to make sure that it really works.

PART 2 – Register File

Design

You are asked to build a register file with eight 16-bit registers. It should have two read ports and one write port. The top level schematic is shown below.

* busA, busB and busW are each 16 bits wide; Ra, Rb, and Rw are each 3 bits wide. * it works as the following:

busA <= R[Ra]; busB <= R[Rb]; when WrEn is ‘1’,

R[Rw] <= busW at next clock cycle; * R[0] always holds value of 0;

* Your first priority is to minimize the area of your design; second priority is performance (delay)

* You are welcome to use

• Schematic

• VHDL

• CORE IP

• or any combination of the above

Ra

Rb

Rw

WrEn

busW

busA

busB

Reg.

File

Suggestion: use FD16CE symbol as a single register to start building the register file. Simulation

With ModelSim, simulate writing/reading values to/from the register file to make sure that it really works.

PART 3 – Memory Write Interface

Design

In order to write to the SRAM using the provided VHDL file “sraminterfacewithpport-sv01.vhd”, you need to implement the protocol specified in page 3 of tutorial 2. The module that implements the protocol is referred as the Memory Interface here. Basically, the Memory Interface is a state machine. Therefore you need to understand the protocol and implement the state machine to interact with the provided VHDL module to write data. The following is the top level schematic of the memory interface and the “sraminterfacewithpport-sv01.vhd” module.

Memory Write Interface Module Inputs : clk

ResetL (active low; to initial state) IssueWrite; CanWrite; Outputs: DoWrite; WriteDone; CanWrite DoWrite WriteAddr WriteData Memory Write

Interface (to be built)

WriteDone IssueWrite resetL clk Sraminterfacewithpport-sv02.vhd (provided)

* The interface should work according to the following: When writing a data, within the same clock cycle do

{

send the data on WriteData; send the addr on WriteAddr; assert the IssueWrite

}

after some number of clock cycles, the WriteDone signal goes ‘high’, meaning the write operation is done.

* You can use Behavioral VHDL as long as it can be synthesis and other tools as usual to implement state machine.

Simulate

With ModelSim, verify the state transition goes correctly in your state machine design.

Putting it all together

Now, you should have a working 16-bit ALU, a register file and a memory write interface. Let’s create a top level schematic that put all of these together like the following figure.

Go to My Network Places\Computers Near Me\152b-lab-01\Project2Files folder, copy all files to your local project directory. They includes the Control Module (TACM) and the sraminterfacewithpport files.

busA busB Ra Rb Rw WrEn BusW clk Reg. File ALU zero

Memory write interface

ALU Ctrl sraminterfacewithpport WriteAddr WriteData canWrite doWrite issueWrite clk resetL WriteDone Control Module provided by TA Clk ResetL IssueWr NextWr Addr SelectL button

This circuit will allow you to do an ALU operation on two registers and write the result back into a register as well as write to the memory, from where you can ‘dump’ to check the result.

PIN allocation:

• a single reset input connect to the resets of the control module, the memory write interface and the sraminterfacewithpport module; this single reset <= push button 1 (remember, all reset should be active low)

• a single clk input connect to the clk of all modules that has the clk inputs. This single clk <= usual clk pin.

• Control Module

o SelectL button(active low) <= push button 4

o WriteL button(active low) <= push button 3

• Register File (because we only have 8 dip switches, the MS bit of Rb is forced to ‘1’)

o Ra(2:0) <= dip switch(1:3)

o Rb(1:0) <= dip switch(4:5)

o Rw <= dip switch(6:8)

• Make an output bus from ALUCtrl

o ALUCtrl(3:0) <= bar LED(9:6)

• And don’t forget to connect the pins for the sraminterfacewithpport

o the left bank SRAM

§ ldata(15:0)

§ laddr(18:0)

§ lcen

§ loen

§ lwen

o the parallel port

§ ppdata(7:0)

§ ppstatus(6:3)

Program to the Board and Test

After you finish this top level schematic, you can simulate it with ModelSim (optional). Then you need to program it to the board.

Testing Procedure:

1. Press the push button 1 to reset.

2. Flip to dip switches to select the operands and the destination register.

3. Repeat pressing the push button 4 to select an ALU function of your choice (the control code of the operation is shown on bar LED (9:6)

4. Press the push button 3 to write

5. ‘Dump’ the memory contents to the screen. 6. If you want to test more, go back to step 2.

Project Report

• Describe your design for PART 1-3.

• Report the number of SLICEs used for each part (1-3) separately. (the SLICEs information can be found in the Place & Route Report)

• Report the Maximum Net Delay of each part (1-3) separately. (the Delay information can be found in the Asynchronous Delay Report)

The End of Project 2.

• If you need to put a lot of the same components in the schematic, put one first, draw wires to all inputs/outputs. Then select this component and all the wires by drawing selecting square. Then copy & paste. You can get 1, 2, 4, 8, 16, 32… of the same components with wires fast by repeating copy & paste. (Notice that the copy and paste will not copy the wire name)

• When you backup your file, you should select Project -> Delete Implementation Data, then select Project-> Archive… to create a zip file. You can unzip a file from the DOS prompt by “unzip [zipfile] –d [directory]” (Notice that if you delete the implementation data, you need to redo the Synthesize and Implement steps to your design in order to program to the board.

• Components generated from COREgen IP tend to take up more SLICEs than the symbols from the library.

• In schematic, two wires are connected if they have the same name even they appear to be

not connected in the editor. As the design gets big, it will make the schematic really messy if all the wires are connected. Another thing is that you don’t need to use any bus trap. Just name a wire called ABC(2:0), and name other wires ABC(0), ABC(1), ABC(2). Then they are connected just like there were the bus traps.