VLSI Design

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VLSI DESIGN – EDA Tools

Lecture by

Prof.R.V.B.Chary

Director, Center for VLSI DESIGN

CVR Engg College.

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VLSI DESIGN METHODOLOGIES

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CURRENT VLSI IMPLEMENTATION

TECHNOLOGY

TECHNOLOGY : CMOS

Channel Length

• MICRON CMOS

> 1 um

• SUB-MICRON CMOS

>0.18um

• DEEP SUB-MICRON CMOS <0.18um

• NANOMETER CMOS

< 100 nm

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VLSI

IMPLEMENTATION

METHODS

FULL-CUSTOM

SEMI -CUSTOM

Standard Cell

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COMPARISON

LOW

MEDIUM

HIGH

COST

HIGH

MEDIUM

LOW

SPEED

HIGH

MEDIUM

LOW

DENSITY

LONG

MORE

LESS

TIME TO

MARKET

FULL

CUSTOM

STANDARD

CELLBASED

FPGA

BASED

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Design Flow

• Full Custom CMOS Chip Design Flow

• Semi-Custmom FPGA Based Design Flow

• Semi-Custom Standard Cell Library Based

CMOS Chip Design Flow

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FULL CUSTOM CMOS CHIP DESIGN

USING CADENCE TOOLS

Requirements:

• CMOS Physical Design Kit (

PDK

)

• NMOS / PMOS Device spice models & symbols

• DRC Rule File

• Extraction Rule File

• L V S Rule File

• Tool:

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CADENCE FULL CUSTOM DESIGN

TOOL – ICFB

ICFB consists of :

– VIRTUOSO SCHEMATIC COMPOSER

– VIRTUOSO LAYOUT EDITOR

– Assura / DIVA DRC, EXTRACT, LVS Physical

Design VERIFICATION TOOLS

– SPECTRE SPICE SIMULATOR (ANALOG

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CMOS TECHNOLOGY FILES AVAILABLE

AT CENTER FOR VLSI DESIGN

• 1.2 um CMOS Physical Design Kit of SCL

Semiconductor Complex Limited,

(CHIP– INDIA)

• S C L 1.2 um Digital Standard Cell Library

• 0.2 um CMOS Generic PDK Kit from Cadence website

• NCSU Cadence PDK Kit

• 0.18, 0.2um, 0.3um, CMOS PDK - TSMC • 0.6 um, 1.6 um, CMOS PDK - AMI

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FULL CUSTOM CMOS IC-DESIGN FLOW

USING CADENCE TOOLS

• DESIGN SPECIFICATIONS

• ARCHITECTURE(FUNCTIONAL BLOCKS &

LEAF CELLS)

• CMOS LEAF CELL DESIGN FLOW

– CMOS TRANSISTOR LEVEL CIRCUIT DESIGN FOR

LEAF CELL

– SYMBOL CREATION

– TEST BENCH FOR SPICE SIMULATION

– PHYSICAL (LAYOUT) DESIGN

– DESIGN RULE CHECK (DRC)

– EXTRACTION

– LAYOUT Vs SCHEMATIC VERIFICATION (LVS)

– POST LAYOUT SIMULATION

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FULL CUSTOM CMOS CHIP

DESIGN EXERCISE USING

CADENCE TOOLS

UG Final Year Project (2005-2006)

Signed/Unsigned Array

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CMOS Leaf Cells Design Flow

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Inverter Schematic SPICE

Simulation

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Inverter Extracted View without

Parasitics

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Inverter Extracted Layout View

With Parasitics

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Top Level CORE Schematic with

I/O Pads

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Top Level CORE Layout Without

Pads

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Top Level CHIP Layout With Pads

for Silicon Foundry

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• CMOS FUNCTIONAL BLOCKS DESIGN USING LEAF

CELLS

• CMOS CIRCUIT DESIGN, SYMBOL CREATION & SPICE

SIMULATION

• CMOS LAYOUT DESIGN

– MANUAL PLACE AND Routing using designed LEAF CELLS – PHYSICAL VERIFICATION(D R C, EXTRACTION, LVS)

– POST-LAYOUT SIMULATION

• TOP LEVEL FULL CUSTOM CMOS CHIP

ASSEMBLING

• Top level Schematic circuit

• Symbol Creation

• SPICE Simulation

• Top level Layout design using Functional Layout blocks(Manual

Place and Route)

• Physical Verification (DRC, Extraction LVS)

• Postlayout Simulation for SIGNOFF

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SEMI CUSTOM FPGA BASED

DESIGN FLOW

• FRONT – END DESIGN FLOW

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FRONT-END DESIGN FLOW FOR CPLD /

FPGA IMPLEMENTATION

• Design Idea / Specifications

• Architecture

• VHDL / Verilog Modelling

• Functional Simulation

• Logic Synthesis

• Post Synthesis Simulation

Note : This is to arrive at Gate Level VHDL /

Verilog Netlist and Gate Level circuit for Vendor

FPGA Technology Library

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FRONT END DESIGN

EDA TOOLS FOR FPGA/CPLD

• POPULAR VHDL/VERILOG SIMULATORS

• Modelsim Simulator

• Active HDL Simulator

• Speedwave

• Silos for Verilog Simulation

• POPULAR CPLD / FPGA SYNTHESIS TOOLS

• Synplify Pro

• FPGA Express

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FRONT-END DESIGN EXERCISE

FOR FPGA IMPLEMENTATION

• SPECIFICATIONS

SYNCHRONOUS 4-BIT COUNTER

ASYNCHRONOUS RESET

• BLOCK DIAGRAM OF THE COUNTER

COUNTER

CLK RESET

Q(3:0) OUTPUT

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COUNTER VHDL MODEL

• library ieee; • use ieee.std_logic_1164.all; • use ieee.std_logic_unsigned.all; • entity counter is • port(clk,reset:in std_logic;

• q:out std_logic_vector(3 downto 0));

• end counter;

• architecture behv of counter is

• signal qi :std_logic_vector(3 downto 0);

• begin

• process(clk,reset)

• begin

• if reset = '1' then

• qi <= "0000";

• elsif clk'event and clk='1' then

• qi <= qi + 1;

• end if;

• end process;

• q <= qi;

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VHDL SIMULATION ENVIRONMENT

VHDL COMPILER VHDL MODEL FILE INTERMEDIATE CODE FOR VHDL MODEL IEEE LIBRARY VHDL SIMULATOR APPLY STIMULUS

WAVE FORM WINDOW

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FPGA LOGIC SYNTHESIS

VHDL MODEL FILE SYNPLIFY PRO SYNTHESIS TOOL VHDL NETLIST FILE FPGA TECH FILE CONSTRAINTS

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SAMPLE NET LIST FROM SYNTHESIS

• Written by Synplicity • -- Wed Dec 21 10:34:28 2005 • library ieee; • use ieee.std_logic_1164.all; • use ieee.numeric_std.all; • library synplify; • use synplify.components.all; • entity L1_2 is • port( • Z : out std_logic; • I0 : in std_logic); • end L1_2; • architecture beh of L1_2 is • signal GND : std_logic ; • signal VCC : std_logic ; • begin • GND <= '0'; • VCC <= '1'; • Z <= I0; • end beh;

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BACK –END DESIGN FOR FPGA

PLACE AND ROUTING THE NET LIST TO GENERATE

BITMAP FILES

NET-LIST FILE _{PLACE AND ROUTE} BIT-MAP FILE

FPGA DEVICE

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POPULAR FPGA DESIGN KITS

ALTERA FPGA DESIGN KITS

¾ MAX+ PLUS II FPGA DEVELOPMENT KIT

¾ QUARTUS FPGA DEVELOPMENT KIT

XILINX ISE FPGA DESIGN KIT

ISE FPGA DESIGN KIT

ISE EMBEDDED KIT

These Kits Comprises

¾

VHDL/VERILOG HDL SIMULATOR

¾

VHDL/VERILOG SYNTHESIS TOOL

¾

PLACE AND ROUTE

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SEMI-CUSTOM STANDARD CELL

LIBRARY BASED CMOS IC

DESIGN FLOW USING CADENCE

TOOLS

• Front End Design Flow

• Back End Design Flow

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Front End Design Flow

• Design Idea / Specifications

• Architecture

• VHDL / Verilog Modelling

• Functional Simulation

• Logic Synthesis

• Post Synthesis Simulation

Note : This is to arrive at Gate Level VHDL /

Verilog Netlist and Gate Level circuit Vendor

Standard Cell Library

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FRONT-END DESIGN FLOW and

CADENCE EDA TOOLS

NCVHDL / NC VERILOG SIMULATOR VHDL / VERILOG MODELFILE RTL COMPILER / BUILD GATES SYNTHESIS TOOL VENDOR STANDARD CELL LIBRARY CONSTRAINTS

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CONTD… VHDL/VERILOG NET LIST POST SYNTHESIS SIMULATION USING NC VHDL / NC VERILOG SIMULATORS

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BACK-END DESIGN FLOW AND CADENCE TOOLS

VERILOG NETLIST

FILE

SOC ENCOUNTER / SILICON ENSEMBLE TOOL (LAY-OUT LEVEL AUTO PLACE AND

ROUTE) STANDARD CELLS LIBRARY LEF FILE GDS II DATA FILE CONTD…

THIS GDS FILE CONTAINS ABSTRACT VIEW OF THE STANDARD CELLS AND WHOSE CONNECTIVITY WITH METAL LAYERS

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CONTD…

I C F B TOOL

(IC FRONT-END TO BACK-END TOOL)

VERILOG NET LIST

FILE

GDS II FILE

ASSURA / DIVA DESIGN RULE CHECK EXTRACTION

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CONTD…

POST LAY-OUT SIMULATION SPECTRE SPICE SIMULATOR

(ANALOG SIMULATOR)

GDS II DATA FILE (TAPE OUT)

SILICON FOUNDRY

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Example Demo for Standard Cell

Based Semi-custom Counter

Design Flow

Counter Verilog Code

module counter(clk,rst,qout); output [3:0] qout; input clk,rst; reg [3:0] qout; always@(posedge clk or posedge rst) begin if(rst) qout <= 4'h0; else qout <= qout + 4'h1; end endmodule

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Counter Test Bench

module tb_counter; reg clk,rst; wire [3:0] qout; counter u0 (clk,rst,qout); initial begin

$sdf_annotate ("/home/chalapathi/rc/rc52lab/work/counter_sdf.sdf.X", u0); clk = 1'b0; rst = 1'b0; #10 rst = 1'b1; #20 rst = 1'b0; end always #10 clk = ~ clk ; endmodule

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Gate Level Circuit Generated by

RTL Compiler Synthesis Tool

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Auto Place and Route using SOC

Encounter at Layout Abstract Level

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EDA TOOLS

AT

CENTER FOR VLSI DESIGN ,

C V R ENGG. COLLEGE

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EDA Tools & Systems available at Center for

VLSI Design:

Cadence EDA Tools for Semi Custom & Full

Custom VLSI Design:

1) NC-VHDL Simulator

2) NC- Verilog Simulator

3) Build Gates Extreme synthesis tool

4) Silicon Ensemble/ SoC encounter for

Auto Place &

Route.

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5) Virtuoso Schematic Capture

6) Virtuoso Layout Editor

7) Diva/ Assura Layout verification for

i. Design Rule Check.

ii. Extractor

iii. Layout Vs Schematic Checker

8) Analog Simulator: Spectre Spice

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EDA Tools under ALTERA University

Program:

Modelsim for VHDL/Verilog Simulation

Quartus FPGA Developer Software

Max Plus II CPLD/FPGA Developer Software

CPLD/FPGA Programmer Boards

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EDA Tools under XILINX University

Program:

ISE 8.1 FPGA Development Software

Chip Scope Software

ISE Embedded Development Software Kit.

SPARTAN-3 FPGA Programmer Boards.

PICO Blaze & Micro Blaze Micro Controller

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Synplify Pro Synthesis tool for CPLD/

FGPA devices.

Multisim 7 Spice simulator.

Texas DSP trainer Kits.

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License Servers:

Cadence Server

ALTERA Server

Synplify Pro Server

Workstations:

Sun SPARC Systems.

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FINAL YEAR UG PROJECTS CARRIED OUT

AT

CENTER FOR VLSI DESIGN

DURING

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1. PROGRAMMABLE BAUD RATE GENERATOR

CMOS CHIP DESIGN USING CADENCE TOOLS

by

Mr. M.Raghavendra, Roll No. 02B81A0446

&

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2. ALU CMOS CHIP DESIGN USING CADENCE

TOOLS

by

Mr. N.Vijaya Bhaskara, Roll No. 02B81A0488

&

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3. ARRAY MULTIPLIER CMOS CHIP DESIGN

USING CADENCE TOOLS

by

Mr. Gaurav Bhatia, Roll No. 02B81A0415

&

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4. SERIAL ADDER CMOS CHIP DESIGN USING

CADENCE TOOLS

by

Ms. Preethi Tiwari, Roll No.

02B81A0414

&

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5. UNIVERSAL SHIFT REGISTER CMOS CHIP

DESIGN USING CADENCE TOOLS

by

Ms. M. Hima, Roll No. 02B81A0419

&

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6. 8-BIT ACCUMULATOR CMOS CHIP DESIGN

USING CADENCE TOOLS

by

Mr. K.Rakesh,Roll No. 02B81A0448

&

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7. PROGRAMMABLE SYNCHRONOUS

UP-DOWN COUNTER WITH PARELLEL LOAD

CMOS CHIP DESIGN USING CADENCE TOOLS

by

Ms. K.Manga,Roll No. 02B81A0433

&

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8. SERIAL MULTIPLIER CMOS CHIP DESIGN

USING CADENCE TOOLS

by

Ms. N.Ramya Reddy,Roll No. 02B81A0450

&

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9. FPGA BASED MAC CHIP DESIGN AND

VERIFICATION USING XILINX TOOLS

by

Mr. S.A Mahesh Kumar,Roll No.

02B81A0430

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Ongoing UG Projects [ 2006-07]

• Single Cycle 32 Bit RISC Processor VHDL

Design and Synthesis

• 16 Bit CPU Verilog HDL Design and

Synthesis

• 16 Bit CPU VHDL Design and Synthesis

• UART Verilog HDL Design and Synthesis

• Peripheral Interface Chip SemiCustom

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..contd

• Full Custom Flash ADC CMOS Chip

design

• Full Custom Complex Multiplier CMOS

Chip Design

• Full Custom Stop-Watch CMOS Chip

Design

• FPGA based Embedded System using

Picoblaze RISC Processor IP

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