Effect of Annealing Ambient on Structural and Electrical Properties of Ge Metal Oxide Semiconductor Capacitors with Pt Gate Electrode and HfO2 Gate Dielectric

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Eﬀect of Annealing Ambient on Structural and Electrical Properties

of Ge Metal-Oxide-Semiconductor Capacitors

with Pt Gate Electrode and HfO

₂

Gate Dielectric

S. V. Jagadeesh Chandra

1

, Myung-Il Jeong

1

, Yun-Chang Park

2

,

Jong-Won Yoon

3

and Chel-Jong Choi

1;4;*

1_{School of Semiconductor and Chemical Engineering, Semiconductor Physics Research Center (SPRC),}

Chonbuk National University, Jeonju 561-756, Korea

2_{Measurement and Analysis Division, National Nanofab Center (NNFC), Daejeon 305-343, Korea}

3_{Department of Advanced Materials Science and Engineering, Dankook University, Cheongan 330-714, Korea} 4_{Department of BIN Fusion Technology, Chonbuk National University, Jeonju 561-756, Korea}

We fabricated Ge metal-oxide-semiconductor (MOS) devices with Pt/HfO2gate stacks and investigated the eﬀect of thermal treatment on

their structural and electrical properties in oxygen (O2) and forming gas (FG) environments. The annealing ambient dependency of the structural

and electrical properties of Ge MOS devices was directly compared to that of Si MOS devices. For both Ge and Si MOS devices, the thermal treatment process led to a decrease in accumulation capacitance regardless of the annealing ambient. The interfacial layer (IL) at the HfO2/Ge

stack was much thinner than the HfO2/Si stack. O2annealing resulted in the improvement of the HfO2interfacial quality of Ge and Si MOS

devices, although the improvement of the Ge devices was greater than that of the Si devices. FG annealing was much more eﬀective in the reduction of interface state density (Dit) in Si devices than in Ge devices. A negligible IL at a HfO2/Ge stack could be a main cause of degraded

electrical performance of a Ge device with FG annealing. [doi:10.2320/matertrans.M2010324]

(Received September 16, 2010; Accepted October 22, 2010; Published December 8, 2010)

Keywords: metal-oxide-semiconductor (MOS), germanium, silicon, HfO2, annealing, interfacial layer, density of interface state

1. Introduction

Extensive studies have been conducted on high dielectric

constant (high-k) materials as possible replacements for

conventional SiO2gate dielectric material in complementary

metal-oxide-semiconductor (CMOS) devices, which require

an equivalent oxide thickness (EOT) of below 1nm.

Among various high-k materials, HfO2 has been identiﬁed

as a promising candidate to meet the scaling requirements stated in the International Technology Roadmap for Semi-conductors.1)_{There is a need for alternate channel materials} that can enhance channel mobility beyond the physical limits of Si-based CMOS devices without sacriﬁcing the produc-tivity required by semiconductor device manufacturers. Recently, Ge has received considerable attention as a promising CMOS-compatible channel material because of its higher intrinsic carrier mobility of hole and electron over Si.2–4) _{The beneﬁts of employing high-}_k_{gate dielectrics on} Ge include a thin interfacial layer (IL) between the high-k material and the Ge, and the possibility of hiding the imperfect properties of native oxide in capacitance scal-ing.5,6) _{This implies that there are many chances for us to}

challenge the integration of a Ge channel and high-k gate

dielectric with a negligible eﬀect on low-permittivity IL. Many studies in this area have been performed over the last decade. Until now, researchers have focused on the simple

deposition of high-k material on chemically cleaned Ge,

various substrate pre-depositional treatments, and post-deposition annealing for various ambient conditions. For example, Kamataet al.7)and Chenet al.8)reported no IL at

ZrO2/Ge and TiLaO/Ge interfaces, respectively. Sunet al.9)

noted various Ge-related defects in the electrical properties of a HfO2/Ge stack, including ﬂatband voltage (VFB) instability with large hysteresis and high leakage currents due to oxygen vacancy and interstitial sites in Ge, respectively. A

thermally-evaporated HfO2 layer, which was deposited directly on Ge

substrates, showed low leakage current characteristics and poor interface quality with low accumulation capacitance values upon N2annealing.10)Wuet al.11)and Zhanget al.12)

observed severe Ge incorporation into HfO2occurring during

thermal annealing due to a haphazard IL between the HfO2

and Ge. Chenet al.13)_{described degraded electrical} proper-ties on Ge substrates with diﬀerent high-k gate dielectrics

such as HfO2 and Al2O3 without an intentional IL after

annealing in a forming gas (FG) ambient at500C, due to

direct contact between the high-k material and the Ge.

Oshima et al.14) observed higher leakage currents in

FG-annealed devices at 370_{C than in as-grown devices when}

HfO2 was deposited directly on a chemically cleaned Ge

substrate. Cheng et al.15) _{experimentally observed that the}

out-diﬀusion of Ge during thermal treatment in NH3ambient

led to degraded leakage current characteristics. In contrast, Gao et al.16) _{demonstrated highly reliable electrical} prop-erties such as low leakage currents and excellent C-V

characteristics with an AlN IL between the HfO2 gate

dielectric and Ge substrate, rather than Ge-surface nitrida-tion, due to the high thermal stability of the AlN IL. Maeda et al.17)obtained good interfacial quality with a low interface state density (Dit) level of 1:81011cm 2eV 1 for HfO2

deposited on Ge3N4/Ge stacks. In this study, we investigated

the eﬀect of O2and FG annealing on the electrical structural

properties of Ge metal-oxide-semiconductor (MOS) devices

*_{Corresponding author, E-mail: cjchoi@chonbuk.ac.kr}

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with Pt/HfO2gate stacks, and demonstrated their comparison

with Si MOS devices. We show that O2annealing is eﬀective

in the improvement of HfO2 interfacial quality with

negligible frequency dispersion, as shown by the capaci-tance-voltage (C-V) curves of Ge MOS devices. We also show that FG-annealed Ge MOS devices exhibited degrada-tion in electrical performance (such as highDitand leakage current levels) due to the absence of an IL between the HfO2

gate dielectric and Ge substrate.

2. Experimental Procedures

MOS capacitors were fabricated on p-type Ge (100) wafers

with doping concentrations of 21018cm 3. After

remov-ing the native Ge oxide by dippremov-ing the sample in a diluted HF solution (1 : 50) for 1 min, HfO2 ﬁlms with a thickness of

6 nm were deposited on the wafers using the atomic layer deposition (ALD) process by means of sequential pulses of HfCl4and H2O sources at a wafer temperature of 300C. For

a gate electrode, 50 nm-thick Pt ﬁlms were sputter-deposited at room temperature, followed by patterning with the

dimensions of 300300mm2 _{using lift-oﬀ lithography.}

Then, post-metallization annealing was carried out at

500_{C for 30 min in O}

2 and FG (H2: 5% and N2: 95%)

environments. For comparison, Pt/HfO2 gate stacks were

formed on p-type Si (100) wafers with a doping concentration

of51015cm 3 using the same fabrication conditions. For

convenience, the MOS devices fabricated on Ge and Si wafers are hereafter referred to as ‘‘Ge devices’’ and ‘‘Si devices’’, respectively. The microstructures of the fabricated devices were examined using a ﬁeld emission transmission

electron microscope (FETEM, Tecnai G2 _{F30 S-Twin) at}

National Nanofab Center (NNFC). C-V and conductance-voltage (G-V) characteristics were measured at 100 KHz using a precision LCR meter (HP4284A). Current-voltage (I-V) characteristics were determined using a precision semiconductor parameter analyzer (Agilent 4156C).

3. Results and Discussion

Figure 1 shows the C-V and G-V characteristics of the Ge and Si devices. For both devices, the thermal treatment process led to a decrease in accumulation capacitance. However, the decrease in the accumulation capacitance of the

O2-annealed Ge-device was insigniﬁcant compared to the

O2-annealed Si-device. This result could be associated with a

relatively large increase in the thickness of the IL beneath the HfO2in Si devices, which will be described subsequently. A

noticeable bump in the C-V curves in the depletion region is clearly visible for the Ge and Si devices without thermal treatments. This could be related to HfO2interfacial quality,

such as Dit related to Si or Ge dangling bonds at the

substrate/gate dielectric interface.18)_{However, after the O}

2

annealing process, the bump in the C-V curve of the Ge device (Fig. 1(a)) almost disappeared, whereas the Si device

(Fig. 1(b)) showed a small bump. This implies that O2

annealing is not particularly eﬀective in improving the interface quality of an HfO2/Si stack. Furthermore, the

FG-annealed Ge device exhibited a strange C-V plot, showing a rapid decrease in accumulation capacitance. This could be

due to the presence of large leakage currents caused by direct

contact between the HfO2 gate dielectric and Ge substrate

without any separation, which will be discussed subsequent-ly. In contrast, the FG-annealed Si device showed a precise C-V plot without any bump in the depletion region, resulting

in an improvement in the interface quality of the HfO2/Si

stack. This was also conﬁrmed through G-V measurements

of the Ge and Si devices before and after annealing in O2

and FG environments, as shown in Figs. 1(c) and 1(d). For

both Ge and Si devices, annealing in an O2 environment

demonstrated a dramatic decrease in the maximum values of conductance nearVFB, suggesting a reduction of theDitlevel. TheDit values of O2-annealed Ge and Si devices, extracted

from the G-V characteristics at 10 kHz (not shown here) as suggested by Yanget al.,19)were measured to be1:51012

and 2:91012cm 2eV 1, respectively. The value of the Ditlevel in the O2-annealed Si devices was nearly two times

higher than that of the O2-annealed Ge devices. This implies

that O2 annealing played a more eﬀective role in the

passivation of Ge dangling bonds than in the passivation of Si dangling bonds. In meticulous, the dominant interface (Pb) centers at the HfO2/Ge stack were physically removed by O2

annealing, resulting in the reduction of the Dit level.20) _In addition, the presence of excessive diﬀused oxygen species at the SiO2/Si interface could depassivate the interface (Pbo)

centers and produced additional interface traps in the Si

devices.21,22) Moreover, we note that the FG-annealed Ge

device shows a signiﬁcant peak (see inset of Fig. 1(c)), whereas the same was disappeared in the FG-annealed Si device (Fig. 1(d)). This indicates that FG annealing is ineﬀective in the passivation of Ge dangling bonds at a gate dielectric/Ge interface caused by containing a similar negative charge on Ge dangling bonds and interstitial

hydrogen in the Ge.23) _{However, Si dangling bonds were}

passivated more eﬀectively at an HfO2/Si interface by

forming Si-H bonds during FG annealing.24) _{For example,}

it is not possible to determine theDit level in FG-annealed

Ge devices due to strange C-V behavior, whereas the Dit

value in FG-annealed Si devices was calculated to be4:1

1011_cm 2_eV 1_.

Figure 2 shows frequency dispersion in the C-V curves measured at a multiple high frequency range. We note that frequency dispersion in the accumulation region of the O2

-annealed Ge devices is negligible (Fig. 2(a)), whereas severe frequency dispersion is shown in the C-V plots of the FG-annealed Ge devices (Fig. 2(b)). In particular, thermally treated Si devices exhibited low frequency dispersion irrespective of the annealing ambient. It has been previously reported that defects in the dielectric layer and/orDitcould

be primary sources of frequency dispersion.25–27) _However,

considering that the Dit level in FG-annealed Si devices is

approximately one order of magnitude lower than that of O2

-annealed Ge devices, the imperfection of HfO2gate dielectric

material such as oxygen vacancies is believed to be a main cause of the annealing ambient dependency of frequency

dispersion in the C-V curves in present devices. Thus, O2

annealing suppresses the formation of oxygen vacancies in

the HfO2 layer due to the oxygen-enriched region during

thermal treatment. However, annealing in an FG environment

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a lack of suﬃcient oxygen in the surroundings, leading to frequency dispersion.

Figure 3 shows cross-sectional high-resolution electron microscope (HREM) images taken from the Ge and Si devices before and after thermal treatments. The thickness

of the as-deposited HfO2 ﬁlms on the Ge and Si substrates

was measured to be 6 nm (Figs. 3(a) and 3(d)). However,

the thickness of the HfO2 in Ge devices increased up to

6:5nm after the O2and FG annealing processes (Figs. 3(b)

and 3(c)). No such variations were monitored in the HfO2

thickness in the Si devices regardless of the annealing ambient (Figs. 3(e) and 3(f)). It is unclear whether there was an increase in the HfO2 thickness for the thermally-treated

Ge devices. However, this could be associated with the

formation of HfGeOx driven by signiﬁcant diﬀusion of Ge

into HfO2.28) Namely, the diﬀusion of substrate atoms into

HfO2 from the interface of the HfO2/substrate led to the

volumetric expansion of the HfO2 layer.29)Such an increase

in HfO2 thickness seems to be a main cause for the small

decrease in the accumulation capacitance value of O2

-annealed Ge devices, even for a thin IL, compared to as-deposited Ge devices. Thus, the thickness of the IL between

the HfO2 and Ge was changed by annealing in O2 and FG

environments due to the nonuniform oxidation behavior of the Ge.11,30) _{For Ge devices, thermal treatment resulted in} a reduction in the thickness of the IL. For example, the

thicknesses of the IL in as-deposited and O2-annealed Ge

devices were measured to be 0.6 and 0.4 nm, respectively. However, the IL thickness in the FG-annealed Ge device was almost negligible. Such a reduction of IL thickness in Ge devices during thermal treatment could be associated with

the easy decomposition of GeO2 into volatile GeO, and the

desorption of GeO at low temperatures (450_C).7)

Insuﬃ-cient oxygen in the vicinity during thermal treatment could be responsible for the negligible IL thickness in FG-annealed

Ge devices, implying direct contact between the HfO2 and

Ge. Moreover, despite the natural characteristics of Ge oxide, a supply of suﬃcient oxygen in the HfO2/Ge interface allows

Fig. 1 C-V characteristics of (a) Ge and (b) Si devices before and after annealing in O2 and FG environments at 500C. G-V

[image:3.595.98.502.72.500.2]

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Fig. 2 C-V curves measured at multiple frequencies for Ge devices after (a) O2and (b) FG annealing at 500C, and for Si devices after

(c) O2and (d) FG annealing at 500C.

Fig. 3 HREM images taken from Ge devices (a) before and after (b) O2and (c) FG annealing at 500C and from Si devices (d) before and

[image:4.595.95.504.76.501.2] [image:4.595.95.501.543.756.2]

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the presence of a thin IL in the O2-annealed Ge device, which

screens the HfO2 from the Ge substrate. In contrast, Si

devices show pronounced ILs with thickness of 1.0, 2.1,

and 1.8 nm for as-deposited, O2-annealed, and FG-annealed

devices, respectively. It has been reported that upon

annealing at temperatures above780C, SiO2 decomposes

followed by transformation into volatile SiO.31)This implies that for Si devices, annealing at 500_{C leads to enhanced IL} thickness.

Figure 4 shows I-V characteristics of Ge and Si devices

after O2 and FG annealing. The open and closed symbols

represent Ge and Si devices, respectively. For the O2

-annealed Ge device, the leakage current density measured

at a gate bias of 1 V was found to be 310 8_Acm 2_.

However, we note that the FG-annealed Ge device showed severely degraded I-V characteristics. For example, the leakage current density of the FG-annealed Ge device

increased signiﬁcantly, up to 0:9101Acm 2 at a gate

bias of 1 V. Such an extremely high leakage current density could be associated with direct contact between the HfO2and

Ge substrate as shown in Fig. 3(c). Similar behavior was

observed by Abe et al.,32) who showed that dipoles at the

HfO2/Si interface caused by direct contact between HfO2

and Si led to high leakage currents (on the order of10 1_to

100_Acm 2_{). Thus, the existence of an IL between the HfO}

2

and substrate is required to reliably attain low leakage currents. This is clearly conﬁrmed by the I-V characteristics

of the Si devices with thermal treatments in O2 and FG

environments. For example, the leakage current densities of O2and FG-annealed Si devices with relatively thick ILs were

measured to be 310 9 _and ₄₁₀ 9_Acm 2_,

respec-tively.

4. Conclusion

We investigated the eﬀects of the O2 and FG annealing

ambient on the structural and electrical properties of Ge

devices, and showed a comparison with Si devices. The reduction in the accumulation capacitance of O2-annealed Ge

devices was relatively insigniﬁcant when compared to O2

-annealed Si devices due to the insigniﬁcant variations in IL thickness at the HfO2/Ge stack. The interface quality of O2

-annealed Ge devices was improved with a possible passiva-tion of the interface centers at the HfO2/Ge stack. On the

other hand, FG-annealed Ge devices exhibited the severe

degradation of HfO2 interface quality due to the similar

charge on Ge dangling bonds and interstitial hydrogen in Ge.

O2-annealed Ge devices showed relatively insigniﬁcant

frequency dispersion compared to O2-annealed and

FG-annealed Si devices. This could be attributed in part to the reduction ofDit, and to the apparent suppression of oxygen

vacancies in the HfO2 layer. A negligible IL between the

HfO2and Ge led to the degradation of electrical performance

in FG-annealed Ge devices caused by the formation of

dipoles at the HfO2/Ge interface. However, O2 annealing

produced low leakage currents, which is comparable to the thermally-treated Si devices. Therefore, we suggest that O2

annealing produces reliable electrical properties such as negligible frequency dispersion, lowDit, and an acceptable leakage current level without an intentional interfacial layer on the Ge substrate.

Acknowledgement

This work was ﬁnancially supported by the ‘‘Support Program for the Advancement of National Research Facili-ties and Equipments (NFEC-2007-11-048017)’’ of the Min-istry of Education, Science and Technology, Republic of Korea, and was partially supported by the ‘‘IT R&D program (KI002083, Next-Generation Substrate Technology for High Performance Semiconductor Devices)’’ of the Ministry of Knowledge Economy, Republic of Korea.

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