UNIT – II
Introduction to Computer Organization
The instruction set architecture describes the instructions which are processed by the computer, but it is not described about how these instructions are processed. We know that, any simple computer has three primary components, the central processing unit (CPU)-which performs may operations and control the each and every component of the system.
The memory sub system which is used to store the programs along with the data being processed by the CPU. The input/output subsystem, which provides the interaction between the CPU and outside world.
Basic Computer Organization:
We know that, the system is an orderly group of interconnected components according to a plan to achieve an objective. So the computer may have several components each of which performs a specific function.
To function the computer successfully, all of its components are properly interconnect to each other. In any computer there are three main components those are;
1. Central Processing Unit (CPU).
2. Memory subsystem.
3. Input/output subsystem.
To interconnect all the components within the system, we use the system bus (common bus). The bus is a set of wires to which all the system components are connected. The buses use less space on circuit board and require less power for its working. It also requires fewer pins on the chip. So buses provide more efficient communication rather than direct connection between the devices. The following diagram shows the interconnection of components with system bus.
The set of wires in the system bus is again classified into three categories;
1. Address bus.
2. Data bus.
3. Control bus.
We know that, the processor can recognize each and every device which is attached to the system by a unique number, it is also known as device address. If the processor is willing to communicate any device, then it places the address of the device on the address bus. For example the processor is wishing to read/write the data or instructions from the memory, and then it places the addresses of the memory locations on the address bus. Similarly to access the data from the key board, the processor places the address of the keyboard on the address bus.
The devices attached to the system have continuously monitored the address bus to determine whether it is the device accessed by the CPU. If the device recognizes its own address then it is activated. The address bus is always unidirectional, it means the CPU always places the address on the address bus, it never receives (reads) the address from the address bus.
The data is transferred through data bus, when the CPU fetches (read) data from memory, first it keep the address of the memory location on address bus. The memory controller attached to the memory unit interprets the address and outputs the data on the data bus. Suppose the CPU writes the data into the memory, the CPU first keep the address on the address bus and then puts the data onto the data bus. The memory controller reads the address and stores the data at appropriate locations.
The control bus is a collection of individual control signals, these signals represents what the operation to be performed by the devices as well as CPU. When the CPU accessing the memory it uses two control signals such as Read and Write.
A computer system may have the number of buses in addition to the common bus, these buses may be I/O bus, local bus etc.
Instruction cycles: The instruction cycle is a procedure processor goes through process an instruction. So the instruction being executed in number of phases such as, Fetch, Decode, Fetch the operands, Execute,
Return the results. The phases of instruction may be changed depending on the context.
Initially the processor Fetches or reads the instruction from the memory, by placing the address of the instruction on the address bus.
Now the memory controller takes this address and decodes it to access the desired memory location. To perform these operations the microprocessor allows sufficient time for memory. Then the processor places the READ signal on the control bus. This signal specifies that the processor is ready to accept the data from the memory of I/O device. Again the memory controller understands the read signal, and then places the instruction on the data bus, then the processor stores this instruction in one of its registers.
Next, the processor decodes the instruction. We know that each instruction may specify various sequences of operations to execute that instruction. When processor decodes the instruction, it will determine that what the sequences of operations to be performed.
Finally the processor executes the instruction, the sequence of operations to execute the instruction varies from instruction to instruction. The execution process may read data from memory or I/O and write the data to the memory or I/O. the following diagram represent the timing of read and write operations to and from the memory.
The I/O read and write operations are similar to the memory read and write operations but some processors may use same set of instructions to communicate with both memory and I/O is called the memory mapped I/O. Some other processors may use different instructions known as isolated I/O.
CPU Organization:
We know that, the CPU controls and coordinate each and every operation with in the system. Generally it fetches instructions from memory by supplying the address and control signals to access the data.
Decode the instruction and controls the execution process. It also supplies the address, data, and control signals required by the memory and I/O devices to execute the instruction. The CPU has three important components such as, the registers, Control unit and Arithmetic and logic unit (ALU). The following diagram shows the CPU internal organization.
The register section has set of registers and common communication mechanism. The system address and data buses are directly connected to the register section to facilitate the programmer to for direct accessing. We know that the processor registers are classified into two grups one is general purpose registers (GPR)-which stores instructions, data and temporary results and another one is special purpose registers-which specify the condition to perform an operation. The data and control buses provide the interfacing between registers, control unit and ALU of the CPU.
Let us consider when the CPU is willing to fetch an instruction from the memory, first of all it places the address of the instruction on the address bus, reads from the one of the processor register Program Counter, which always have the address of the next instruction to be executed. At the end of the instruction fetch the CPU reads the instruction from the data bus, then stores it into internal register called as instruction register.
The arithmetic and logic unit (ALU) performs all arithmetic and logic operations. To perform these operations, the ALU receives the data from the processor internal registers and then return the result to the registers again after completing the operation. The ALU performs these operations
with clock cycle speed. It means one instruction is executed per one clock cycle.
The control unit controls the each and every operation performed with the system by generating the control signals. Such as load the data into the registers, increment the contents of the registers, clear the data etc. To generate the control signals the ALU may also receives the data from the processor registers, this data may be instruction opcode or some flag bits.
The control unit may generate the control signals to the system bus also, such as READ, WRITE and IO/M’. The control unit causes the CPU and other devices to perform the operations to correctly process the instructions.
Memory Subsystem Organization and Interfacing:
We know that the computer has two types of memories, one is the Read Only Memory (ROM) and another one is the Random Access Memory (RAM).
Read Only Memory: The ROM chips are designed for the applications in which data is only read. These chips are programmed with data by an external unit before they are added to the computer. Once the data is loaded into the ROM, it is not possible to change and data is permanently stored in the ROM even if the power is off. There are several types of ROM chips are available in the market.
A masked ROM or simply ROM is programmed with data when the chip is fabricated. These ROM chips are useful in consumer appliances, once the ROM is installed, the data will not be changed.
A PROM is a programmable ROM; this ROM is programmed by an expert PROM programmer. The PROM has a series of internal connections like fuses. This ROM is programmed by burning these fuses, and data is stored in standard manner. Once the fuses are blown those cannot be restored. It means the PROM is only programmed once.
An EPROM is an erasable ROM, this ROM is programmed in similar manner like PROM but it is possible to erase and reprogram this ROM.
The EPROM is fabricated with leaky capacitors. These capacitors cause to store the correct value of data in the memory. The contents of EPROM are erased by placing them under the ultraviolet light, which causes the
capacitors to their charge. One of the drawbacks in EPROM is suppose we put it in ultraviolet light all the data within the ROM is erased.
Another kind of ROM is EEPROM, Electronically Erasable PROM. It works as EPROM but the contents are erased and reprogrammed electronically. One of the important feature of EEPROM is it erases only the unnecessary data from the memory locations. One common use of EEPROM is Basic Input Output System (BIOS). A special type of EEPROM is called flash EEPROM which electronically erase data in block wise rather than location wise.
Random Access Memory: It is also called as a read/write memory in which we can store and change the data. This memory also called X MB memory. The data in RAM was lost when the power off. To access the data from any location of RAM chip, the processor takes the unique interval of time. We can classify the RAM depending on how they maintain the data.
There are two types of RAMs one is Dynamic RAM, or DRAM and another one is Static RAM or SRAM.
The Dynamic RAMs are fabricated with leaky capacitors, initially these capacitors are fully charged to represent the maximum value. As the time being the charge is slowly a leak and goes too low to represent the valid data. Before the total discharge we refresh the capacitors. DRAMS are used in personal computers (PCs).
The static RAM or SRAM is like a register, once the contents are written into SRAM they stay valid, it does not require refreshing. The static RAMs are faster than DRAMs, but they are more expensive.
Internal Chip Organization: The internal organizations of the RAM and ROM chips are similar. The memory chips are organized either in linear fashion or two- dimensional fashion. Here let we design an 8X2 ROM chip with the help of the tri-state buffers. The following is the diagram.
The ROM chip consists of a eight memory locations each location capacity is two bits.
To construct these memory locations we use 16 tri-state buffers. Each location (row) of
the memory is connected to the 3X8 decoder. This decode has three input address lines, labeled as (A2,A1,A0) and one control signal chip enable (CE). By changing the values of the address lines the decoder is used to select one of the eight locations of the memory when chip enabled is set to 1. Otherwise the circuit is not working. The outputs from the tri-state buffers are connected to the two output buffers in bitwise manner, representing two bits (D1 and D0). The chip enable signal and output enable signals are ended and connected to the output buffers. When CE and OE bits are 1, the 8X2 memory circuit is producing the output.
To organize the memory in this fashion is complex, when number of locations of the memory gradually increased. So to avoid the increase in size of design logic, we follow the two dimensional organization. Let us consider we design the same
8X2 ROM chip in two dimensional organization. The following is the diagram.
Here also we use the 16 tri-state buffers which are arranged in four rows, each row have four buffers. These four buffers in a row
represent the two data locations (high order and low order). These four rows are connected to the one 2X4 decodes which has two address input lines A2 and A0. By using these address lines this decoder is used to select one of the four rows from the memory chip.
We use one more 1X2 decoder which has the input address line A0 and is used to select one of the two locations in a row. The both decoders are connected to the chip enable signal (CE).
The outputs from the tri-state buffers are connected to the four output buffers in column wise and two signals from the 1X2 decoder are connected to the output buffers. Two control signals CE and OE are ended and connected to the output buffers (D1 and D0).
Here A0 address input line is deterministic output enable logic. The above
A2 A1 Row
selected
A0 Locaion Selected
0 0 First 0 First
0 1 Second 0 Third
1 0 Third 0 Fifth
1 1 Fourth 0 Seventh
0 0 First 1 second
0 1 Second 1 fourth
1 0 Third 1 sixth
1 1 Fourth 1 Eighth
table shows the functional performance of the 8X2 memory chip in two- dimensional organization.
Memory Subsystem Configuration: It is very easy to setup a memory unit with a single chip by simply adding the chip to the common bus. But the single chip is not sufficient to store the large volumes of data and instructions, for this reason the memory systems are fabricated with more than one chip.
To combine the more than one memory chip, we combine the corresponding address lines and control lines of the chips and the data lines are connected to the data bus. Let us consider we try to combine two 8X2 memory chips to form a one 8X4 memory chip to store the more bits per location. The following is the diagram.
Here each 8X2 chip has three address input lines to select one of the location and two control signals and two output lines. The address and control signals of both of the chips are combined and four data output lines (D3 to D0) are connected to the data bus.
When to access the data from the memory unit, the CPU places the address on the address lines, the both chips reads the address bits A2, A1, A0 and perform their internal decoding. If CE and OE signal are set (enabled), then chips output their data on the four bits of data bus.
The following is the diagram shows how to construct a 16X2 memory system by using two 8X2 memory chips. Here the upper chip has eight memory locations from 0 to 7 addressed by 0000 to 0111 and the lower chip has remaining eight memory locations from 8 to 15 addressed by 1000 to 1111. The upper chip is enabled when A3=0 and lower chip is enabled when A3=1. It means the address input line A3 is determining from which chip is in active
state. The outputs from the both chips are connected to D1 and Do lines of the data bus. This configuration is known as higher order interleaving.
It is also possible to construct the same memory system in low order interleaving fashion. In low order interleaving configuration the A0 address input line determining which memory chip is active. When A0=0 the upper chip is enabled otherwise the lower chip is enabled.
The final step in the memory module design is to develop the CE and OE input logic. The diagram shows the design of control logic. The chip enable signal (CE) is developed with the unused bits of address lines. it also specify whether the chip follows isolated I/O or memory mapped I/O. The output enable signal is generally either RD or RD’ generated by the CPU.
Multibyte Data Organization: We know normally the memory is organized in byte wise manner. It means the CPU assigns the address for each byte in memory. But when we stores the data of any type sometimes it may needs more than one byte in memory. In such a situations it is necessary for every CPU to specify the order of data stored in the memory locations.
There are two commonly used organizations for multibyte data; one is big-endian method and another one is little-endian method. In big-endian format the most significant byte of the data stored in the memory location address X and remaining bytes of data stored in the locations X+1 and soon. In little-endian method the least significant byte of data stored in memory location address X and remaining bytes of data stored in locations X+1 and soon. For example consider the data 01020304H stored in both manners starting from the memory address 100H.
When we organize the data in two methods, there was a problem in transferring data between computers with different endian organizations.
To resolve the problem some external programs are available to convert
the data files from one format to another format. One more issue we should consider in multibyte organization is alignment of data. Generally the CPU reads more than one byte at a time from the memory. To specify the alignment of data in memory, microprocessors follow some specific methods for example some processors store the multibyte data at memory locations whose address is divisible by four and then four bytes are accessed at a time.
I/O Subsystem Organization and Interfacing:
We know that the CPU treats the memory as the homogeneous, because the even if the memory is made up integrating of several memory chips the total memory is treated as a single unit. The operations performed on the memory (READ & WRITE) is the same in any case. But the organization and interfacing of the I/O devices may vary from device to device because their functionalities are different.
We know that each and every I/O device interface with the CPU through the common bus. Here each device has a separate circuitry to organize its operations as well as control the interface with the common bus. This is known as device controller or device driver. To establish a effective interface with the I/O devices the CPU assigns unique address to each and every I/O device. The following diagram shows the generic interface circuitry for the input device. To design the input interface circuitry we use tri-state buffers. The data from the input device is goes to the tri-state buffers. The tri-state buffers in the input interface facilitate not more than one input device is allowed to write the data on to the data bus. When the values of address and control buses are correct, then the enable logic is high. Now the tri-state buffers are active and transfer the data to the data bus. Suppose the enable logic is not active then the tri-state buffers not transfer the data to the data bus.
The key component in the input interface design is enable logic. The enable logic gets the correct address from the address bus (because each I/O device is identified by a unique address) and control signal from the control bus. For the input device the control signal may be the READ signal and IO/M’ signal to specify whether the input device may follow
isolated I/O or memory mapped I/O. The following diagram shows the design of control logic for the input device. Here the circuit have 8-bit address and RD and IO/M’ control signals.
The low order address bits of the address lines are (A3 to A0) 0000 and remaining bits are (A7 to A4) set to 1111. The input interface design follows the combinational logic.
The designing of the output circuitry is a bit different from the input interface design. Here we use register in place of tri-state buffers, because the data from the CPU may receive by many output devices at a time (number of output devices are allowed to read the data from the data bus).
Here the load logic plays an important role in the design of output interface. When it receives correct address from the address bus and control signals from the control bus enables the output controller to load the data from the data bus to the register. The following diagram shows
generic output interface circuit.
Here the control signals are write signal (WR) and IO/M’ signal. The output interfacing circuit also connected to the 8- bit address lines, out of the four lower order bits (A3 to A0) are set to 0 and remaining bits (A7 to A4) are set to 1.
The following diagram shows the design of load logic in output interface circuit.
Some of the devices may perform both input and output functionality. For example hard disk of the computer performs both
read and writes (input and output) operations. Such a device require combined interface which perform both input and output. The following diagram shows the bidirectional input, output device.
One of the major problems during the input, output organization is speed mismatch between the CPU and I/O devices. We know that the CPU working with much more speed than the I/O devices. It leads to the timing problem when I/O devices interface with the CPU. There are several mechanisms are proposed to solve the timing problem. Let us consider the following are some of them.
Suppose the CPU wants to read data from the disk, it issues appropriate address and control signals to the device. Now the device takes few milliseconds to fetch the data, during the mean time the CPU reads the invalid data from the device and performs the operations. It leads to the wrong processing of data.
To avoid the above situation, when CPU interacts with the I/O device, first it places the READY signal on the control bus and then the address of the device on the address bus. Now the device takes few milliseconds to interpret the control signal and fetch the data. Until that the CPU is in waiting sate. This process wastes the CPU time.
To avoid the CPU waiting, we introduce the interrupt method. It is the extension of waiting process. Here the CPU issues the control signals and address to the device and then goes to execute another program. When the data is ready at the device, the device controller generates an interrupt signal to the CPU. Now CPU, realizes that data is ready at the devices and temporarily stops the current work and reads the data from the device.
The interrupt generation method needs some additional circuitry, all the problems occur due to all data transfer happen through CPU. In latest method we avoid the CPU in the data transfers and able to transfer the data and instructions to and from memory and I/O devices. This method is known as Direct Memory Access (DMA).
A Relatively Simple Computer:
Here we are examining a sample computer by interconnecting all necessary components. The sample system is similar to the real world system in all aspects. For the designing of the sample system, let we consider, it has 8K of ROM whose addresses are started with 0, followed by 8K of RAM. It also has a bidirectional I/O port with the address 8000H and it follows the memory mapped mechanism to access the data either
from memory or form the I/O devices. The basic components of the system (CPU, Memory, and I/O) are interconnected by a common bus. The following diagram shows interconnection structure of sample CPU.
Here the CPU has 16-bit address lines, which specify address of memory locations and I/O devices. These address lines are labeled as A15 to A0, the CPU is also have 8-bit data lines to transfer the data between CPU and Memory, I/O devices, these data lines are labeled as D7 to D0.
The CPU may also have two control signals READ and WRITE. We specify that the sample CPU follows the memory mapped I/O so it does not require IO/M’ control signal.
Let we analyze the memory system, to simplify the design of the sample system we consider there is only one ROM chip and one RAM chip. Here the ROM capacity is 8K, whose addresses in the range 0 to 8K-1 (0000 0000 0000 0000 to 0001 1111 1111 1111 in binary). To access the memory chip the CPU must specify the address used by the chip. Here the processor may use 13 address lines (A1 to A0) to access 8K of memory.
The remaining three lines are (A15, A14, A13) used to specify the control logic (CE) to select one of the memory chips. To enable the ROM chip and to access its contents the three most significant bits of address lines are 000. The ROM chip also have output enable signal (OE) which is connected to the READ control line. When both of the signals OE and CE are set then only the contents of the ROM is able to access.
The RAM chip also has 8K capacity, it is a read and writable memory. It has two control signals READ and WRITE, these two control signals specify whether to read the data from RAM or to write the data into the RAM. These two signals are used in combined with chip enable signal (CE). Out of the two memory chips (ROM & RAM) only one chip is enabled at a time. The following diagram shows the final design of the sample CPU.
Now we analyze the I/O sub system, it has connected to the I/O port whose address is 8000H and it also a bidirectional. The CPU specifies the address and control signals to enable the input and output interface. The I/O sub system of sample CPU uses register to store the data which was received from the CPU and then transfer to the output device. It uses tri- state buffers in the input interface to transfer the data from input unit to the CPU. The I/O subsystem follows the memory mapped I/O so it does not need IO/M’ control signal.
An 8085 Based Computer:
The 8085 microprocessor has three main chips, one is actual 8085 processor, second one is 8755A ROM chip and third one is 8156 RAM chip. To interface with RAM and ROM chips and access the data, the 8085 uses eight (8) multiplexed pins. It means the same pins are used to represent the address as well as to transfer the data to and from the memory.
These pins are generally representing the first eight low order address bits, labeled as AD7 to AD0. But these eight bits are used to represent only the half of the address. We know that it is not possible to access the memory without full address, for this purpose the 8085 uses address latch latch enable signal (ALE). This signal is set to 1 when first clock cycle of memory access then it loads the low order memory address bits into the load register; in next clock cycle this ALE signal is set to 0, to transfer the data from the memory. The diagram shows the multiplexing and demultiplexing of address pins in 8085.
The 8755A chip has 2K of EPROM; its address range is 0 to 2K-1. It has two I/O ports, at addresses 00H and 01H. This chip has two enable signals, one is CE this is always set to logic 1 and another one is PROG/CE’, which is in active when clock is low. This ROM chip is activated when A11 =0. The ROM is designed in flodback method; this is a common design practice in smaller systems to reduce the logic to design.
The following diagram shows the minimal 8085 processor.
The 8755A chip has two I/O ports those are directly connected to the Data Direction Register (DDR). It determines which port is act as an input port and which port is act as an output port.
The 8156 RAM chip in 8085 processor contains 256 bytes and two 8-bit I/O ports, one 6-bit I/O port. The chip is enabling when A12 bit is set to 1.
Here we use the commands to transfer the data between the RAM and 8085 processor instead of DDR. But here we use the status register which represents the status of the ports to the CPU. We know that the 8085 uses the isolated memory organization, so the I/O devices and memory locations have the same addresses.
This 8085 minimal system design is useful to control the small electronic appliances.
UNIT-II PROBLEMS
1. Show the internal linear configuration of 32X2 memory chip.
2. Show the internal two-dimensional configuration of 32X2 memory chip.
3. Show the internal organization of 16X4 memory chip that minimizes the total size of address decoders.
4. Show the internal organization of 16X4 memory chip; make the array of memory cells as square as possible.
5. Design a 16X4 memory system with high order interleaving using 8X2 memory chips for a computer with 8-bit address bus.
6. Design 32X8 memory sub system with high-order interleaving using 16X2 memory chips for a computer system with 8-bit address bus.
7. Design 16X4 memory sub system with low-order interleaving using 8X2 memory chips for a computer system with 8-bit address bus.
8. Design 32X8 memory sub system with low-order interleaving using 16X2 memory chips for a computer system with 8-bit address bus.
9. Design 32X8 memory sub system with split interleaving (one high-order bit and one low-order bit are interleaved) using 8X4 memory chips for a computer system with 8-bit address bus.
10. Assumes the memory system is connected to CPU with 8-bit address bus. Show the logic to generate the CE and OE signals for the following memory
addresses.
a) 0 to 15 b) 16 to 31 c) 240 to 255
11. Show how the following values stored in memory in big-endian and little-endian formats. Consider each value starts at address 22H.
a) 12345678H b) 0927H c) 5551212H
12.
12. Design an interface for input device which has binary address1010 1010 it computer system as isolated I/O.
13. Design an interface for input device which has binary address1010 1010 it computer system as memory mapped I/O.
Same as the above problem but remove the IO/M’ signal.
14. Design an interface for output device which has binary address1010 1010 it computer system as isolated I/O.
15. Design an interface for output device which has binary address1010 1010 it computer system as memory mapped I/O.
Same as the above problem but remove the IO/M’ signal.
16. Design an interface bidirectional input/output device that has binary address 1000 0001. Computer system uses isolated I/O.
