High-Speed Printed Circuit

(1)

Th W ld L d i Hi h P f Si l P i S l ti The World Leader in High Performance Signal Processing Solutions

A Practical Guide to A Practical Guide to

High-Speed Printed Circuit Board Layout

Board Layout

John Ardizzoni Dennis Falls

Analog Devices Avnet Electronics Marketing

(2)

Agenda g

Overview

Schematic

Location, location, location

Trust no one

Power supply bypassing

Parasitics

Ground and power planes

Packaging

RF Signal routing and shielding g g g

Checking the layout

Summary

(3)

Overview

PCB layout is one of the last steps in the design process and y p g p often one of the most critical

High-speed circuit performance is heavily dependant on layouty

A high-performance design can be rendered useless due to a poor or sloppy layout

Today’s presentation will help:

Today s presentation will help:

zImprove the layout process

zEnsure expected circuit performance is achieved

zReduce design time

zLower cost

zLower stress for you and the PCB designer

(4)

Schematic

(5)

Schematic

The strength of any structure (including PCB’s) is only as g y ( g ) y good as the foundation on which it built upon!

A good layout starts with a good Schematic!

Schematic flow and content

Include as much information as you can

What should you include?

(6)

Items to Include on a Schematic

Notes

Component tolerances and case sizes

Part numbers (internal/external/alternative)

Board stack up

T t li t d

Tests or alignment procedures

Power dissipation

Controlled impedance and line matching

Component de rating

Component de-rating

Thermal requirements

Keep outs

Mechanical considerations

Critical component placement

Warning flags

What ever else you can think of!y

(7)

Schematic

40 MHz

C1 0.1uF

U1

+5V R6 301 S1

C4 2.2uF +5V

40 MHz OSC Out

Must be right at op amp supply

pins Put C4 and C7 on

back of board right under the power supply pin.

Run 40MHz traces on bottom

Place this cap right at pin 14 to digital ground

+

R3

562 ADA4860-

1 -

+ R4

210

C5 0.01uF

R5 562

C2 C3

C6 0.01uF

C7 U2

VIN

VOUT

R2 50

R7 50 of the board ensure signal

trace is the same length 40 MHz

OSC Out

R1 1K

Linear Regulator

Temperature -5V

SAT SAT C7

2.2uF

U3 D1 U4

1N4148

Must be right at op amp supply

pins

+5 V +5V 50

FREQUENCY ADJUST

1.0 C2=C3, use these 2 capacitors to adjust the -3dB BW

D ti T bl

+

See critical component placement drawing for location

AD590

ADP667 Temperature

Sensor

+12V +5

V

VOUT

Linear Regulator

-12V -5V

+ +

U5 8

D2 1N4148

C8 10uF Case

size 1210

C9 0.01

uF

C11 0.1uF

C12 10uF Case

size 1210

C13

10uf C16

-5V V

+5V

R8 1K

1K

Derating Table

R1 R2 R3 C1 C2 C3 U1 U2

VALUE 1

2 3 4 5 6 7 8

62mW 10mW ITEM REF DES RATING ACTUAL

+ 10uf +

Case size

1210 C14

0.1uF

C15 0.1uF

10uF Case size

1210

2.0 All Resistors in ohms unless noted otherwise.

3.0 All capacitors in pF unless noted otherwise.

6 0 U1 SOIC-14 U2 SOT-23-6 U3 SOIC-8 U4 SOIC-8 ^0.062"

Signal 1 Analog Ground 1

Digital Ground Power plane

A l G d 2

BOARD STACK UP 1.0 All resistors and capacitors are 0603 case size unless noted otherwise.

4.0 Run analog traces on Signal 1 layer, run digital traces on Signal 2 layer NOTES:

5.0 Remove ground plane on all layers under the mounting pins of U2

6.0 U1 SOIC 14, U2 SOT 23 6, U3, SOIC 8, U4 SOIC 8 Analog Ground 2 Signal 2

(8)

Location, location, location!

(9)

Location, Location, Location , ,

Just as in real estate location is everything!

Input/output and power connections are typically defined…Everything else is undefined

z

Critical component placement

z

Signal routing

z

Circuit and component proximity

z

Circuit and component proximity

(10)

Trust No One

(11)

Trust No One

If you’re doing your own y g y layout, that’s one thing.

If you’re not ….

(12)

Trust No One

If you’re doing your own y g y layout, that’s one thing.

If you’re not ….

zDon’t assume the CAD group isDon t assume the CAD group is going to read your mind and get it right!

(13)

Trust No One

If you’re doing your own y g y layout, that’s one thing.

If you’re not ….

zIn the end you’re responsible ffor making it work!

(14)

Trust No One

If you’re doing your own y g y layout, that’s one thing.

If you’re not ….

zYou’re responsible for making it work!

When working with the CAD

Group

(15)

Trust No One

If you’re doing your own y g y layout, that’s one thing.

If you’re not ….

When working with the CAD Group

zMake sure you and the designer are on the same page

(16)

Trust No One

If you’re doing your own y g y layout, that’s one thing.

If you’re not ….

When working with the CAD Group

zBrief circuit explanation

(17)

Trust No One

If you’re doing your own y g y layout, that’s one thing.

If you’re not ….

When working with the CAD Group

C iti l t l t

zCritical component placement

(18)

Trust No One

If you’re doing your own layout, that’s one thing.

If you’re not ….

zDon’t assume the CAD group is going to read your mind and get going to read your mind and get it right!

When working with the CAD Group

are on the same page

zCritical component placement

zInput/Output connections

(19)

Trust No One

If you’re doing your own layout, th t’ thi

that’s one thing.

If you’re not ….

z Don’t assume the CAD group is going to read your mind and get it

g g y g

right!

z You’re responsible for making it work!

When working with the CAD

When working with the CAD Group

z Make sure you and the designer are on the same page

z Brief circuit explanation

z Critical component placement

z Input/Output connections

z Board outline drawing and stack up

(20)

Trust No One

If you’re doing your own layout, that’s one thing

that’s one thing.

If you’re not ….

z Don’t assume the CAD group is going to read your mind and get it

i ht!

right!

z You’re responsible for making it work!

When working with the CAD Group

z Make sure you and the designer are on the same page

z Brief circuit explanation

z Critical component placementp p

z Input/Output connections

z Board outline, stack up

z Tell them to call you if they have a question!

question!

(21)

Power Supply Bypassing

(22)

Power Supply Bypassing pp y yp g

Bypassing is essential to yp g high speed circuit

performance

(23)

Power Supply Bypassing pp y yp g

Bypassing is essential to yp g high speed circuit

performance

Capacitors right at power p g p

supply pins

(24)

Power Supply Bypassing pp y yp g

Bypassing is essential to yp g high speed circuit

performance

Capacitors right at power p g p supply pins

zCapacitors provide low AC impedance to ground

zProvide local charge storage for fast rising/falling edges

(25)

Power Supply Bypassing pp y yp g

Bypassing is essential to yp g high speed circuit

performance

Capacitors right at power

^IC

+V_S L1

p g p

1µH

supply pins

C1 0.1µF

Keep trace lengths short

EQUIVALENT DECOUPLED POWER LINE CIRCUIT RESONATES AT:

f = 1 2π^√ _LC

f = 500kHz f = 500kHz

(26)

Power Supply Bypassing pp y yp g

Bypassing is essential to yp g high speed circuit

performance

Capacitors right at power p g p supply pins

Keep trace lengths short

(27)

Power Supply Bypassing pp y yp g

Bypassing is essential to yp g high speed circuit

performance

Capacitors right at power p g p supply pins

Keep trace lengths short

Close to load return

zHelps minimize transient currents in the ground plane

(28)

Power Supply Bypassing pp y yp g

Bypassing is essential to high speed circuit

performance

Capacitors right at power supply pins

supply pins

zProvide local charge storage g g for fast rising/falling edges

Keep trace lengths short

Close to load return

zHelps minimize transient currents in the ground plane

Values

Individual circuit performance

zIndividual circuit performance

(29)

Power Supply Bypassing pp y yp g

Bypassing is essential to high speed circuit

performance

Capacitors right at power supply pins

supply pins

z Capacitors provide low AC impedance to ground

z Provide local charge storage for fast rising/falling edges

fast rising/falling edges

Keep trace lengths short

Close to load return

z Helps minimize transient currents

z Helps minimize transient currents in the ground plane

Values

z Individual circuit performance

z Maintains low AC impedance

(30)

Power Supply Bypassing pp y yp g

Bypassing is essential to high speed circuit

high speed circuit performance

Capacitors right at power supply pins

z Capacitors provide low AC impedance to ground

Keep trace lengths short

Close to load return

V l

Values

z Multiple resonancesp

(31)

Power Supply Bypassing pp y yp g

Bypassing is essential to high d i it f

speed circuit performance

Capacitors right at power supply pins

z Capacitors provide low

z Capacitors provide low impedance AC return

Keep trace lengths short

Close to load return

V l

Values

z Multiple resonances

Ferrite beads

(32)

Parasitics

(33)

Parasitics

Parasite – An organism that grows, feeds, and is sheltered on

g g , , or in a different organism while contributing nothing to the survival of its host.

Parasitics in high-speed PCB’s, can destroy circuit performance!

(34)

Parasitics

PCB parasites take the form of undesired capacitors, inductors and resistors embedded within the PCB

inductors and resistors embedded within the PCB

Parasitics are extremely difficult to remove from a PCB

Prevention is the best method to minimize parasitics

(35)

Trace/Pad Capacitance p

A d

C = kA C d

3 . 11

K = relative dielectric constant K = relative dielectric constant

A = area in cm²

d = spacing between plates in cm

(36)

Trace/Pad Capacitance p

A d Example: Pad of SOIC

L = 0.2cm W = 0.063cm

kA

K= 4.7

A = 0.0126cm²

d C kA

3 .

=11

K = relative dielectric constant

d = 0.073cm C = 0.072pF K = relative dielectric constant

A = area in cm²

(37)

Trace/Pad Capacitance p

Example: Pad of SOIC L = 0 2cm W = 0 063cm A d

L = 0.2cm W = 0.063cm K= 4.7

A = 0.0126cm²

kA

A 0.0126cm d = 0.073cm C = 0.072pF

d C kA

3 .

=11

K = relative dielectric constant _C

p

K = relative dielectric constant A = area in cm²

Reduce Capacitance

1) Increase board thickness or layers 2) Reduce trace/pad area 3) Remove ground plane

(38)

Approximate Trace Inductance pp

All dimensions are in mm

(39)

Approximate Trace Inductance pp

Example

L= 25.4mm W = .25mm

H = .035mm (1oz copper) Strip Inductance = 28.8nH At 10MH Z 1 86 Ω a 3 6% error At 10MHz Z_L = 1.86 Ω a 3.6% error

in a 50Ω system

(40)

Approximate Trace Inductance pp

Example

Minimize Inductance L= 2.54cm =25.4mm

W = .25mm 1) Use Ground plane 2) Keep length short (halving

the length reduces H = .035mm (1oz copper)

Strip Inductance = 28.8nH At 10MH Z 1 86 Ω a 3 6% error

the length reduces inductance by 44%) 3) Doubling width only

reduces inductance by At 10MHz Z_L = 1.86 Ω a 3.6% error reduces inductance by

(41)

Via Parasitics

Via Inductance Via Capacitance

⎤

⎡ ⎛ 4h⎞ C ≈ ⁰^.⁵⁵ε^r^TD¹ _pF

L = inductance of the via, nH

D₂ = diameter of clearance hole in the ground plane, cm

D di t f d di i

⎥⎦nH

⎢⎣ ⎤

⎡ ⎟ +

⎠

⎜ ⎞

⎝

≈ ⎛ 4 1

ln

2 d

h h

L 2 1

1

D C D ^r

≈ − ^pF

H = length of via, cm D = diameter of via, cm

D₁= diameter of pad surrounding via, cm T = thickness of printed circuit board, cm

= relative electric permeability of circuit board material

C = parasitic via capacitance, pF

εr

Given:

H= 0.157 cm thick board, D= 0.041 cm

C parasitic via capacitance, pF

Given:

T = 0.157cm, D 0 071 L ~ 1.2nh

D₁=0.071cm D₂ = 0.127

C ~ 0.51pf

(42)

Via Cross Section

D T&H

D₂ T&H

D

D₁ D

(43)

Capacitor Parasitic Model p

R_P R_S L

r

C

C = Capacitor R_DA C_DA

R_P = insulation resistance

R_S = equivalent series resistance (ESR)

L = series inductance of the leads and plates R_DA = dielectric absorption

R_DA = dielectric absorption C_DA = dielectric absorption

(44)

Resistor Parasitic Model

C L

C_P L

R

R = Resistor

C_P = Parallel capacitance

L= equivalent series inductance (ESL)

R

L= equivalent series inductance (ESL)

(45)

Low Frequency Op Amp Schematic q y p p

(46)

High Speed Op Amp g p p p

Schematic

(47)

High Speed Op Amp g p p p Schematic

Parasitic Capacitance

(48)

(49)

Stray Capacitance Simulation Schematic y p

(50)

Frequency Response with 2pF Stray Capacitance q y p p y p

1.8dB peaking

1.8dB peaking 1.8dB peaking

(51)

Stray Inductance y

Parasitic Inductance

(52)

Parasitic Inductance Simulation Schematic

AD8055 24.5mm x .25mm” =29nH

(53)

Pulse Response With and Without Ground p Plane

0.6dB overshoot

(54)

Transient Response AD8009 p

1GHz Current Feedback Amplifier

R_F

402Ω +5V

10uF

402Ω

R_G

0.1uF

150Ω

0.1uF

10 F

-5V

10uF

(55)

Small Changes Can Make a Big Difference! g g

Circuit B Circuit A

(56)

Improper Use of Scope Probe Ground Clip p p p p

(57)

Effect of Clip Lead Inductance p

(58)

Proper Grounding for Scope Probe in High- p g p g

Speed Measurments

(59)

Small Changes Make Big Differences g g

Circuit B Circuit A

21ns 17ns

25% reduction in ringing duration and amplitude

(60)

Ground and Power Planes

(61)

Ground and Power Planes Provide

A common reference point p

Shielding

Lower noise

Lower resistance

Lower impedance

Reduces parasitics

Heat sink

Power distribution

(62)

Ground Plane

II

I

(63)

Ground Plane and Trace Routing Ground Plane and Trace Routing

Digital Circuitry Analog

Circuitry

Resistor

Clock Circuitry

Wrong Way

Input Connector

Circuitry Circuitry

Circuitry

Sensitive Analog Circuitry Disrupted by Digital Supply Noise Digital Supply Noise

I_D

ANALOG CIRCUITS

DIGITAL CIRCUITS V_D V_A

+ +

I_A

V_IN

INCORRECT

V_IN

(64)

Ground Plane and Trace Routing Ground Plane and Trace Routing

Circuitry

Resistor

Clock Circuitry

Wrong Way

Circuitry Circuitry

Circuitry

Sensitive Analog Circuitry Disrupted by Digital Supply Noise Digital Supply Noise

I_D

DIGITAL CIRCUITS V_D V_A

+ +

I_A

V_IN

INCORRECT

V_IN

(65)

Ground Plane and Trace Routing Ground Plane and Trace Routing

Circuitry

Resistor

Right Way

Circuitry

Clock Circuitry

Sensitive Analog Circuitry Safe from Digital Supply Noise

I_D

I_A CORRECT

DIGITAL CIRCUITS

V_D V_A

+ +

V_IN

I_A GND

(66)

Ground Plane and Trace Routing Ground Plane and Trace Routing

Circuitry

Resistor

Right Way

Circuitry

Clock Circuitry

Sensitive Analog Circuitry Safe from Digital Supply Noise

I_D

I_A CORRECT

V_D V_A

+ +

V_IN GND

(67)

Ground Plane and Trace Routing Ground Plane and Trace Routing

Grounding Example:

Top layer is solid ground.

Resistor

Signal

Input Termination

p y g

Bottom has a trace/transmission line connecting the RF connector to the load.

R t t fl i th t l

Top Side

Resistor

Return current flows in the top layer ground plane directly above the trace on the opposite side.

Bottom side

(68)

Ground Plane and Trace Routing

Grounding Example: DC Current vs. AC Current:

AC current follows the path of least

impedance

Ground Plane and Trace Routing

In a split or broken ground, the return currents follow the path of least

i d

Resistor

DC current

impedance

At DC, the current follows the path of least resistance

As the frequency increases the

DC current follows the path of least

resistance

As the frequency increases, the current follows the path of least inductance

Since there is now a ‘loop’ the

inductance can be quite high and the circuit can now propagate EMI/RFI

(69)

Grounding Mixed Signal ICs: Single PC Board g g g

ANALOG DIGITAL

V_A V_D

MIXED

V_A V_D

AGND DGND

SIGNAL DEVICE SYSTEM

STAR GROUND

A A D D

ANALOG GROUND PLANE

DIGITAL GROUND PLANE GROUND

D A

DIGITAL ANALOG

SUPPLY SUPPLY

(70)

Ground Plane Recommendations

There is no single grounding method which is guaranteed to work 100% of the time!

R d l d t d iti

Remove ground plane under op amps to reduce parasitic capacitance

At least one layer on each PC board MUST be dedicated to ground plane!

p

Provide as much ground plane as possible especially under traces that operate at high frequency

Use thickest metal as feasible (reduces resistance and provides improved thermal transfer)

improved thermal transfer)

Use multiple vias to connect same ground planes together

Do initial layout with split analog and digital ground planes

Follow recommendations on device data sheet (read datasheet)

Keep bypass capacitors and load returns close to reduce distortion

Connect analog, digital and RF grounds at one point

(71)

Packaging and Pinout

(72)

Op Amp Packaging and Pinout p p g g

Packaging plays a large role in high-speed applications g g p y g g p pp

Smaller packages

zBetter at higher speeds

zLess parasitics

zCompact layout

Analog Devices Low Distortion Pinout

zIntuitively makes more sense

zCompact layout

Streamline signal flow

zStreamline signal flow

zLower distortion

(73)

Op Amp SOIC Packaging p p g g

Traditional SOIC-8 layout

Feedback routed around or underneath amplifier p

(74)

Op Amp SOIC Packaging p p g g

Traditional SOIC-8 layout

Feedback routed around or underneath amplifier p

(75)

Analog Devices Low Distortion Pinout g

Pinout enables compact p

Original Pin-Out

layout

^F^B ¹ ^Disable

2 3

8 7 6

–IN +IN

+V_S V

+ -

NC

3 4

6

–V_S 5

+IN V_OUT

NC

SOIC

1 8

NC +V_S

SOIC

2

5 6

FEEDBACK 7

–IN +IN

S

OUTPUT NC

–V_S

3 4

14-0-0010481

(76)

Analog Devices Low Distortion Pinout g

Pinout enables compact p

Original Pin-Out

layout

Lower distortion

Disable F_B ¹

2 3

8 7 6

–IN +IN

+V_S V

+ -

3 4

6

–V_S 5

+IN V_OUT

NC

SOIC

1 8

NC +V_S

SOIC

2

5 6

FEEDBACK 7

–IN +IN

S

OUTPUT NC

–V_S

3 4

4-0-001

(77)

Analog Devices Low Distortion Pinout g

Pinout enables compact p

Original Pin-Out

layout

Lower distortion

Improved thermal

Disable F_B ¹

2 3

8 7 6

–IN +IN

+V_S V

+ -

Improved thermal

performance

³

4

6

–V_S 5

+IN V_OUT

NC

SOIC

1 8

NC +V_S

SOIC

2

5 6

FEEDBACK 7

–IN +IN

S

OUTPUT NC

–V_S

3 4

4-0-0010481

(78)

Analog Devices Low Distortion Pinout g

Pinout enables compact p

Original Pin-Out

layout

Lower distortion

Improved thermal

Disable F_B ¹

2 3

8 7 6

–IN +IN

+V_S V

+ -

Improved thermal performance

LFCSP

zAD8099 AD8045 AD8000

3 4

6

–V_S 5

+IN V_OUT

NC

zAD8099, AD8045, AD8000, SOIC ADA4899, ADA4857, ADA4817

1 8

NC +V_S

SOIC

2

5 6

FEEDBACK 7

–IN +IN

S

OUTPUT NC

–V_S

3 4

4-0-001

(79)

Low distortion pinout enables compact p p

and streamline layout

(80)

Low distortion pinout enable compact and p p streamline layout

Tantalum

C

RF

C

RL

AD80XX

RT RG R

0 0

Tantalum

(81)

RF Signal Routing and

Shielding

(82)

In This Section

RF Components from Analog Devices

PC Board Circuit Material Types and Minimizing Lossesyp g

Microstrip and Stripline Transmission Lines

Ground Plane Layout Considerations

Developing a RF Printed Circuit Board

Using Discrete Components with RF Devices

Shielding of RF Circuit Boards

(83)

RF Components from Analog Devices

http://www.analog.com/en/rfif-components/products/index.htmlp g p p

(84)

Analog Devices Components Requiring Matched RF Interfaces

AD60x, AD8xxx and ADL533x series of RF/IF and Variable Gain Amplifiers

ADF70xx and 702x series Radio Transmitters and Transceivers

AD4xxx and ADF7xxx series of PLL Synthesizers and VCO’s

AD84xx and ADL53xx series of Modulators and Demodulators

AD83xx and ADL539x series of Mixers and Multipliers

AD83xx and ADL5519 series of Log Amps and Detectors

AD836x and ADL550x series of RMS Detectors ADG9 i f RF S it h

ADG9xx series of RF Switches

(85)

PC Board Circuit Material Type and Minimizing Losses

PC board material selection is usually based on price verses

PC board material selection is usually based on price verses performance

Select PC board dielectric material to have the lowest loss tangent

Some types of “FR4” dielectric materials are low loss below 8-10

Some types of FR4 dielectric materials are low loss below 8-10 GHz

PTFE(Teflon) dielectric material is usually used for the lowest loss at the higher RF and microwave frequency ranges, but at a much g q y g , higher price

Be sure that the correct impedance transmission line is used for the interconnection of the RF devices

Use as wide of a transmission line as possible for the correct

impedance, and try to keep it short to reduce “Skin Effect” losses

Use high “Q”, or low loss passive components for all RF matching, coupling and bypassing requirements

coupling, and bypassing requirements

(86)

Microstrip and Stripline Transmission Lines p p

50 ohm interfaces are most often used between most “integrated”

RF devices

Interconnects less than 1/20 of a wavelength long can usually be made without a matched transmission line

Avoid long microstrip lines as they could become g p y

“antennas”(microstrip) and radiate RF

To minimize coupling to the transmission line, DO NOT place other traces or ground plane closer than three times of the dielectric

h i ht height

Use proper technique for making bends in microstrip lines

Locate the microstrip lines on the component side of the board if possible

possible

(87)

Microstrip Transmission Lines p

Microstrip

Controlled Impedance Line

C S ti

Cross Section

Advantages:

Transmission line on outside layer of board

Easy to attach components to trace

Components can be placed at

different locations along the line to aid in tuning

Aid in RF testing as you are able to measure levels along the line

Disadvantages: 87 ⎡ 5.98H ⎤

g

Slightly higher loss

Not shielded and could radiate RF signal

( )

^⎥_⎦^⎤

⎢⎣

⎡ + +

= W T

Z H

r

O 0.8

98 . ln 5

41 . 1 87 ε

(88)

Stripline Transmission Lines

Stripline

Controlled Impedance Line Cross Section

Advantages:

Lower loss at higher microwave frequencies

frequencies

Shielded transmission line, no RF radiation from board

Disavantages:

Requires vias to connect to line

No ability to connect tuning or termination components to line termination components to line

No access to line to make

adjustments or connections to line

for RF testing Ω = ^⎢_⎣^⎡

(

+

)

^⎥_⎦^⎤

T W Z_O B

8 . 0

) ( 9 . ln 1

) 60

( ε

Higher PCB cost _r _⎣

( )

_⎦

(89)

Microstrip and Stripline Transmission Lines p p

Bends in Microstrip and Stripline

In order to preserve a constant impedance around a bend, some general layout rules MUST be general layout rules MUST be followed

DO NOT make a right angle bend as shown

A i ht l b d b d ith

A right angle bend can be made with a “swept” bend, or a “Mitered” bend

Bends in a transmission line that are less than 90 degrees can also be g

mitered as shown

(90)

Ground Plane Layout Considerations y

Do NOT have breaks or voids in the RF ground plane under, or over RF transmission lines

Ground plane Vias around the RF circuits should be spaced closer than 1/20 of a wavelength as a minimum, or closer if possible at the higher frequencies

Use as large size vias as practical to minimize inductance

“Stitch” the top and bottom ground planes together with as many vias as possible

Signal and bias lines can be placed below RF ground plane layer followed by another “power” ground plane layer for the DC and digital returns

Under components that require heat sinking have solid ground

Under components that require heat sinking, have solid ground plane with many closely spaced vias to transfer heat to all ground plane layers