JFET AMPLIFIER CONFIGURATIONS

(1)

+15V + V_in -+ V_OUT -RL R_G + +

[a] Common Source Amplifier [b] Common Drain [Source Follower] Amplifier

R_S R_S +15V + V_in -+ V_OUT -RL + +

[c] Common Gate Amplifier JFET AMPLIFIER CONFIGURATIONS

+15V R_G + V_in -+ V_OUT -R_S + +

Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007.MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

(2)

R_G +15V I_D R_L + V_out _ +

JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS

R_i + V_i _ R_i R_L g_mV_gs ₊ V_out _ + V_i _ 2N5459 R_S g s g d s + V_gs _ R_S d

COMMON SOURCE AMPLIFIER WITH BYPASSED SOURCE RESISTOR

[

]

L m v S m L m v S m gs L gs m S gs m gs L gs m in out v

R

g

A

or

R

g

R

g

A

R

g

v

R

v

g

R

v

g

v

R

v

g

v

A

−

=

+

−

=

+

−

=

+

−

=

1

2 9/27/06

Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

(3)

R_G +15V I_D + V_out _ +

JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS

R_i + V_i _ R_i g_mV_gs + V_out _ + V_i _ 2N5459 R_S g g + V_gs _ R_S d d s

COMMON DRAIN [SOURCE FOLLOWER] AMPLIFIER

s

[

]

v m_mS _S S m gs S gs m S gs m gs S gs m in out v

R

g

R

g

A

R

g

v

R

v

g

R

v

g

v

R

v

g

v

A

+

=

+

=

+

=

1

;

1

3 9/27/06

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+15V I_D R_L d + V_out _ +

JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS

+ V_i _ R_i RL g_mV_gs ₊ V_out _ + V_i _ 2N5459 R_S g d s _ V_gs + R_S

COMMON GATE AMPLIFIER

s R_i

g

4 9/27/06

(5)

L m v i S i i m L m S i i m gs L gs m in out

R

g

A

R

g

R

g

R

g

v

R

v

g

v

then if v A = = + + = + + − − = =

⎥

⎦

⎤

⎢

⎣

⎡

; , 1 1

0

5 9/27/06

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DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

MASSACHUSETTS INSTITUTE OF TECHNOLOGY

CAMBRIDGE, MASSACHUSETTS 02139

Low Frequency Hybrid-π Equation Chart

TRANSISTORS

Characteristic Common Emitter

CE with RE CC [E. Follower] Common Base

Voltage Gain [if ro >>RL] L m v g R A =− E L v R R A ≈− Av ≈1

(

o

)

s E L o v R R r R A 1 // + + = β β π Current Gain β_o β_o β_o+1 1 + o o β β Input Impedance rπ //RB

(

)

[

rπ + βo +1RE

]

//RB

[

rπ +

(

βo +1

)

RE

]

//RB 1 + o r β π Output Impedance RL [if ro >>RL] RL [if ro >>RL]

(

)

E o B s R R R r // 1 // ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ + + β π RL [if ro >>RL] Phase Reversal? Yes Yes No No JFET’S

Characteristic Common Source C Source with

RS Common Drain [Source Follower] Common Gate Voltage Gain [if rds >>RL] L m v g R A =− S m L m v R g R g A + − = 1 _m _S S m v R g R g A + = 1 S i i m L m v R R R g R g A + + = 1 Ri= generator resistance Current Gain S D I I Very large! S D I I Very large! S D I I Very large! 1 + = S m S m i R g R g A Input Impedance RG RG RG S m S m S R g R g R // 1 1= + Output Impedance RL [if rds >> RL] RL [if rds >> RL] S m S m S R g R g R // 1 1= + RL [if rds >>RL] Phase Reversal? Yes Yes No No 6 9/27/06

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FET COMMON-SOURCE AMPLIFIER BIASING-GRAPHICAL METHOD #1

1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER.

[VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0]

2. ASSUME RS << RL.

3. PLOT A LOAD LINE ON THE OUTPUT CHARACTERISTICS. KEEP THE ID , VDS = 0

INTERCEPT ON THE GRAPH PAGE; I. E. STAY AWAY FROM NEARLY VERTICAL LOAD LINES.

4. CALCULATE RL FROM THE LOAD LINE INTERCEPTS. USE CLOSEST STD. VALUE.

5. PICK Q-POINT VALUE OF VGS FOR MAXIMUM LINEAR OUTPUT SWING.

6. CALCULATE ID: 2 ) off ( GS GS DSS D

V

1

I

⎟

⎠

⎞

⎜

⎝

⎛

−

=

; OR ESTIMATE FROM CHARACTERISTICS.

7. CALCULATE RS FOR VGS AT ID .

R

V

I

S GS D

=

⎛

⎝

⎜

⎞

⎠

⎟

. USE CLOSEST STANDARD VALUE. 8. COMPARE RS AND RL ; IF RS IS CLOSE TO RL , REPLOT THE LOAD LINE.

9. RECALCULATE RS FOR NEW VGS . REPEAT STEPS 7 AND 8 AS NECESSARY!

CALCULATING JFET SMALL-SIGNAL g

m

1. CALCULATE gm FROM ΔID /ΔVGS ON DRAIN CHARACTERISTICS FROM CURVE

TRACER [LARGE SIGNAL gm ]

2. OR USE MEDIAN SPECIFICATION SHEET VALUE. [FOR A FAST ESTIMATE.]

OR DSS D ) off ( GS DSS ) off ( GS GS ) off ( GS DSS m

I

V

I

2

V

1

V

I

2

g

⎟

=

−

⎠

⎞

⎜

⎝

⎛

−

=

WHERE VGS or ID = OPERATING POINT.

When VGS = VGS(OFF), ID = 0 ; IDSS = ID @ VGS = 0. NOTE THAT THE SMALL-SIGNAL

TRANSCONDUCTANCE DEPENDS ON THE DC BIAS POINT, JUST AS IT DOES FOR THE BIPOLAR TRANSISTOR!

7 9/27/06

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FET COMMON-SOURCE AMPLIFIER BIASING-GRAPHICAL METHOD #2

2. REFER TO THE COMBINED TRANSFER [TRANSCONDUCTANCE] CHARACTERISTICS AND DRAIN CHARACTERISTICS CURVES [ATTACHED].

3. CHOOSE RS AS FOLLOWS: DSS ) OFF ( GS S

I

V

R

=

. DRAW THE LINE REPRESENTING RS

FROM THE ORIGIN OF THE TRANSFER CURVE GRAPH; THE “Q” POINT IS AT THE INTERSECTION OF THE TWO PLOTS. THIS SETS IDQ AT ABOUT 0.4 IDSS.

4. EXTEND A HORIZONTAL LINE FROM THE IDQ VALUE ON THE TRANSFER

CHARACTERISTICS’ LEFT-HAND AXIS ALL THE WAY ACROSS THROUGH THE DRAIN CHARACTERISTICS.

5. THE RIGHT-HAND VOLTAGE INTERCEPT FOR THE LOAD LINE [ON THE DRAIN

CHARACTERISTICS] IS EQUAL TO THE SUPPLY VOLTAGE VDD. CHOOSE A VALUE FOR

VDSQ THAT GIVES A ROUGHLY SYMMETRICAL OUTPUT VOLTAGE SWING AROUND VDSQ.

6. DRAW A VERTICAL LINE FROM VDSQ UPWARDS TO INTERSECT WITH THE LINE

DRAWN IN STEP #4. THIS INTERSECTION GIVES THE Q-POINT.

7. DRAW THE LOAD LINE FROM THE SUPPLY VOLTAGE THRU THE Q-POINT UNTIL IT INTERSECTS WITH THE CURRENT AXIS.

8. DIVIDE THE SUPPLY VOLTAGE BY THE CURRENT AXIS VALUE TO GET THE TOTAL VALUE OF RESISTANCE IN THE DRAIN-SOURCE CIRCUIT.

9. SUBTRACT THE VALUE OF RS FOUND IN STEP #3 FROM THE VALUE FOUND IN STEP

#8 TO GET THE VALUE OF LOAD [OR DRAIN] RESISTOR. USE CLOSEST STANDARD VALUE FOR BOTH RESISTORS.

10. NOTE THAT THE MORE VERTICAL THE LOAD LINE, THE SMALLER THE VALUE OF RL. LOW RL EQUALS LOW VOLTAGE GAIN [AV = - gmRL]. ACCEPTING A LOWER

VOLTAGE VDQ WITH ITS ATTENDANT ASYMMETRICAL VOLTAGE SWING WILL ALLOW A

HIGHER VALUE RL. INCREASING SUPPLY VOLTAGE WILL ALSO ALLOW A LARGER

VALUE OF RL AND A MORE SYMMETRICAL VOLTAGE SWING. [THE MORE HORIZONTAL

THE LOAD LINE, THE HIGHER THE TOTAL DRAIN-SOURCE RESISTANCE.]

8 9/27/06

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FET SOURCE-FOLLOWER LOAD LINE/GAIN EXAMPLES & METHOD

2. CHOOSE Q-POINT; i.e. CHOOSE -VGS FROM DRAIN CHARACTERISTICS GRAPH.

3. CALCULATE ID: 2 ) off ( GS GS DSS D

V

1

I

⎟

⎠

⎞

⎜

⎝

⎛

−

=

; OR ESTIMATE FROM CHARACTERISTICS.

4. CALCULATE RS; USE CLOSEST STANDARD VALUE.

5. CALCULATE LOAD LINE INTERCEPTS, [MAY HAVE TO USE Δ BECAUSE THE ID-VDS = 0 INTERCEPT MAY BE WAY OFF THE GRAPH PAGE].

6. CALCULATE gm: DSS D ) off ( GS DSS ) off ( GS GS ) off ( GS DSS m

I

V

I

2

V

1

V

I

2

g

⎟

=

−

⎠

⎞

⎜

⎝

⎛

−

=

7. CALCULATE Av:

A

g R

v m S m S

=

+

1

8. _S m o R g R = 1 //

9. EXAMPLES [VP = VGS(OFF) = -5.8V; IDSS = 9mA]

Example 1 Example 2 Example 3

1. VGS, ID -4V, 1.2mA -3V, 2.3mA -2V, 4.2mA

2. RS= 3.3 kΩ 1.2 kΩ 470 Ω

3. Δ ID @ Δ VDS 4.55mA 12.5V, 5.32mA 10V, 4.17mA

4. gm= 963 μMHO 1,500 μMHO 2,030 μMHO

9 9/27/06

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10 9/27/06 Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT

OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

5. Av= .761 .643 .488