Homework # 2. Solutions. 4.1 What are the differences among sequential access, direct access, and random access?

ECE337 / CS341, Fall 2005

Introduction to Computer Architecture and Organization Instructor: Victor Manuel Murray Herrera

Homework # 2 Solutions

Date assigned: 09/19/05, 05:00 PM Due back: 09/30/05, 8:00 AM

Answer in a brief form the following questions:

4.1 What are the differences among sequential access, direct access, and random access?

Sequential access: Memory is organized into units of data, called records.

Access must be made in a specific linear sequence. Direct access: Individual blocks or records have a unique address based on physical location. Access is accomplished by direct access to reach a general vicinity plus sequential searching, counting, or waiting to reach the final location. Random access: Each addressable location in memory has a unique, physically wired-in addressing mechanism. The time to access a given location is independent of the sequence of prior accesses and is constant.

4.2 What is the general relationship among access time, memory cost, and capacity?

Faster access time, greater cost per bit; greater capacity, smaller cost per bit;

greater capacity, slower access time.

4.3 How does the principle of locality relate to the use of multiple memory levels?

It is possible to organize data across a memory hierarchy such that the percentage of accesses to each successively lower level is substantially less than that of the level above. Because memory references tend to cluster, the data in the higher-level memory need not change very often to satisfy memory access requests.

4.4 What are the differences among direct mapping, associative mapping, and set-associative mapping?

In a cache system, direct mapping maps each block of main memory into only

one possible cache line. Associative mapping permits each main memory block

to be loaded into any line of the cache. In set-associative mapping, the cache

is divided into a number of sets of cache lines; each main memory block can be

mapped into any line in a particular set.

4.5 For a direct-mapped cache, a main memory address is viewed as consisting of three fields. List and define the three fields.

One field identifies a unique word or byte within a block of main memory. The remaining two fields specify one of the blocks of main memory. These two fields are a line field, which identifies one of the lines of the cache, and a tag field, which identifies one of the blocks that can fit into that line.

4.6 For an associative cache, a main memory address is viewed as consisting of two fields. List and define the two fields.

A tag field uniquely identifies a block of main memory. A word field identifies a unique word or byte within a block of main memory.

4.7 For a set-associative cache, a main memory address is viewed as consisting of three fields. List and define the three fields.

One field identifies a unique word or byte within a block of main memory. The remaining two fields specify one of the blocks of main memory. These two fields are a set field, which identifies one of the sets of the cache, and a tag field, which identifies one of the blocks that can fit into that set.

4.8 What is the distinction between spatial locality and temporal locality?

Spatial locality refers to the tendency of execution to involve a number of memory locations that are clustered. Temporal locality refers to the tendency for a processor to access memory locations that have been used recently.

4.9 In general, what are the strategies for exploiting spatial locality and temporal locality?

Spatial locality is generally exploited by using larger cache blocks and by incorporating prefetching mechanisms (fetching items of anticipated use) into the cache control logic. Temporal locality is exploited by keeping recently used instruction and data values in cache memory and by exploiting a cache hierarchy.

* Explain the write policy in the memory cache and the possible approaches to cache coherency.

Before a block that is resident in the cache can be replaced, it is necessary to consider if it has been altered in the cache but not in main memory. Basically, there are two problems with writing in the CACHE memory. First, more than one device may have access to main memory. If a word has been altered only in the CACHE, then the corresponding memory word is invalid.

The simplest technique to write in the CACHE is called write through. With this

technique, all write operations are made to main memory as well as to the

CACHE, ensuring that main memory is always valid. The main disadvantage is

that it generates substantial memory traffic and may create a bottleneck. An alternative technique, knows as write back, minimizes memory writes. With this, updates are made only in the CACHE. When an update occurs, an UPDATE bit associated with the line is set. Then, when a block is replaced, it is written back to main memory if and only if the UPDATE bit is set.

Another problem is when there is more than one device that has its own CACHE.

Possible approaches to CACHE coherency are: Bus watching: Each CACHE controller monitors the address lines to detect write operations to memory by other bus masters. If another bus master writes to a location in shared memory that also resides in the cache memory, the cache controller invalidates that cache entry. This technique depends on the use of a write-through policy by all cache controllers. Hardware transparency: Additional hardware is used to ensure that all updates to main memory via cache are reflected in all caches.

Non-cacheable memory: Only a portion of main memory is shared by more than one processor, and this is designated as non-cacheable.

5.1 What are the key properties of semiconductor memory?

They exhibit two stable (or semistable) states, which can be used to represent binary 1 and 0; they are capable of being written into (at least once), to set the state; they are capable of being read to sense the state.

5.2 What are two senses in which the term random-access memory is used?

(1) A memory in which individual words of memory are directly accessed through wired-in addressing logic. (2) Semiconductor main memory in which it is possible both to read data from the memory and to write new data into the memory easily and rapidly.

5.3 What is the difference between DRAM and SRAM, in terms of application?

SRAM is used for cache memory (both on and off chip), and DRAM is used for main memory.

5.4 What is the difference between DRAM and SRAM, in terms of characteristics such as speed, size, and cost?

SRAMs generally have faster access times than DRAMs. DRAMS are less expensive and smaller than SRAMs.

5.5 Explain why one type of RAM is considered to be analog and the other digital.

A DRAM cell is essentially an analog device using a capacitor; the capacitor can

store any charge value within a range; a threshold value determines whether the

charge is interpreted as 1 or 0. A SRAM cell is a digital device, in which binary

values are stored using traditional flip-flop logic-gate configurations.

5.6 What are some applications for ROM?

Microprogrammed control unit memory; library subroutines for frequently wanted functions; system programs; function tables.

* What are the differences among PROM, EPROM, EEPROM, and flash memory?

PROM is a nonvolatile read only memory that can be written into only once. The writing process is performed electrically and may be performed by a supplier or customer at a time later than the original chip fabrication. EPROM is read and written electrically; before a write operation, all the storage cells must be erased to the same initial state by exposure of the packaged chip to ultraviolet radiation.

Erasure is performed by shining an intense ultraviolet light through a window that is designed into the memory chip. EEPROM is a read-mostly memory that can be written into at any time without erasing prior contents; only the byte or bytes addressed are updated. Flash memory is intermediate between EPROM and EEPROM in both cost and functionality. Like EEPROM, flash memory uses an electrical erasing technology. An entire flash memory can be erased in one or a few seconds, which is much faster than EPROM. In addition, it is possible to erase just blocks of memory rather than an entire chip. However, flash memory does not provide byte-level erasure. Like EPROM, flash memory uses only one transistor per bit, and so achieves the high density (compared with EEPROM) of EPROM.

5.8 Explain the function of each pin in the next picture:

A0 - A1 = address lines. CAS = column address select. D1 - D4 = data lines. NC:

= no connect. OE: output enable. RAS = row address select. Vcc = voltage source. Vss = ground. WE: write enable.

5.9 What is the parity bit?

A bit appended to an array of binary digits to make the sum of all the binary digits, including the parity bit, always odd (odd parity) or always even (even parity).

5.10 How is the syndrome for the Hamming code interpreted?

A syndrome is created by the XOR of the code in a word with a calculated version of that code. Each bit of the syndrome is 0 or 1 according to if there is or is not a match in that bit position for the two inputs. If the syndrome contains all 0s, no error has been detected. If the syndrome contains one and only one bit set to 1, then an error has occurred in one of the 4 check bits. No correction is needed. If the syndrome contains more than one bit set to 1, then the numerical value of the syndrome indicates the position of the data bit in error. This data bit is inverted for correction.

5.11 How does SDRAM differ from ordinary DRAM?

Unlike the traditional DRAM, which is asynchronous, the SDRAM exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states.

PROBLEMS

4.1 A set associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses.

The cache is divided into 16 sets of 4 lines each. Therefore, 4 bits are needed to identify the set number. Main memory consists of 4K = 212 blocks. Therefore, the set plus tag lengths must be 12 bits and therefore the tag length is 8 bits. Each block contains 128 words. Therefore, 7 bits are needed to specify the word.

TAG SET WORD

Main memory address = 8 4 7

4.3 For the hexadecimal main memory addresses: 111111H, 666666H, BBBBBBH, show the following information, in hexadecimal format:

a. Tag, line, and word values for a direct-mapped cache, using the format of figure 4.8.

b. Tag and word values for an associative cache, using the format of figure 4.10.

c. Tag, set and word values for a two-way set associative cache, using the

format of figure 4.12.

Address (H) 111111

Address (binary) 000100010001000100010001 a. Tag (8) / Line (14) / Word (2) 11H / 0444H / 1H

b. Tag (22) / Word (2) 044444H / 1H c. Tag (9) / Set (13) / Word (2) 022H / 0444H / 1H

Address (H) 666666

Address (binary) 011001100110011001100110 a. Tag (8) / Line (14) / Word (2) 66H / 1999H / 2H

b. Tag (22) / Word (2) 199999H / 2H c. Tag (9) / Set (13) / Word (2) 0CCH / 1999H / 2H

Address (H) BBBBBB

Address (binary) 101110111011101110111011 a. Tag (8) / Line (14) / Word (2) BBH / 2EEEH / 3H

b. Tag (22) / Word (2) 2EEEEEH / 3H c. Tag (9) / Set (13) / Word (2) 177H / 0EEEH / 3H

4.4 List the following values:

a. For the direct cache example of figure 4.8: address length, number of addressable units, block size, number of blocks in main memory, number of lines in cache, size of tag.

b. For the associative cache example of figure 4.10: address length, number of addressable units, block size, number of blocks in main memory, number of lines in cache, size of tag.

c. For the two-way associative cache example of figure 4.12: address length, number of addressable units, block size, number of blocks in main memory, number of lines in set, number of sets, number of lines in cache, size of tag.

a) Address length: 24; number of addressable units: 224; block size: 4;

number of blocks in main memory: 222; number of lines in cache: 214;

size of tag: 8.

b) Address length: 24; number of addressable units: 224; block size: 4;

number of blocks in main memory: 222; number of lines in cache: 4000 hex; size of tag: 22.

c) Address length: 24; number of addressable units: 224; block size: 4;

number of blocks in main memory: 222; number of lines in set: 2; number

of sets: 213; number of lines in cache: 214; size of tag: 9.

Internal Memory

Suppose that we have a 7-bit word DRAM. Assume that you store the 7-bit input word: 0011001.

• What is the minimum number of ‘k’ bits necessary for the Hamming single- error-correcting (SEC)?

Suppose that when you read the data, the bit 1 of the input value (let bit 1 the least significant bit), change from 1 to 0 (without change of the parity bits).

• Show the whole procedure for the check bit calculation (like the example in pages 156-159 (150 – 153 in 6

edition) of the textbook).

We know that: 2

−1 ≥ M + K . Since M = 7 (7 bits), then K = 4.

Now:

Bit position

11 10 9 8 7 6 5 4 3 2 1

Position number

1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001

Data bit D7 D6 D5 D4 D3 D2 D1

Check bit

C8 C4 C2 C1

7 5 4 2 1

1 D D D D D

C = ⊕ ⊕ ⊕ ⊕

7 6 4 3 1

2 D D D D D

C = ⊕ ⊕ ⊕ ⊕

6 4 3 2

4 D D D D

C = ⊕ ⊕ ⊕

7 6 5

8 D D D

C = ⊕ ⊕

Bit position

11 10 9 8 7 6 5 4 3 2 1

Position number

1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001

Data bit D7 D6 D5 D4 D3 D2 D1

Check bit

C8 C4 C2 C1

Word stored as

0 0 1 1 1 0 0 1 1 0 1

Word fetched as

0 0 1 1 1 0 0 1 0 0 1

Check bit

1 1 1 0

So, after the final check, we have:

0011 1110

1101 ⊕ =

That means that we have an error in position 3, that is the bit 1 (D1).