COURSE PLAN
Subject : Microprocessor & Microcontroller Year :III yr regular Topic
No Topic Name No. of
Periods
Proposed Date of Completion UNIT – I : INTEL 8086 MICROPROCESSOR
1
Evolution of microprocessor and its types. Features and
architecture of 8086 microprocessor
2 12/7/2021
2
8086 pin configuration.
Instruction set of 8086-data transfer
2
18/7/2021
3
Instruction set of 8086- arithmetic instruction, Bit manipulation instruction
2
19/7/2021
4
Instruction set of 8086-Branch &
loop instruction, process control
& interrupt instruction
2
24/7/2021
5
Interrupt of 8086
microprocessor. Addressing modes of 8086 microprocessor
2
26/7/2021
6 Assembly language programming
of 8086 2 31/7/2021
UNIT – II : INTEL 8051 MICROCONTROLLER
1
Introduction of microcontroller, architecture of 8051
microcontroller
2 2/8/2021
2
Pin configuration of 8051 microcontroller, I/O ports and circuits,timer/counter
2 7/8/2021
3 Special function registers in 8051,
Memory organisation of 8051 2 9/8/2021
4 serial communication 2 14/8/2021
5 Interrupt in 8051 microcontroller 23/8/2021 UNIT – III : INTEL 8051 PROGRAMMING
1
Introduction to instruction set, data transfer group, Arithmetic group
2 28/8/2021
2 Logical group, Program branch
group 2 4/9/2021
3
Boolean manipulation group, Addressing modes on 8051 microcontroller
2 6/9/2021
4 Assembly language programming
of 8051 microcontroller 2 11/9/2021
UNIT – IV : PERIPHERAL INTERFACING
1 Parallel I/O 8255 2 13/9/2021
2 Programmable interval timer
8254 18/9/2021
3 Keyboard/display controller
8279, Serial I/O 8251 2 20/9/2021
4 D/A interfacing, A/D interfacing 2 27/9/2021 5 Temperature sensor and stepper
motor interfacing 2 4/109/2021
UNIT – V : ADVANCED MICROPROCESSOR AND MICROCONTROLLER
1 AVR microcontroller 2 9/10/2021
2 PIC microcontroller 2 11/10/2021
3 ARM microcontroller 2 16/10/2021
4 JTAG boundary scan architecture 2 18/10/2021
5 Core 2 duo processor 2 20/10/2021
6 I7 core processor 2 25/10/2021
MICROPROCESSOR AND MICROCONTROLLER
AIM
To learn the concepts of microprocessor, microcontroller and its applications
To design microprocessor & microcontroller along with interfacing devices
To understand the impact of microcontroller in engineering applications.
OBJECTIVE
Provide an overview of difference between microprocessor and micro controller.
Provide background knowledge and core expertise in 8086 microprocessor and 8051 microcontroller.
Provide an overview of architecture and the pin configuration of 8086 microprocessor and Intel 8051 microcontroller.
Exhibit programming skills, choose suitable hardware and program the devices to solve engineering problems.
Overview about advanced microcontroller like AVR,PIC and ARM
PRE TEST
1)The binary number 11111010 is equivalent to hexadecimal number is …………..
a) FA b)AF c)2A d)F1
2)2’s complement of binary number 0101 is ………..
a) 1011 b) 1111 c) 1101d)1110
3) A device which converts BCD to seven segments is called ……..
a) Encoder b) Decoder c) Multiplexer d)None of these 4)For the gate in the given figure the output will be ………..
a) 0 b) 1 c) Ad) Ā
4) The basic storage element in a digital system is ………….
a) Flipflop b) counter c) multiplexer d)encoder 5) Which device has one input and many outputs?
a) Multiplexer b) Demultiplexer c) Counter d)Flip flop
6) The hexadecimal number (3E8)16 is equal to decimal number ………
a) 1000 b) 982 c)768 d)323
7) A three state switch has three outputs. These are …….. , …….. , ……….
a) low, low and high b) low, high, high c)low. floating, low d) low, high, floating 8) 1’s complement of 11100110 is ……….
a) 00011001 b)10000001 c)00011010 d)00000000
9) The hexadecimal number (3E8)16 is equal to decimal number ………
a) 1000 b)982 c) 768 d)323
10) A counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2 MHz clock. Then conversion time is ………..
a) 8 μ sec b)10 μ sec c)2 μ sec d) 5 μ sec Answer
1) a 2) a 3) b 4) d 5) a 6) a 7) d 8) a 9) a 10) a
THEORY BEHIND
MODULE I
INTEL 8086 MICROPROCESSOR
Microprocessor Evolution and Types- Architecture of 8086- Pin configuration-Instruction Set- Addressing Modes – Interrupts-Simple Programs.
EVOLUTION OF MICROPROCESSOR – TYPES OF MICROPROCESSORS
The microprocessor is nothing but the CPU and it is an essential component of the computer.
It is a silicon chip that comprises millions of transistors and other electronic components that process millions of instructions per second. A Microprocessor is a versatile chip that is
combined with memory and special-purpose chips and pre-programmed by software. It accepts digital data as i/p and processes it according to the instructions stored in the memory.
The microprocessor has many functions like functions of data storage; interact with various other devices and other time-related functions. But, the main function is to send and receive the data to make the function of the computer well. This article discusses the types and evolution of microprocessors.
Microprocessor Evolution of Microprocessor
The microprocessor has become a more essential part of many gadgets. The evolution of microprocessors was divided into five generations such as first, second, third, fourth and fifth generation and the characteristics of these generations are discussed below.
First Generation Microprocessors
The first generation microprocessors were introduced in the year 1971-1972. The instructions of these microprocessors were processed serially; they fetched the instruction, decoded and then executed it. When an instruction of the microprocessor was finished, then the microprocessor updates the instruction pointer & fetched the following instruction, performing this consecutive operation for each instruction in turn.
Second Generation Microprocessors
In the year 1970, a small number of transistors were available on the integrated circuit in the second-generation microprocessors. Examples of the second-generation microprocessors are
16-bit arithmetic 7 pipelined instruction processing, MC68000 Motorola microprocessor.
These processors are introduced in the year 1979, and Intel 8080 processor is another example of the microprocessor. The second generation of the microprocessor is defined by overlapped fetch, decode and execute the steps. When the first generation is processed in the execution unit, then the second instruction is decoded and the third instruction is fetched.
The difference between the first generation microprocessor and second-generation microprocessors was mainly the use of new semiconductor technologies to manufacture the chips. The result of this technology resulted in a fivefold increase in instruction, speed, execution and higher chip densities.
Third Generation Microprocessors
The third generation microprocessors were introduced in the year 1978, as denoted by Intel’s 8086 and the ZilogZ8000. These were 16-bit processors with a performance like mini computers. These types of microprocessors were different from the previous generations of microprocessors in that all main workstation industrialists began evolving their own ISC based microprocessor architectures.
Fourth Generation Microprocessors
As many industries converted from commercial microprocessors to in house designs, the fourth generation microprocessors are entered with outstanding design with a million transistors. Leading-edge microprocessors like Motorola’s 88100 and Intel’s 80960CA could issue & retire more than one instruction per clock cycle.
Fifth Generation Microprocessors
Fifth-generation microprocessors employed decoupled superscalar processing, and their design soon exceeded 10 million transistors. In the fifth generation, PCs are a low-margin, high volume business conquered by a single microprocessor.
Types of Microprocessor
Microprocessors are classified into five types, namely: CISC-Complex Instruction Set Microprocessors, RISC-Reduced Instruction Set Microprocessor, ASIC- Application Specific Integrated Circuit, Superscalar Processors, DSP’s-Digital Signal Microprocessors.
Types of Microprocessors Complex Instruction Set Microprocessors
The short term of Complex Instruction Set Microprocessors is CISM and they classify a microprocessor in which orders can be performed together along with other low-level activities. These types of processors perform different tasks like downloading, uploading, recalling data into the memory card and recalling data from the memory card. Apart from these tasks, it also does complex mathematical calculations in a single command.
Reduced Instruction Set Microprocessor
The short term of Reduced Instruction Set Microprocessor is RISC. These types of processors are made according to the function in which the microprocessor can carry out small things in specific commands. In this way, these processors complete more commands at a faster rate.
Superscalar Microprocessors
Superscalar processor facsimiles the hardware on the processor to perform various tasks at a time. These processors can be used for ALUs or multipliers. They have different operational units and these processors can carry out more than one command by continuously transmitting several instructions to the extra operational units inside the processor.
The Application Specific Integrated Circuit
The short term of Application Specific Integrated Circuit processor is an ASIC. These processors are used for particular purposes that include automotive emissions control or personal digital assistants computer. This type of processor is made with the proper specification, but apart from these, it can also be made with off the shelf gears.
Digital Signal Multiprocessors
Digital signal processors are also called as DSP’s, these processors are used to encode and decode the videos or to convert the D/A (digital to analog) &A/D (analog to digital). They need a microprocessor that is excellent in mathematical calculations. The chips of this processor are employed in RADAR, home theatres, SONAR, audio gears, TV set-top boxes, and Mobile phones
There are many companies like Intel, Motorola, DEC (Digital Equipment Corporation ), TI (Texas Instruments) associated with many microprocessors such as 8085 microprocessors, ASIC, CISM, RISC, DSPs and 8086 microprocessors like Intel
ADVANTAGES AND DISADVANTAGES OF MICROPROCESSORS
The advantages of microprocessors are
The processing speed is high
Intelligence has been brought to systems
Flexible.
Compact size.
Easy maintenance
Complex mathematics
Some of the disadvantages of the microprocessor are it might get overheated and the limitation of the microprocessor imposes on the size of data.
The applications of the microprocessors mainly involve in controllers in home appliances, wireless communication equipment, office publication and automation, consumer electronic goods, calculators, accounting system, video games, industrial controllers and data acquisition systems
8086 MICROPROCESSOR ARCHITECTURE AND OPERATION
It is a 16 bit microprocessor. 8086 has a 20 bit address bus can access up to 220 memory locations ( 1 MB) . It can support up to 64K I/O ports. It provides 14, 16-bit registers. It has multiplexed address and data bus AD0- AD15 and A16 – A19. It requires single phase clock with 33% duty cycle to provide internal timing. 8086 is designed to operate in two modes, Minimum and Maximum. It can prefetches up to 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package.
Minimum and Maximum Modes
The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single microprocessor configuration. The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi-microprocessors configuration.
8086 microprocessor architecture
Internal Architecture of 8086 has two blocks BIU and EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. Bus Interface Unit: It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions: Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control. The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.
This queue permits prefetches of up to six bytes of instruction code. Whenever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction. These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output. The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory. These intervals of no bus activity, which may occur between bus cycles, are known as Idle state. If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. The BIU also contains a dedicated adder which is used to generate the 20 bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address.
For example, the physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register. The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.
Execution Unit
The Execution unit is responsible for decoding and executing all instructions. The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bus cycles to memory or I/O and perform the operation specified by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.
Internal Registers of 8086
The 8086 has four groups of the user accessible internal registers. They are the instruction pointer, four data registers, four pointer and index register, four segment registers.
The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status register, with 9 of bits implemented for status and control flags. Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix.
All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are:
Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation.
Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH
contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing.
Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used in Loop, shift/rotate instructions and as a counter in string manipulation,.
Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high- order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high- order word of the initial or resulting number. The following registers are both general and index registers:
Stack Pointer (SP) is a 16-bit register pointing to program stack. Base Pointer (BP) is a 16- bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.
Flags is a 16-bit register containing 9 one bit flags.
Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand.
Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.
Sign Flag (SF) - set if the most significant bit of the result is set.
Zero Flag (ZF) - set if the result is zero
Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register.
Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even.
Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation.
ADDRESSING MODES
The way of specifying data to be operated by an instruction is known as addressing modes.
Implied - the data value/data address is implicitly associated with the instruction.
Register- references the data in a register or in a register pair.
Immediate - the data is provided in the instruction.
Direct - the instruction operand specifies the memory address where data is located.
Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers.
Based :- 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides.
Indexed :- 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides.
Based Indexed :- the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides.
Based Indexed with displacement :- 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides.
INTERRUPTS IN 8086 MICROPROCESSOR The processor has the following interrupts:
INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction.
When an interrupt occurs, the processor stores FLAGS register into stack, disables further interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine address of which is stored in location 4 * <interrupt type>. Interrupt processing routine should return with the IRET instruction.
NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location 0008h. This interrupt has higher priority then the maskable interrupt.
Software interrupts can be caused by: INT instruction - breakpoint interrupt. This is a type 3 interrupt. INT <interrupt number> instruction - any one interrupt from available 256 interrupts. INTO instruction - interrupt on overflow Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine.
Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode (type 7). Software interrupt processing is the same as for the hardware interrupts.
The figure below shows the 256 interrupt vectors arranged in the interrupt vector table in the memory.
Minimum Mode Interface When the Minimum mode operation is selected, the 8086 provides all control signals needed to implement the memory and I/O interface. The minimum mode signal can be divided into the following basic groups : address/data bus, status, control, interrupt and DMA.
Address/Data Bus : these lines serve two functions. As an address bus is 20 bits long and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit address gives the 8086 a 1Mbyte memory address space. More over it has an independent I/O address space which is 64K bytes in length.
The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively. By multiplexed we mean that the bus work as an address bus
during first machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0 LSB. When acting as a data bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt type codes from an interrupt controller.
Status signal : The four most significant address lines A19 through A16 are also multiplexed but in this case with status signals S6 through S3. These status bits are output on the bus at the same time that data are transferred over the other bus lines. Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment registers are used to generate the physical address that was output on the address bus during the current bus cycle.
Code S4S3 = 00 identifies a register known as extra segment register as the source of the segment address.
Memory segment status code
Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level.
Control Signals : The control signals are provided to support the 8086 memory I/O interfaces. They control functions such as when the bus is to carry a valid address in which direction data are to be transferred over the bus, when valid write data are on the bus and when to put read data on the system bus.
ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.
Another control signal that is produced during the bus cycle is BHE bank high enable. Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1.
These lines also serves a second function, which is as the S7 status line. Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus. The logic level of M/IO tells external circuitry whether a memory or I/O transfer is taking place over the bus. Logic 1 at this output signals a memory operation and logic 0 an I/O operation. The direction of data transfer over the bus is 74ignallin by the logic level output at DT/R. When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode.
Therefore, data are either written into memory or output to an I/O device. On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This corresponds to reading data from memory or input of data from an input port. The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to signal external device that valid write or output data are on the bus. On the other hand, RD indicates that the 8086 is performing a read of data of the bus.
During read operations, one other control signal is also supplied. This is DEN (data enable) and it signals external devices when they should put data on the bus. There is one other control signal that is involved with the memory and I/O interface. This is the READY signal.
READY signal is used to insert wait states into the bus cycle such that it is extended by a number of clock periods. This signal is provided by an external clock generator device and can be supplied by the memory or I/O sub- system to signal the 8086 when they are ready to permit the data transfer to be completed.
Maximum Mode Interface When the 8086 is set for the maximum-mode configuration, it provides signals for implementing a multiprocessor / coprocessor system environment. By multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own program. Usually in this type of system environment, there are some system resources that are common to all processors. They are called as global resources. There are also other resources that are assigned to specific processors. These are known as local or private resources. Coprocessor also means that there is a second processor in the system. In this two processor does not access the bus at the same time. One passes the control of the system bus to the other and then may suspend its operation. In the maximum - mode 8086 system, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor.
ASSEMBLY LANGUAGE PROGRAMMING OF 8086 Machine Language
• Set of fundamental instructions the machine can execute.
• Expressed as a pattern of 1’s and 0’s
Assembly Language
• Alphanumeric equivalent of machine language
• Mnemonics more human-oriented than 1’s and 0’s
Assembler:
• Computer program that transliterates (one-to-one mapping) assembly to machine language
• Computer’s native language is machine/assembly language
CPU Registers:
Fourteen 16-bit registers „ Data Registers
• AX (Accumulator Register): AH and AL
• BX (Base Register): BH and BL
• CX (Count Register): CH and CL
• DX (Data Register): DH and DL „ Pointer and Index Registers
• SI (Source Index)
• DI (Destination Index)
• SP (Stack Pointer)
• BP (Base Pointer)
• IP (Instruction Pointer) Segment Registers
• CS (Code Segment)
• DS (Data Segment)
• SS (Stack Segment)
• ES (Extra Segment) „ FLAGS Register:
• Zero flag • Sign flag • Parity flag • Carry flag • Overflow flag
Fetch-Execute Process „ Program Counter (PC) or Instruction Pointer (IP)
• Holds address of next instruction to fetch „ Instruction Register (IR)
• Stores the instruction fetched from memory. „ Fetch-Execute process
• Read an instruction from memory addressed by PC
• Increment program counter
• Execute fetched instruction in IR
• Repeat process
Assembly Language Syntax
Program consists of statement per line. „ Each statement is an instruction or assembler directive „ Statement syntax
• Name operation operand(s) comment „ Name field
• Used for instruction labels, procedure names, and variable names.
• Assembler translates names into memory addresses
• Names are 1-31 characters including letters, numbers and special characters ? . @ _ $ %
• Names may not begin with a digit.
INSTRUCTION SET OF 8086 MICROPROCESSOR The 8086 microprocessor supports 8 types of instructions −
Data Transfer Instructions
Arithmetic Instructions
Bit Manipulation Instructions
String Instructions
Program Execution Transfer Instructions (Branch & Loop Instructions)
Processor Control Instructions
Iteration Control Instructions
Interrupt Instructions
Let us now discuss these instruction sets in detail.
Data Transfer Instructions
These instructions are used to transfer the data from the source operand to the destination operand. Following are the list of instructions under this group −
Instruction to transfer a word
MOV − Used to copy the byte or word from the provided source to the provided destination.
PPUSH − Used to put a word at the top of the stack.
POP − Used to get a word from the top of the stack to the provided location.
PUSHA − Used to put all the registers into the stack.
POPA − Used to get words from the stack to all registers.
XCHG − Used to exchange the data from two locations.
XLAT − Used to translate a byte in AL using a table in the memory.
Instructions for input and output port transfer
IN − Used to read a byte or word from the provided port to the accumulator.
OUT − Used to send out a byte or word from the accumulator to the provided port.
Instructions to transfer the address
LEA − Used to load the address of operand into the provided register.
LDS − Used to load DS register and other provided register from the memory
LES − Used to load ES register and other provided register from the memory.
Instructions to transfer flag registers
LAHF − Used to load AH with the low byte of the flag register.
SAHF − Used to store AH register to low byte of the flag register.
PUSHF − Used to copy the flag register at the top of the stack.
POPF − Used to copy a word at the top of the stack to the flag register.
Arithmetic Instructions
These instructions are used to perform arithmetic operations like addition, subtraction, multiplication, division, etc.
Following is the list of instructions under this group −
Instructions to perform addition
ADD − Used to add the provided byte to byte/word to word.
ADC − Used to add with carry.
INC − Used to increment the provided byte/word by 1.
AAA − Used to adjust ASCII after addition.
DAA − Used to adjust the decimal after the addition/subtraction operation.
Instructions to perform subtraction
SUB − Used to subtract the byte from byte/word from word.
SBB − Used to perform subtraction with borrow.
DEC − Used to decrement the provided byte/word by 1.
NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.
CMP − Used to compare 2 provided byte/word.
AAS − Used to adjust ASCII codes after subtraction.
DAS − Used to adjust decimal after subtraction.
Instruction to perform multiplication
MUL − Used to multiply unsigned byte by byte/word by word.
IMUL − Used to multiply signed byte by byte/word by word.
AAM − Used to adjust ASCII codes after multiplication.
Instructions to perform division
DIV − Used to divide the unsigned word by byte or unsigned double word by word.
IDIV − Used to divide the signed word by byte or signed double word by word.
AAD − Used to adjust ASCII codes after division.
CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower byte.
CWD − Used to fill the upper word of the double word with the sign bit of the lower word.
Bit Manipulation Instructions
These instructions are used to perform operations where data bits are involved, i.e.
operations like logical, shift, etc.
Following is the list of instructions under this group −
Instructions to perform logical operation
NOT − Used to invert each bit of a byte or word.
AND − Used for adding each bit in a byte/word with the corresponding bit in another byte/word.
OR − Used to multiply each bit in a byte/word with the corresponding bit in another byte/word.
XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the corresponding bit in another byte/word.
TEST − Used to add operands to update flags, without affecting operands.
Instructions to perform shift operations
SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.
SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into the new MSB.
Instructions to perform rotate operations
ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry Flag [CF].
ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry Flag [CF].
RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to MSB.
RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB.
String Instructions
String is a group of bytes/words and their memory is always allocated in a sequential order.
Following is the list of instructions under this group −
REP − Used to repeat the given instruction till CX ≠ 0.
REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF
= 1.
MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided memory location.
OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided memory location to the I/O port.
SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL or string word with a word in AX.
LODS/LODSB/LODSW − Used to store the string byte into AL or string word into AX.
Program Execution Transfer Instructions (Branch and Loop Instructions)
These instructions are used to transfer/branch the instructions during an execution. It includes the following instructions −
Instructions to transfer the instruction during an execution without any condition −
CALL − Used to call a procedure and save their return address to the stack.
RET − Used to return from the procedure to the main program.
JMP − Used to jump to the provided address to proceed to the next instruction.
Instructions to transfer the instruction during an execution with some conditions −
JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
JAE/JNB − Used to jump if above/not below instruction satisfies.
JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
JC − Used to jump if carry flag CF = 1
JE/JZ − Used to jump if equal/zero flag ZF = 1
JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.
JNC − Used to jump if no carry flag (CF = 0)
JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
JNO − Used to jump if no overflow flag OF = 0
JNP/JPO − Used to jump if not parity/parity odd PF = 0
JNS − Used to jump if not sign SF = 0
JO − Used to jump if overflow flag OF = 1
JP/JPE − Used to jump if parity/parity even PF = 1
JS − Used to jump if sign flag SF = 1
Processor Control Instructions
These instructions are used to control the processor action by setting/resetting the flag values.
Following are the instructions under this group −
STC − Used to set carry flag CF to 1
CLC − Used to clear/reset carry flag CF to 0
CMC − Used to put complement at the state of carry flag CF.
STD − Used to set the direction flag DF to 1
CLD − Used to clear/reset the direction flag DF to 0
STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.
Iteration Control Instructions
These instructions are used to execute the given instructions for number of times. Following is the list of instructions under this group −
LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0
LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX
= 0
LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 &
CX = 0
JCXZ − Used to jump to the provided address if CX = 0 Interrupt Instructions
These instructions are used to call the interrupt during program execution.
INT − Used to interrupt the program during execution and calling service specified.
INTO − Used to interrupt the program during execution if OF = 1
IRET − Used to return from interrupt service to the main program
MODULE II
INTEL 8051 MICROCONTROLLER
8051 Architecture-pin configuration – flags and PSW-CPU registers-Internal RAM & ROM- Special Function Registers- I/O Ports & Circuits.
INTEL 8051 Microcontroller
INTRODUCTION TO MICROCONTROLLER
A microcontroller is a small and low-cost microcomputer, which is designed to perform the Specific tasks of embedded systems like displaying microwave’s information, receiving remotesignals, etc. The general microcontroller consists of the processor, the memory (RAM, ROM, and EPROM), Serial ports, peripherals (timers, counters), etc.
The following table highlights the differences between a microprocessor and a microcontroller
TYPES OF MICROCONTROLLERS
Microcontrollers are divided into various categories based on memory, architecture, bits and Instruction sets.
Following is the list of their types –
A) Bit
Based on bit configuration, the microcontroller is further divided into three categories.
8-bit microcontroller − this type of microcontroller is used to execute arithmetic and logical operations like addition, subtraction, multiplication division, etc. For example, Intel 8031 and 8051 are 8 bits microcontroller.
16-bit microcontroller − this type of microcontroller is used to perform arithmetic and logical operations where higher accuracy and performance is required. For example,
Intel 8096 is a 16-bit microcontroller.
32-bit microcontroller − this type of microcontroller is generally used in automatically controlled appliances like automatic operational machines, medical appliances, etc.
b) Memory Based on the memory configuration, the microcontroller is further divided into two categories.
External memory microcontroller − This type of microcontroller is designed in such a way that they do not have a program memory on the chip. Hence, it is named as external memory microcontroller. For example: Intel 8031 microcontroller.
Embedded memory microcontroller − this type of microcontroller is designed in such a way that the microcontroller has all programs and data memory, counters and timers, interrupts, I/O ports are embedded on the chip. For example: Intel 8051 microcontroller.
c) Instruction Set
Based on the instruction set configuration, the microcontroller is further divided into two Categories.
CISC − CISC stands for complex instruction set computer. It allows the user to insert asingle instruction as an alternative to many simple instructions.
RISC − RISC stands for Reduced Instruction Set Computers. It reduces the operational time by shortening the clock cycle per instruction.
APPLICATIONS OF MICROCONTROLLERS
Microcontrollers are widely used in various different devices such as − Light sensing and controlling devices like LED.
Temperature sensing and controlling devices like microwave oven, chimneys.
Fire detection and safety devices like Fire alarm.
Measuring devices like Volt Meter.
INTRODUCTION TO 8051 MICROCONTROLLER
8051 microcontroller is designed by Intel in 1981. It is an 8-bit microcontroller. It is built with40 pins DIP (dual inline package), 4kb of ROM storage and 128 bytes of RAM storage, 2 16-bittimers. It consists of are four parallel 8-bit ports, which are programmable as well as addressable as per the requirement. An on-chip crystal oscillator is integrated in the microcontroller having crystal frequency of 12 MHz.
Features of 8051 MC
4K bytes internal ROM
128 bytes internal RAM
Four 8-bit I/O ports (P0 - P3).
Two 16-bit timers/counters
One serial interface
only 1 On chip oscillator (external crystal)
6 interrupt sources (2 external , 3 internal, Reset)
64K external code (program) memory(only read)PSEN
64K external data memory(can be read and write) by RD,WR
Code memory is selectable by EA (internal or external)
ARCHITECTURE OF 8051 MICROCONTROLLER.
In the following diagram, the system bus connects all the support devices to the CPU. The system bus consists of an 8-bit data bus, a 16-bit address bus and bus control signals. All otherdevices like program memory, ports, data memory, serial interface, interrupt control, timers, andthe CPU are all interfaced together through the system bus.
The pin diagram of 8051 microcontroller looks as follows –
Pins 1 to 8 − these pins are known as Port 1. This port doesn’t serve any other functions.It is internally pulled up, bi-directional I/O port.
Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its initial values.
Pins 10 to 17 − these pins are known as Port 3. This port serves some functions like interrupts, timer input, control signals, serial communication signals RxD and TxD, etc.
Pins 18 & 19 − these pins are used for interfacing an external crystal to get the system clock.
Pin 20 − this pin provides the power supply to the circuit.
Pins 21 to 28 − these pins are known as Port 2. It serves as I/O port. Higher order
address bus signals are also multiplexed using this port.
Pin 29 − this is PSEN pin which stands for Program Store Enable. It is used to read a signal from the external program memory.
Pin 30 − this is EA pin which stands for External Access input. It is used to enable/disable the external memory interfacing.
Pin 31 − this is ALE pin which stands for Address Latch Enable. It is used to demultiplex the address-data signal of port.
Pins 32 to 39 − these pins are known as Port 0. It serves as I/O port. Lower order address and data bus signals are multiplexed using this port.
Pin 40 − this pin is used to provide power supply to the circuit.
8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or output. Hence, total 32 input/output pins allow the microcontroller to be connected with the peripheral devices.
Pin configuration, i.e. the pin can be configured as 1 for input and 0 for output as per the logic state.
Input/Output (I/O) pin − All the circuits within the microcontroller must be connected to one of its pins except P0 port because it does not have pull-up resistors built-in.
Input pin − Logic 1 is applied to a bit of the D register. The output of transistor is turned off and the other pin remains connected to the power supply voltage over a pull-up resistor of high resistance.
Port 0 − The P0 (zero) port is characterized by two functions −
When the external memory is used then the lower address byte (addresses A0A7) is applied on it, else all bits of this port are configured as input/output.
When P0 port is configured as an output then other ports consisting of pins with built-in pull-up resistor connected by its end to 5V power supply, the pins of this port have this resistor left out.
Input Configuration
If any pin of this port is configured as an input, then it acts as if it “floats”, i.e. the input has unlimited input resistance and in-determined potential.
Output Configuration
When the pin is configured as an output, then it acts as an “open drain”. By applying logic 0 toa port bit, the appropriate pin will be connected to ground (0V), and applying logic 1, the
external output will keep on “floating”.In order to apply logic 1 (5V) on this output pin, it is necessary to build an external pullup resistor.
Port 1
P1 is a true I/O port as it doesn’t have any alternative functions as in P0, but this port can be configured as general I/O only. It has a built-in pull-up resistor and is completely compatible with TTL circuits.
Port 2
P2 is similar to P0 when the external memory is used. Pins of this port occupy addresses intended for the external memory chip. This port can be used for higher address byte with addresses A8-A15. When no memory is added then this port can be used as a general input/output port similar to Port 1.
Port 3
In this port, functions are similar to other ports except that the logic 1 must be applied to appropriate bit of the P3 register.
Pins Current Limitations
When pins are configured as an output (i.e. logic 0), then the single port pins can receive a current of 10mA.
When these pins are configured as inputs (i.e. logic 1), then built-in pull-up resistors provide very weak current, but can activate up to 4 TTL inputs of LS series.
If all 8 bits of a port are active, then the total current must be limited to 15mA (port P0:
26mA).
If all ports (32 bits) are active, then the total maximum current must be limited to 71mA.
INTERRUPT OF 8051 MICROCONTROLLER
Interrupts are the events that temporarily suspend the main program, pass the control to the external sources and execute their task. It then passes the control to the main program where it had left off.
8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt can be enabled
or disabled by setting bits of the IE register and the whole interrupt system can be disabled by clearing the EA bit of the same register.
Steps in executing an interrupt
Upon receiving the interrupt signal the Microcontroller , finish current instruction and saves the PC on stack
Jumps to a fixed location in memory depending on type of interrupt
Starts to execute the interrupt service routine until RETI (return from interrupt)
Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get pop PC from stack
Each interrupt has a specific place in code memory where program execution (interrupt service routine) begins.
External Interrupt 0: 0003h
Timer 0 overflow: 000Bh
External Interrupt 1: 0013h
Timer 1 overflow: 001Bh
Serial : 0023h
Timer 2 overflow(8052+) 002bh
IE (Interrupt Enable) Register
This register is responsible for enabling and disabling the interrupt. EA register is set to one for enabling interrupts and set to 0 for disabling the interrupts. Its bit sequence and their meanings are shown in the following figure.
EA - It disables all interrupts. When EA = 0 no interrupt will be acknowledged and EA = 1 enables the interrupt individually.
ES - Enables/disables serial port interrupt.
ET1 - Enables/disables timer1 overflow interrupt.
EX1 - Enables/disables external interrupt1.
ET0 - Enables/disables timer0 overflow interrupt.
EX0 - Enables/disables external interrupt0.
IP (Interrupt Priority) Register
We can change the priority levels of the interrupts by changing the corresponding bit in the Interrupt Priority (IP) register as shown in the following figure.
A low priority interrupt can only be interrupted by the high priority interrupt, but not interrupted by another low priority interrupt.
If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served.
If the requests of the same priority levels are received simultaneously, then the internal polling sequence determines which request is to be serviced.
PS - It defines the serial port interrupt priority level.
PT1 - It defines the timer interrupt of 1 priority.
PX1 - It defines the external interrupt priority level.
PT0 - It defines the timer0 interrupt priority level.
PX0 - It defines the external interrupt of 0 priority level.
TCON register specifies the type of external interrupt to the microcontroller.
8051 MEMORY ORGANIZATION
The 8051 microcontroller's memory is divided into Program Memory and Data Memory.
Program Memory (ROM) is used for permanent saving program being executed, while Data Memory (RAM) is used for temporarily storing and keeping intermediate results and variables.
Program Memory (ROM)
Program Memory (ROM) is used for permanent saving program (CODE) being executed.
The memory is read only. Depending on the settings made in compiler, program memory
may also use to store constant variables. The 8051 executes programs stored in program memory only. code memory type specified is used to refer to program memory. 8051 memory organization allows external program memory to be added.
Internal Data Memory
Up to 256 bytes of internal data memory are available depending on the 8051 derivative.
Locations available to the user occupy addressing space from 0 to 7Fh, i.e. first 128 registers and this part of RAM is divided in several blocks. The first 128 bytes of internal data memory are both directly and indirectly addressable. The upper 128 bytes of data memory (from 0x80 to0xFF) can be addressed only indirectly. Since internal data memory is used for CALL stack also and there is only 256 bytes splited over few different memory areas fine utilizing of this memory is crucial for fast and compact code.
Memory block in the range of 20h to 2Fh is bit-addressable, which means that each bit being there has its own address from 0 to 7Fh. Since there are 16 such registers, this block contains in total of 128 bits with separate addresses ( Bit 0 of byte 20h has the bit address 0, and bit 7 of byte 2Fh has the bit address 7Fh).
Three memory typesspecifies can be used to refer to the internal data memory: data, idata, and bdata.
External Data Memory
Access to external memory is slower than access to internal data memory. There may be up to 64K Bytes of external data memory. Several 8051 devices provide on-chip XRAM space that is accessed with the same instructions as the traditional external data space. This XRAM space is typically enabled via proper setting of SFR register and overlaps the external memory space. Setting of that register must be manually done in code, before any access to external memory orXRAM space is made.
The mikroC PRO for 8051 has two memory typesspecifies that refers to external memory space: xdata and pdata.
SFR Memory
The 8051 provides 128 bytes of memory for Special Function Registers (SFRs). SFRs are bit, byte, or word-sized registers that are used to control timers, counters, serial I/O, port I/O, and peripherals.
8051 TIMER/COUNTER
8051 Timer/Counter Two internal Timers/Counters 16-bit timer/counter Timer uses system clockas source of input pulses Counter uses external input pulses from port 3 (T0,T1) If associatedinterrupt is enabled, when count overflow an interrupt is generated Registers TH0, TL0 :timer/counter register of timer 0 TH1, TL1 : timer/counter register of timer 1
TMOD: ModeSelect register,TCON: Control Register
TIMER
Set the initial value of registers
Start the timer and then the 8051 counts up.
Input from internal system clock (machine cycle)
When the registers equal to 0 and the 8051 sets a bit to denote time out
Counter
Count the number of events
Show the number of events on registers
External input from T0 input pin (P3.4) for Counter 0 External input from T1 input pin (P3.5) for Counter 1 External input from Tx input pin.
We use Tx to denote T0 or T1.
TMOD REGISTER
Both Timer 0 &Timer 1 use the same Mode register TMOD
It is an-8-bit register .The lower 4-bits are meant for
Timer 0 &the upper 4-bits are meant for Timer 1
It is not bit addressable.
It is used similar to any other register of 8051. For ex:
MOV TMOD, #21H
Every timer has a mean of starting and stopping.
GATE=0
Internal control
The start and stop of the timer are controlled by way of software Set/clear the TR for start/stop timer
SETB TR0 CLR TR0 GATE=1
External control
The hardware way of starting and stopping the timer by software and an external source.
Timer/counter is enabled only while the INT pin is high and the TR control pin is set (TR).
C/T: Timer or counter selected cleared for timer operation (input from internal system clock). Set for counter operation (input from Tx input pin).
M1, M0:Used for mode selection, because the Timers of 8051 can be set in 4-different modes.
M1 M0 Mode Operation
0 0 0 13-bit timer mode 8-bit THx + 5-bit TLx (x= 0 or 1) 0 1 1 16-bit timer mode 8-bit THx + 8-bit TLx
1 0 2 8-bit auto reload 8-bit auto reload timer/counter; THx holds
a value which is to be reloaded into TLx each time it overflows.
1 1 3 Split timer mode
TCON REGISTER
Timer control register TMOD is a 8-bit register which is bit addressable and in which Upper nibble is for timer/counter,
lower nibble is for interrupts
TR (Timer run control bit)
TR0 for Timer/counter 0; TR1 for Timer/counter 1.
TR is set by programmer to turn timer/counter on/off.
TR=0 : off (stop) TR=1 : on (start)
TF (timer flag, control flag)
TF0 for timer/counter 0; TF1 for timer/counter 1.
TF is like a carry. Originally, TF=0. When TH-TL roll over to 0000 from FFFFH, the TF is set to 1.
TF=0 : not reach TF=1: reach
If we enable interrupt, TF=1 will trigger ISR.
Operation Modes Mode 0
13-bit counter, an interrupt is generated when counter overflows.
It takes 8192 input pulses to generate the next interrupt.
Mode 1
16-bit counter, similar to mode 0, but take 65536 input pulses Mode 2
8-bit reload
TL1 operates as timer/counter
TH1store a number and reload to TL1 when overflows Mode 3
Timer 1 is inactive, hold count value.
TL0 and TH0 operate as two separate 8-bit timer/counter TL0 control by timer 0 control bits
TH0 operate as timer driven by system clock, prescaled by 12 and cause timer 1 interrupt Overflows
Working of Timer Mode 1
let us consider timer 0 as an example.
16-bit timer (TH0 and TL0)
TH0-TL0 is incremented continuously when TR0 is set to 1.
8051 stops to increment TH0-TL0 when TR0 is cleared.
The timer works with the internal system clock. In other words, the timer counts up each machine cycle.
When the timer (TH0-TL0) reaches its maximum of FFFFH, it rolls over to 0000, and TF0 is raised.
Programmer should check TF0 and stop the timer 0.
1. Choose mode 1 timer 0 MOV TMOD,#01H
2. Set the original value to TH0 and TL0.
MOV TH0,#FFH
MOV TL0,#FCH
3. You better to clear the TF: TF0=0.
CLR TF0
4. Start the timer.
SETB TR0 Steps of Mode 1
The 8051 starts to count up by incrementing the TH0-TL0 TH0-TL0= FFFCH,FFFDH,FFFEH,FFFFH,0000H
• When TH0-TL0 rolls over from FFFFH to 0000, the 8051 set TF0=1.
TH0-TL0= FFFE H, FFFF H, 0000 H (Now TF0=1)
• Keep monitoring the timer flag (TF) to see if it is raised.
AGAIN: JNB TF0, AGAIN
• Clear TR0 to stop the process.
CLR TR0
• Clear the TF flag for the next round.
CLR TF0
8051- SERIAL COMMUNICATION
Types of Serial communications
The 8051 has two pins for transferring and receiving data by serial communication.
These two pins are part of the Port3(P3.0 &P3.1)
These pins are TTL compatible and hence they require a line driver to make them RS232 compatible
Max232 chip is one such line driver in use.
Serial communication is controlled by an 8-bit register called SCON register; it is a bit addressable register.
Interfacing to PC
SCON (Serial control) register
These two bits of SCON register determine the framing of data by specifying the number of bits per character and start bit and stop bits. There are 4 serial modes.
SM0 SM1
0 0 Serial Mode 0
0 1 Serial Mode 1, 8 bit data,1 stop bit, 1 Start bit 1 0 Serial Mode 2
1 1 Serial Mode 3
REN (Receive Enable) also referred as SCON.4.When it is high; it allows the 8051 to receive data on the RxD pin. So to receive and transfer data REN must be set to 1.When REN=0, the receiver is disabled. This is achieved as below
SETB SCON.4
& CLR SCON.4
TI (Transmit interrupt) is the D1 bit of SCON register. When 8051 finishes the transfer of 8-bit character, it raises the TI flag to indicate that it is ready to transfer another byte. The TI bit is raised at the beginning of the stop bit.
RI (Receive interrupt) is the D0 bit of the SCON register. When the 8051 receives data serially, viaRxD, it gets rid of the start and stops bits and places the byte in the