MSP430 Microcontroller Workshop

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MSP430 Microcontroller Workshop

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Important Notice

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Revision History

March 2010 – Revision 1.0

July 2010 – Revision 1.1 Roadmap and portfolio slide update July 2010 – Revision 1.2 Name change

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Introduction

This module will cover the MSP430 architecture, instruction set, and development tools. In the lab exercise Code Composer Studion will be installed and we will verify that the hardware and software has been configured properly.

Agenda

Introduction to the MSP430F5xx 5xx Active & Low Power Mode

Operation

A Mixed-Signal Application Example Using Hardware Timers to Conserve

Power

A Fully-optimized ADC12 Routine MSP430 Tools, Resources and

Conclusion

2

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Module Topics

Introduction ... 1-1 Module Topics... 1-2 Introduction ... 1-3 TI Processor Portfolio... 1-3 5xx Summary... 1-4 MSP430 Generations... 1-5 MSP430 Roadmap... 1-6 Orthogonal CPU ... 1-7 Unified Clock System... 1-7 5xx Operating Modes ... 1-8 Operating Range ... 1-8 Memory Map ... 1-9 SYS Module ... 1-9 GPIO...1-10 Port Map Module...1-10 Universal Serial Communications Interface ...1-11 LCD_B and AES128 ...1-11 USB ...1-12 CC430...1-12 Embedded Emulation ...1-13 Block Diagram...1-14 Experimenter’s Board...1-14 Code Composer Studio 4.1 ...1-15 Community Support ...1-15

Lab 1: Setting up the Software and Hardware...1-17

Objective ...1-17 Hardware / Software Requirements...1-17 Procedure...1-18

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Introduction

TI Processor Portfolio

TI Embedded Processing Portfolio

3 5xx Gen Summary… 32-bit ARM Cortex™-M3 MCUs 16-bi t ultra-low power MCUs DSP DSP+ARM ARM Cortex-A8 MPUs Stel laris® ARM®_Cortex™-M3 MSP430™ Sitara™ ARM®Cortex™-A8 & ARM 9 C6000™ DaVi nci™ video pr oc essors TI Embedded Processors

Digital Si gnal Processors (DSPs) Microcontroll ers (MCUs) ARM®-Based Processors

O MAP™

Software & Dev. Tools

U p to 100 MHz

Flash 8 KB to 256 KB

USB, ENET MAC +PHY CAN,

AD C, PWM, SPI Connectivity, S ecurity, Motion Control, HM I, Industrial Automation $ 1.00 to $8.00 300MHz to >1GH z C ache, RAM, R OM USB, C AN, PCIe, EMAC Industrial computing,

POS & portable data terminals $5.00 to $20.00 Up t o 25 MHz Flash 1 KB to 256 K B Analog I/O, A DC LCD, USB, RF Measurement, Sensing, General Purpose $0.25 to $9.00 300MHz to >1Gh z +Accelerato r Cache RAM, ROM USB, ENET, PC Ie, SATA , SPI Floating/Fixed Poi nt Video, Audio, Voice, Security, Conferencing $5.00 to $200.00 32-bit real-time MCUs C2000™ Delfino™ Piccolo™ 40MHz to 300 MHz Flash, RAM 16 KB to 512 K B PWM, ADC , CAN, SPI, I2_C Motor Control, Digital Power, Lighting, Ren. Enrgy

$1.50 to $20.00 Ultra Low pow er DSP C5000™ Up to 300 MHz +Accelerator Up to 320KB RA M U p to 128KB ROM USB, AD C McB SP, SPI, I2_C Audio, V oice Medical, Biometrics $3.00 to $1 0.00 Multi-core DSP C6000™ 24.000 MMACS Cache R AM, ROM SRIO, EMAC DMA, PC Ie Telecom test & meas,

media gateways, base stations $40 to $200.00

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5xx Summary

5xx Generation Summary

Ultra-Low Power

230 µA/MHz

1.9 µA standby mode

Wake up from standby in < 5 µs

Increased Performance

Up to 25 MHz

8 MHz across entire operating range (1.8 - 3.6 V)

1.8V ISP flash erase & write

Fail-safe, flexible clocking system

Innovative Features

Integrated LDO, BOR, WDT+, RTC

Multi-channel DMA supports data movement in standby mode

More connectivity: USB, RF

AES encryption, RTC on backup battery

User-defined Bootstrap Loader

Industry-leading code density 4

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MSP430 Generations

1xx

2xx

4xx

5xx

Basic Clock System Basic Clock System + FLL, F LL + Unified Clock System UCS

Cor e voltage same as supply voltage

Core voltage same as supply voltage

Progr ammable Cor e Voltage with integr ated PMM 16-bit CPU 16- bit CPU, CPUX 16-bit CPU, CPU X 16-bit CPUXV2 GPIO GPIO w/ pull- up and

pull- down

GPIO GPIO w/pull- up and pull-down, drive str ength

N/A N/A N/A CRC 16

Software RT C Software R TC Software RT C with Basic

Timer, Basic Timer + RTC T rue 32-bit RTC w/Alarms USART USCI, USI USAR T, USCI USCI, USB, RF DMA up to 3-ch DMA up to 3-ch DMA up to 3-ch DMA up to 8-ch MPY16 MPY16 MPY16, MPY32 MPY32 ADC10,12 ADC10,12 ADC12 ADC12_A 4- wir e JT AG 4- wir e JT AG, some devices with

Spy-Bi- Wire

4-wire JTAG 4- wir e JT AG and Spy- Bi-Wire

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MSP430 Generations

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Roadmap…

Category 2xx 4xx 5xx

CPU Clock (max) 16MH z 8MHz 25MH z Active Cur rent

(@ 3.0V, typical) 515u A @ 1MH z 4.2mA @ 8MH z 9.1mA @ 16 MHz 6 00uA @ 1MHz 4 .8m A @ 8MHz N /A 290u A @ 1 MHz 1.84mA @ 8 MHz Æ23 0 u A/MHz 8.90mA @ 2 5MHz

120KB / 8KB ( Flash / RAM) 120KB / 8KB ( Flash / RAM) 256KB / 16KB ( Flash / RAM) Wake-up T ime Fr om LPM3 1us 6us 5us

Standby LPM3 Cur rent 0.9 – 1.1uA 1.1 – 2.5uA 1.9uA ( RTC, WDT , SVS enabled)

LPM4 Cur rent 0.1uA 0.1uA 1.2uA ( LPM4) / 0.1uA ( LPM4.5) Flash ISP Minimu m DV_CC 2.2V 2.7V 1.8V

Por t I/O Inter rupt Capability P1/P2 P1/P2 P1/P2

Some devices also P3/P4 Pr og. Port Pin Dr ive Str ength N/A N/A All por t pins

Pr og. Pull-ups / Pull- downs All por t pins N/A All por t pins 12-bit A/D Inter nal Refer ence

Curr ent

500 uA 500 uA 100 uA* 12-bit A/D Active Conver sion

Curr ent 800 uA 800 uA 150 uA* Available MCLK Sources DCO

LFXT1 XT 2 (if available) VLO F LL LF XT 1 XT2 ( if available) F LL LFXT 1 / XT 1 UCS XT2 ( if available) VLO R EF O Available FLL Reference Clocks N/A LF XT 1 LFXT1, REFO, & XT2 ( if pr esent) * 2xx, 4xx – AD C12 ; 5xx - R EF & AD C12 _A

MSP430 Roadmap

100+ dev ic es 2xx-Catalog • 16 M Hz • 120 kB F lash • 8 kB RAM • 500 nA Stand by • 1.8 – 3. 6V 75 + de vices F = Flash C = ROM FR = FRAM 10 0+ devices 4xx: L CD F23x0 ne ration Produ ction Developm en t Device F23x-F24x F261x F241x F20xx F21x1 F 21x2 F22xx F13x-F14x F15x-F16x F541x F543x F44x Fx43x F/CG461x Fx47x F 471xx The Ne w Ge 5xx-6xx •25M Hz •256 kB Fl ash •16 kB RAM •1. 8 – 3.6V •FRAM , US B, RF •6xx: L CD Control ler •230 uA/M Hz FR57xx FRAM CC430 RF F550x USB F552x USB F51x2 Lighting F23x0 F/C11xx F12xx L 092 0.9V Native F 53xx Gen Purpose F6/563x BGM, Catalog

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Orthogonal CPU

5xx MSP430Xv2 Orthogonal CPU

C-compiler friendly

Memory address range increased to 1MB

CPU registers increased to 20-bits

Address-word instructions Direct 20-bit CPU register access

Atomic (memory-to-memory) instructions

Instruction compatiblewith previous CPU

Cycle count optimization

Extension word allows all instructions Direct access to 1MB address space

Bit, byte, word and address-word data

Repeat instruction function

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UCS…

Unified Clock System

Six independent clock sources

Low Freq LFXT1 32768 Hz crystal VLO 10 kHz REFO 32 kHz High Freq XT1 4 – 32 MHz crystal XT2 4 – 32 MHz crystal

DCO FLL mul ti ple of reference clock

FLL references are divisible LFXT1 / XT1

REFO

XT2

ACLK / SMCLK / MCLK tree is

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5xx Operating Modes

SVS protection for just 200 nA Active Mode – 230 uA/MHz

CPU acti ve

Fast Peri pher al s Enabled

32 kHz Per ipheral s Enabled - RTC

LPM0 – 70 uA CPU di sabled

Fast Peri pher al s Enabled

32 kHz Per ipheral s Enabled – RTC

LPM3 – 1.9 uA CPU di sabled

Fast Peri pher al s Di sabled

32 kHz Per ipheral s Enabled

RT C, Watchd og & SVS pro tectio n

LPM4 – 1.2 uA All clocks disabl ed

Wake on interrupt

LPM4.5 (LPM5) – 100 nA Regul ator & al l clocks disabled

No RAM retenti on

BOR on nRST/ NMI or Port I/ O

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Operating Range…

Operating Range

5xx Voltage vs. Frequency Operating Range

25MHz peak performance

More performance across VCC range

Flash ISP @ min. VCC

8MHz @ min. VC C Up to 25MHz @ 2.4V-3.6V Programmable VCORE maximizes power efficiency Lowering V_CCor V_CORE reduces system current

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Memory Map

5xx Memory Map

Page-free 20-bit addressing

User-definable Boot Strap Loader

RAM starts at 0x1C00

Always a contiguous

block

Beginning of MAIN flash

moves according to RAM

Vector table starts at 0xFF80

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SYS…

SYS Module

5xx Peripherals – The SYS Module

Reset Interrupt Vector Generator Æ

Generates a constant that maps to the cause of last reset

Simplifies reset handling

Manages non-maskable interrupts

Reset events

NMI’s split into SYSNMI & UNMI

SYSNMI’s have higher priority

Separate interrupt vectors

Factory application data is

Brownout (BOR) (highest priorit y) RST/NMI (POR)

DoBO R (BO R) Port_wak eup (BO R) Security violat ion (BO R) SVSL (POR)

SVSH (PO R) SVML_O VP (PO R) SVMH_OVP (POR) DoPO R (PO R) WDT time out (PUC) WDT k ey v iolation (PUC)

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GPIO

5xx Peripherals – GPIO

Initial state of GPIO pins is a digital input

Port registers allow for different configurations

PxDIR – direction (input vs output)

PxREN – enables internal pull-up/pull-down resistors (input)

PxDS – enables additional drive strength (output)

Select ports have interrupt capabilities

PxIE – Interrupt enable

PxIES – Interrupt edge select

PxIFG – Interrupt flag registers

GPIO functionality is multiplexed with analog

and digital peripheral functions

PxSEL – Peripheral function select

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Port Map Module…

Port Map Module

5xx Peripherals – Port Map Module

Port mapping allows for additional digital signals to be mapped to one or several output pins.

PM_xxx denotes a por t-mappable signal

Datasheet sp ecifies whi ch por ts can be mapped

By default, single configuration per PUC reset

Port Mapp ing Reconfi gure bit (PMRECNFG ) al low s for runtim e re-configur ations

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Universal Serial Communications Interface

USCI - New standard MSP430 serial interface

Auto clock start from any low power mode

Two independent communication blocks

Asynchronous communication modes

UART standard and multiprocessor protocols

UART with automatic Baud rate detection (LIN support)

Two modulators support n/16 bit timing

IrDA bit shaping encoder and decoder

Synchronous communication modes

SPI (Master & Slave modes, 3 & 4 wire)

I2C (Master & Slave modes) UxRXBUF URXD SMCLK UCLKI ACLK SM CLK

Recei ver Shif t Reg ister Baud -Rate Gener ator

Tran smit Sh ift Reg ister UxTXBUF

Clock Phase and Polarity UCLK UTXD SOM I SIMO ST E 16 LCD and AES…

LCD_B and AES128

5xx Peripherals – LCD_B & AES128

LCD distinguishes 6xx from 5xx

Static, 2-, 3- or 4-mux displays

Supports up to 196 LCD segments

Blinking of individual segments

Regulated charge pump

Software-driver contrast control

Integrated drivers to decouple LCD load from the bias generation

Encryption and decryption according to AES FIPS PUB 197 with 128-bit key

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USB

5xx + USB

Single-chip USB solution

Just add USB connector & TI-supplied USB API software

for the most common device classes (CDC/HID/MSC)

USB + analog + ultra-low-power

ESD _{TPD 2E00 1DRL} ESD Protection Diode Arr ay 18 CC430… Serial Comms Comparat or 12-bit ADC Timers RAM CPU RTC CRC₁₆ DMA 32x32_MPY Power Supply & Superv is ion

Flash Clock s USB Module +3.3V V_USB DVCC +5V V BUS PUR D-D+ 4MHz

CC430

Low Power RF IC Radi o Frequency

5xx + Low-Power RF – The CC430

CC430 Low-power RF SoC Supports: 300-348MHz, 387- 464MHz and 779-928MHz MSP430 5xx MCU Low Power < 1 GHz RF Transceiver MSP430 MCU

Appl ication & Protocol processor

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Embedded Emulation

5xx Embedded Emulation

Used for in-system programming and emulation

JTAG access can be “locked” using SW – no fuse

JTAG pins serve as 4 x pin GPIO port (Port J)

Support for both 4-wire and 2-wire “Spy-Bi-Wire”

Compatible with existing MSP430 tools

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Emulation…

5xx Embedded Emulation

Simplifies in-system debugging and reduces

development time

Up to 8 hardware breakpoints with complex triggering capabilities

40-bit wide CPU cycle counters in hardware

JTAG Mailbox system provides direct interface to the CPU during…

Debugging (Run-time data UART – RTDX)

Programming / Test

State Storage: non-intrusive trace buffer for

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Block Diagram

MSP430F5438A Block Diagram

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MSP-EXP430F5438…

Experimenter’s Board

MSP-EXP430F5438

Easy power select

USB, JTAG , Battery

USB communication

Microphone

Filtered PWM audio output

Active, selectable gain

Head phone com pati bility

2-axis accelerometer

Dot-matrix LCD (138x110)

I ntegrated backl ight

1 x 5-direction switch

2 x push-button switches

RF Interface

CCxxxx EVMs

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Code Composer Studio 4.1

Code Composer Studio v4.1:

A single development

platform for all TI processors

Enhancements:

Speed

Code size improvements

Auto-updating

License manager

Support for all TI MCUs

Only $495for MCU Edition

FREE 16KB-limited edition

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Community Support…

Community Support

Videos, Blogs, Forums

Extensive community support and idea exchange

Global customer support

http://e2e.ti.com

Growing collection of technical wiki articles

Tips & tricks, common pitfalls, and design ideas

http://wiki.msp430.com

Extensive Community Support

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Lab 1: Setting up the Software and Hardware

Objective

The objective of this lab exercise is to install Code Composer Studio and verify that the hardware and software has been configured properly. Also, we will cover some of the basic features of the development tools using a simple program running on the MSP430F5438A. These development tools will be used with all of the following lab exercises in this workshop.

Hardware / Software Requirements

• PC running Windows XP or greater

• Code Composer Studio 4.1

• MSP-FET430UIF with JTAG ribbon cable and USB cable

• MSP-EXP430F5438 board with MSP430F5438 device

• Labs and solutions files

Lab_1: Blink the LED

FET

Blink the LED

with C code

running on the

MSP430F5438A

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Procedure

If you’ve already completed the installation steps that were emailed to you before the workshop, skip to step 9.

Download and Install Code Composer Studio 4.1

1. Click on this link to begin the Code Composer Studio download process. Download the latest DVD image of Code Composer Studio. You will need to agree to the export conditions and you will be emailed a link to the installation zip file. Click on the link and save the zip file to your desktop. Unzip the file into a folder on your desktop named Setup CCS. You can delete the zip file and the Setup CCS folder when the installation has completed.

2. Disconnect any evaluation board or FET that you have connected to your PCs USB port(s).

3. Open the

Setup CCS

folder on your desktop and double-click on the file named

setup_CCS_n.n.n.n.exe

.

4. Follow the instructions in the Code Composer Studio installation program. Select

the

Platinum Edition

for installation when the

Product Configuration

dialog

window appears. Click

.

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5. In the

Choose ISA

dialog, make sure that only the

MSP430

checkbox is selected.

Click

.

In the

Select Components

dialog,

uncheck

the

Target Content

and

Emulators

checkboxes then check the

MSP430 USB FET

checkbox and click

.

Click

Next in the Start Copying Files dialog.

The installation should take less than 10

minutes to complete.

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Driver Installation

6. Download the workshop installation files from this link on the MSP430 One Day Work-shop Wiki site. Unzip the file to your desktop (the folder name is MSP430).

7. In the unzipped MSP430 folder on your desktop, open the USB drivers folder.

Double-click on setup.exe. Follow the wizard steps until it completes. Then, using Windows Ex-plorer, navigate to C:\Program Files\Texas Instruments Inc\TUSB3410 Single Driver Installer\DISK1 and double-click on setup. Follow the wizard steps until the driver in-stallation completes.

Lab File Installation

8. Back in the unzipped MSP430 folder on your desktop, open the Labs folder and

double-click on 5xx_ODW.exe. Leave the unzip directory as C:\5xx_ODW and double-click Unzip. When the process completes, click Close. The labs have now been installed in

C:\5xx_ODW.

Hardware Setup

9. Connect the USB cable to the MSP-FET430UIF port marked USB and that the other end

of the cable to your computer’s USB port. Your computer should recognize the new USB device.

10. Next, connect the ribbon cable to the MSP-FET430UIF port marked Target and the

other end to the JTAG emulation debug port on the MSP-EXP430F5438 Experimenter’s Board.

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11. The MSP-EXP430F5438 Experimenter’s Board has several jumpers that control power to the board:

JP4 – pins 5-6

SW1 JP2 JP3 JP1

Be sure that the jumpers are set as follows:

• JP1 – 430 PWR provides power to the MSP430F5438A (ON)

Used to measure current consumption of the MSP430F5438A • JP2 – SYS PWR provides power to the entire MSP-EXP430F5438 board (ON)

Used to measure current consumption of the entire board • JP3 – RF PWR provides power to the RF connector headers (ON)

• JP4 – USB RST enable for USB chip (ON)

• SW1 – FET/USB/BATT power supply switch (FET position) FET: Power board from FET interface

USB: Power board from USB interface BATT: Power board from batteries

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Start Code Composer Studio

12. On your PC desktop you should have a shortcut that looks like this:

Double-click the shortcut to start Code Composer Studio 4.1. As CCS loads, the following splash screen will be displayed:

After a few moments, the Workspace Launcher window will appear. In the Workspace window, enter C:\ 5xx_ODW\workspace and click the OK button on the lower right.

This will create a workspace folder in that location. All of the workshop’s lab project folders will be added to this location as we work on them.

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13. If you are prompted to review and install updates, click No. When the license dialog appears, select Evaluate Code Composer for 30 days and click OK.

When the Welcome screen appears, close it by clicking on the CCS emblem in the upper right corner.

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Create a New Project

14. On the menu bar, click File Æ New Æ CCS Project. When the New CCS Project dialogue appears, name the project Lab_1 and click Next. Note that this location will be under the workspace folder.

In the Select a type of project window, change the project type to MSP430 and click Next.

In the Additional Project Settings window, make no changes and click Next.

In the Project Settings window, change the Device Variant to MSP430F5XXX and

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Understanding the IDE Display

15. CCS 4.1 is a highly customizable tool, but your first view of it should look like below:

If the Cheat Sheets pane is open on the right, close it by clicking the X on the tab. The left-hand pane is the Project pane. All of the components; libraries, source files, settings, etc. that comprise a project are displayed here. The middle pane is the

Workspace pane. When you are editing, the Eclipse editor will be seen here, along with tabs to the files being edited. The Outline pane, on the right, displays C/C++ file elements, like structures, etc.

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Create and Add a Source File

16. Right-click in the Project pane and select New Æ Source File. When the New Source File window appears, name the Source File Blink_LED.c and click Finish. In the Project pane you will see that Blink_LED.c is now added to the project and that the file is open for editing in the Workspace pane. (If it is not open for editing, double-click on Blink_LED in the Project pane.)

In the Blink_LED.c editor window that appears, type the following code, or you can cut/paste it from the Blink_LED.txt file included in the Lab_1 folder.

To cut/paste, select File Æ Open File… from the menu bar. Navigate to:

C:\5xx_ODW\Lab_1, select Blink_LED.txt, and then click Open. Cut/Paste to the Blink_LED.c editor window.

#include "msp430x54x.h"

void main(void) {

WDTCTL = WDTPW + WDTHOLD; // Hold WDT for clock/port config

P1OUT = 0x00;

P1DIR |= BIT0; // Enable LCD output

WDTCTL = WDT_ADLY_1000; // WDT source by ACLK, 1s interval

SFRIE1 |= WDTIE; // Enable WDT interrupt

__enable_interrupt(); // Enable global interrupts

}

// Watc

#pragma vector = WDT_VECTOR

hdog Timer interrupt service routine

__interrupt void WDT_ISR(void) {

SFRIFG1 &= ~WDTIFG;

P1OUT ^= 0x01; // Toggle P1.0 using exclusive-OR

}

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Download and Run the Program

17. Click the Debug button (not the Debug perspective button). Clicking this button

will compile the source file in your project and download the executable to the flash memory of the MSP430F5438A.

A Progress Information window will open and inform you of the status of the assembly and download.

Note: If the FET firmware does not match the CCS version, CCS will automatically

prompt you to update it – if you are prompted, select Update. 18. You should now have a screen that looks something like this:

The buttons on the top-left that look like this:

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Halt Debugging and Close the Project

19. Click the Terminate All button to halt the program, terminate the debugger

session and return to the editor view.

20. Right-click on Lab_1 in the project pane and select Close Project.

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Introduction

This module will explore the ultra-low power capabilities of the MSP430 architecture. The Power Management Module (PMM) and Unified Clock System (UCS) will be discussed along with techniques that are used to minimize power consumption. In the lab exercise we will experiment with the various active and low power modes.

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Module Topics

Active and Low Power Operation... 2-1

Module Topics... 2-2 Active and Low Power Operation ... 2-3

Ultra-Low Power Best Practices... 2-3 Unified Clocking System (UCS) ... 2-5 Power Management Module (PMM)... 2-7 Interrupts and the Stack ... 2-9 Intrinsics ... 2-9 Fail-Safe Behavior...2-10 Available Oscillators ...2-10 Overview of Lab2 Exercise ...2-11

Lab 2: Active and Low Power Mode Operation ...2-12

Objective ...2-12 Procedure...2-14

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Active and Low Power Operation

Ultra-Low Power Best Practices

Ultra Low Power (ULP) Operation Best Practices

Power-efficient MSP430 apps:

Minimize instantaneous current draw Maximize time spent in low power modes

The MSP430 is inherently low-power, but your

design has a big impact on power efficiency

Proper low-power design techniques make the

difference

28

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ULP Operation Best Practices

Power draw increases with…

Vcc

CPU clock speed (MCLK) Temperature

Slowing MCLK reduces instantaneous power, but

usually increases active duty cycle

Power savings can be nullified

The ULP ‘sweet spot’ that maximizes performance for the minimum current consumption per MIPS: 8 MHz MCLK

Full operating range (down to 1.8V)

5xx has integrated LDO with variable output voltage Optimize core voltage for chosen MCLK speed

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ULP Best Practices…

ULP Operation Best Practices

Digital input pins subject to shoot-through current

Input voltages between VIL and VIH cause shoot-through if input is allowed to “float” (left unconnected)

Port I/Os should

Driven as outputs

Be driven at Vcc/ground by an external device

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Unified Clocking System (UCS)

ULP Clock Control:

Unified Clocking System (UCS) Defaults

FLLREFCLK = XT1CLK ACLK = XT1CLK MCLK = DCOCLKDIV SMCLK = DCOCLKDIV DCOCKLDIV = DCOCLK / 2 DCO_freq ~= 2 MHz, so MCLK_freq ~= 1 MHz SMCLK_freq ~= 1MHz 31

ULP Clock Control (FLL)…

ULP Clock Control:

The 5xx Frequency Locked Loop (FLL)

FLLREFCLK sources:

32 kHz internal REFO LFXT1 / XT1

crystal oscillator XT2 crystal oscillator

DCO frequency equation

f_DCO= (f_FLLREFCLK/ n) * (N + 1) * D n = FLLREFDIV

N = FLLN D = FLLD

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ULP Clock Control:

The 5xx Digitally Controlled Oscillator (DCO)

DCO ranges from 200 kHz – 60 MHz RSEL bits select the range

DCO bits set one of 32 taps in each range MOD bits mix two frequencies

f_DCOand f_DCO+1to produce DCOCLK

33

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Power Management Module (PMM)

Integrated Low Dropout (LDO) regulator: VCC? VCORE

V_COREis programmable to four levels Brown Out Reset (BOR) is always ON PMM is password protected

Unlock: PMMCTL_H = 0xA5

Lock: PMMCTL_H = 0x00

Integrated Supervision and Monitoring

Monitoringprovides interrupts on low voltage condition

Supervisiongenerates Power On Reset (POR) on low voltage condition

Vcc domain is referred to as the high-side (SVSH, SVMH)

Core voltage domain is referred to as the low-side (SVSL, SVML)

Accurate voltage supervision

200nA - Normal Performance Mode (20 us response time)

2 uA - Fast Performance Mode (2 us response time)

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V core…

Steps to Change V

_CORE

Increa sing the Core Voltage

1. Change the low-side monit ort hreshold

2. Change the core voltage level

3. Wait until the core voltage level is reached

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Voltage Supervision & Monitoring

Power on Def ault Mode

N orm al Per for mance Mode

+800 nA active curr ent c onsumption

0 nA LPM2 ,3,4 curr ent c onsumption

High -sid e Full Perfo rm ance Mod e

• High-s ide Full Perform ance Mode

• Low-side SVS / SVM disabled

• +4uA a ctive curre nt cons um ption

• +0uA LPM2,3,4 curre nt consumption

• Automatic high-s ide pr ote ction whe n CPU is active SVS / SVM d isabled

• SVS / SVM disa bled

• Ze ro-powe r BOR protec tion is ALWAYS ON

• 5 us wake up fr om LPM2,3,4

• +0 uA active & LPM 2,3 ,4 curr ent consumption

High -side Fast Perf ormance Mod e

•High-side Fas t Pe rformance Mode

•Low-side SVS / SVM disable d

•5 us wak eup from LPM2,3,4

•+4 uA active & LPM2,3,4 c ur rent cons um ption

•Autom atic high-side pr otec tion when CPU is a ctive

Maximum Rob ust ness

•Fas t Per for mance Mode

•5 us wa keup from LPM2,3 ,4

•+8 uA ac tiv e & LPMx curr ent c onsumption Cur rent 150 us wakeup from LPMx 5 us wakeup from LPMx 36 Entering LPMs…

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Interrupts and the Stack

Entering Interrupts

Any currently executing instruction is completed.

The PC, which points to the next instruction, is pushed onto the stack. The SR is pushed onto the stack.

The interrupt with the highest priority is selected

The interrupt request flag resets automatically on single-source flags. Multiple source flags remain set for servicing by software.

The SR is cleared. This terminates any low-power mode. Because the GIE bit is cleared, further interrupts are disabled.

The content of the interrupt vector is loaded into the PC; the program continues with the interrupt service routine at that address.

38

Intrinsics…

Intrinsics

Using Intrinsic Functions to

Program the Status Register (SR)

Intrinsic Functions: __bi c_ SR_reg iste r(LPM3 _bits); __bi c_ SR_reg iste r_on_ exit(LPM3 _bits); __bi s_ SR_reg iste r(LPM3 _bits + GIE); __bi s_ SR_reg iste r_on_ exit(unsign ed short a); __ge t_ SR_re giste r(void) ;

__ge t_ SR_re giste r_on _exit(void) ; __en able _interr upts( ) ;

__di sa ble_i nterrup ts( ); Other useful intrinsics:

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Fail-Safe Behavior

Fail-Safe Behavior & Clock Requests

LFXT1 reverts to REFO

HFXT1 & XT2 revert to DCO On startup, LFXT1 will fail

because quartz crystals are not instant-on

Clearing the fault flags allows expected default operation

Modules place clock requests to the system clocks

LPM3 entry can be prevented if a module requires SMCLK to operate properly

User must be aware of the clocks required in the system.

40

Available Oscillators…

Available Oscillators

ULP Review of Available Oscillators

Clock Frequency Precision Current Draw Crystal Required High-Frequency DCO 100kHz – 60MHz Low 60uA HFXT1/ XT2 4 - 32MHz High 260uA @ 12MHz X

MODOSC 5MHz n/a n/a

Low-Frequency

LFXT1 32kHz High 300nA X

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Overview of Lab2 Exercise

Lab2: Active & ULP Mode Operation

Learn and understand how two key modules (PMM & UCS) achieve ultra low power operation by measuring the power consumption of various Active and LPM3 scenarios Using an ammeter and measure the current through the PWR1 jumper

FET

42

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Lab 2: Active and Low Power Mode Operation

Objective

The objective of this lab exercise is to gain an understanding on how two key modules of the MSP430F5438A are used to achieve ultra-low power operation. The Power Management

Module (PMM) and Unified Clock System (UCS) will be configured and modified as we measure the typical average current consumption of the device in the following active and LPM3

scenarios:

• Active running at 8 MHz – initialize the FLL

• Active running at 25 MHz – change the COREV levels for greater than 8 MHz operation

• LPM3 REFO- enter LPM3 with default ACLK settings • LPM3 LFXT1 – handle oscillator faults to set LFXT1 ACLK

• LPM3 VLO – evaluate ultra-low power tradeoffs for oscillators at VLO ACLK

The LPM3 applications blink the LED on and off every 3 seconds. After you have verified that the application download and function, you can comment out the line P1OUT ^= ~BIT0; . This will allow you to measure the current without the spikes due to the LED.

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In the Active Running scenarios (first two in the box above) a function is called to provide a current consumption test. This test includes a mix of various MSP430 instructions (type I, II, JMP, emulations, etc.) and uses various MSP430 addressing modes. The function is called from C with the following code:

// Call active mode current consumption test ACTIVE_MODE_TEST();

ACTIVE_MODE_TEST ( ) is written in assembly and consists of the following:

.global ACTIVE_MODE_TEST .text

ACTIVE_MODE_TEST MOV #0x2000, R4 MOV #0x4, 0(R4) MOV &0x2000, &0x2002 ADD @R4, 2(R4) SWPB @R4+ MOV @R4, R5 IDD_AM_L1 ; run 8 times

XOR @R4+, &0x2020 DEC R5

JNZ IDD_AM_L1 JMP ACTIVE_MODE_TEST .end

- Code mixes with types of instructions: type I,II, JMP, emu - Code mixes with address modes

- Type of Instructions

# of instructions: 6+8*3 = 30

ALU inst: 2+2*8 = 18 -60%

Data Read inst: 4+1*8 = 12 -40%

Data Write inst: -40% Control/Jump : 8 -26%

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Procedure

Import CCS Project

1. Import the CCS project for this lab exercise by clicking: Project Æ Import Existing CCS/CCE Eclipse Project

Then in the Import dialog window click Browse and navigate to: C:\5xx_ODW\ Lab_2. Select Lab_2 in the Projects box, check the Copy projects into workspace checkbox and click Finish.

In the Project pane of CCS, click the plus sign (

+

) to the left of Lab_2 and notice the files are listed for the various low power measurement scenarios. Note that the ACTIVE_8_MHZ.c file is included in the build.

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Active Running at 8 MHz

In this scenario we will measure current consumption of the device in the active mode running at 8 MHz.

2. Be sure that Lab_2 is set as the [Active – ACTIVE_8_MHZ] build configuration. If

not, then right-click in the Project pane, select Active Build Configuration and left-click ACTIVE_8_MHZ.

3. Open ACTIVE_8_MHZ.c for editing and notice the following:

• halBoardInit( ) initializes the GPIO for minimum current consumptions and ultra-low power operation

• Init_FLL_Settle( ) selects the RSEL, DCO taps, delay for FLL to settle, and MCLK, SMCLK, ACLK sources

• For future reference:

Check out #include “hal_ucs.h”

Check the MSP430 application notes for hal_UCS and hal_PMM library

descriptions

4. Click the Debug button to assemble/compile and download the executable into the

device flash memory.

5. Click the Run button to run the program, then click the Terminate All button

to halt the program, terminate the debugger session, and return to the C/C++ perspective. 6. Disconnect the 14-pin JTAG cable from the Experimenter’s board.

7. Be sure that the batteries are in place on the underneath of the Experimenter’s board and move the SW1 – FET/USB/BATT power supply switch to BATT.

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10. Measure the current consumption:__________ (It should be between 1.9 mA – 2.1 mA). 11. Some further information:

Since the CPU performs a 32-bit fetch, code alignment can impact current consumption significantly …

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Active Running at 25 MHz

In this scenario we will change the core voltage levels for operation greater than 8 MHz and measure current consumption of the device in the active mode running at 25 MHz.

12. Disconnect and turn off your multimeter. Reconnect the JP1 – MSP430 PWR jumper, and the 14-pin JTAG cable. Move the SW1 – FET/USB/BATT power supply switch to FET.

13. Right-click in the CCS Project pane and select Active Build Configuration. Left-click ACTIVE_25_MHZ. Lab_2 should now be set as the [Active – ACTIVE_25_MHZ] build configuration.

14. Open ACTIVE_25_MHZ.c for editing and notice the following:

• SetVCore(PMMCOREV_3) is used to set one level at a time - <hal_pmm.c>

//***********************************************************// // Set VCore

//**********************************************************// unsigned int SetVCore (unsigned char level)

{

unsigned int actlevel; unsigned int status = 0; level &= PMMCOREV_3;

actlevel = (PMMCTL0 & PMMCOREV_3); // step by step increase or decrease

while (((level != actlevel) && (status == 0)) || (level < actlevel)) { if (level > actlevel) status = SetVCoreUp(++actlevel); else status = SetVCoreDown(--actlevel); } return status; }

• SVSx & SVMx management turns off SVSL and SVSM, leaves SVSH in full performance mode, and delivers fast wake-up (5 μs) time with SVS protection on DVcc

15. Click the Debug button, click the Run button and then click the Terminate

All button.

16. Disconnect the 14-pin JTAG cable from the Experimenter’s board and move the SW1 – FET/USB/BATT power supply switch to BATT.

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LPM3 REFO Mode

In this scenario we will enter the LPM3 mode with the default ACLK settings and measure current consumption of the device when the internal 32 kHz REFO clock sources ACLK. 20. Disconnect and turn off your multimeter. Reconnect the JP1 – MSP430 PWR jumper,

and the 14-pin JTAG cable. Move the SW1 – FET/USB/BATT power supply switch to FET.

21. In the CCS Project pane, set LPM3_REFO as the active build configuration.

22. Open LPM3_REFO.c for editing and notice the following:

• Entering LPM3 using intrinsic functions

__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, enable interrupts __no_operation(); // For debugger

• Watchdog triggers an interrupt approximately every 3 seconds

/* Initialize WDT to interval timer mode, triggering every 3 seconds */ WDTCTL = WDTPW+WDTSSEL__VLO+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0;

SFRIE1 |= WDTIE; // Enable WDT interrupt • Return from ISR using intrinsic function

// Watchdog Timer interrupt service routine #pragma vector = WDT_VECTOR

__interrupt void WDT_ISR(void) {

__bic_SR_register_on_exit(LPM3_bits); }

All button.

25. Remove and save the JP1 – MSP430 PWR jumper and connect the multimeter leads to the header with the red lead closest to the edge of the board.

26. Turn on your multimeter and set it to the lowest DC milliamp measurement range. (Be sure that the leads are connected to the proper jacks to read current).

27. LED1 on the Experimenter’s board will blink ON and OFF if the program is running correctly.

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LPM3 LFXT1 Mode

In this scenario we will handle oscillator faults to set LFXT1 ACLK and measure current consumption of the device when the internal 32 kHz crystal on the LFXT1 oscillator sources ACLK.

30. In the CCS Project pane, select LPM3_LFXT1 as the active build configuration.

31. Open LPM3_LFXT1.c for editing and notice the following:

• Initializing crystal pins and LFXT_Start( );

/* Initialize LFXT1 */

P7SEL |= BIT1+BIT0; // Enable crystal pins LFXT_Start(XT1DRIVE_0);

• LFXT_Start (XT1DRIVE_0); <hal_UCS.c>

void LFXT_Start(unsigned int xtdrive) {

UCSCTL6_L |= XT1DRIVE1_L+XT1DRIVE0_L; // Highest drive set - XT1 startup while (SFRIFG1 & OFIFG) { // check OFIFG fault flag

UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clr OSC flt flags SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag

}

UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) |(xtdrive); // set Drive mode }

All button.

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LPM3 VLO Mode

In this scenario we will evaluate the tradeoffs for oscillator at VLO ACLK and measure current consumption of the device when VLO sources ACLK.

39. In the CCS Project pane, select LPM3_VLO as the active build configuration.

40. Open LPM3_VLO.c for editing and notice the following:

• ACLK clock source selection

SELECT_ACLK(SELA__VLOCLK); // Select VLO_CLOCK to source ACLK

• Other UCS_Library macros

All button.

46. Measure the current consumption while LED1 is OFF:__________ (It should be

between 1.2 μA – 1.6 μA).

Halt Debugging and Close the Project

47. Turn off your multimeter.

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Introduction

This module will discover the mixed-signal capability of the MSP430 architecture and learn about its effect on low power operation. In the lab exercise we will measure an “analog” signal using the integrated temperature sensor, perform an analog-to-digital conversion, and send the results over a USB link to a CCS4 terminal window.

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Module Topics

Analog Peripherals ... 3-1

Module Topics... 3-2 Analog Peripherals ... 3-3

Comp_B Analog Comparator ... 3-3 ADC12_A... 3-4 Conversion Memory and Control ... 3-5 Lab 3 Overview ... 3-6

Lab 3: Brute-Force Temperature Sampling... 3-8

Objective ... 3-8 Procedure... 3-9

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Analog Peripherals

Comp_B Analog Comparator

Inverting and noninverting terminal input multiplexer

Software-selectable RC filter for the comparator output

Output provided to Timer_A capture input

Interrupt capability

Selectable reference voltage generator and voltage hysteresis generator

Reference voltage input from shared reference

Ultra-low-power comparator mode

44

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ADC12_A

ADC12_A Features

12-bits, SAR, 200 ksps+ Timer_A/B, software triggers Up to 12 external input Conversion Modes: Single Sequence Repeat-single Repeat-sequence Internal/external reference 16 conversion result storage

Input range: Vss – Vref

45

ADC12_A…

ADC12_A Enhancements

VREF settling time

75usvs. 17ms

Tighter temp coefficient on internal reference

±50ppm vs. ±100ppm

Lower power modes

Selectable speed vs power

ADC12_A core is only enabled when needed

Higher clock dividers for faster system clocks

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ADC12 Temperature & Vcc Sampling

On-chip temperature sensor channel

On-chip Vcc/2 channel

The temperature sample period > 30 us

Temp sensor offset voltage is large and must be calibrated

2-point calibration data inside Factory Application Data

47

Conversion Memory and Control…

Conversion Memory and Control

ADC12 Conversion Memory & Control

Each memory register is configurable

EOSx – Identifies the end of a sequence-of-conversions.

When the conversion result is written into the EOS ADC12MEMx register, the interrupt will be triggered.

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Lab 3 Overview

Lab 3: Brute-force Temperature Sampling

49

Lab 3 code…

Lab 3.c Code

while(1){

REFCTL0 |= REFON; // Enable internal reference

__delay_cycles(85); // Settling time for reference

ADC12CTL0 |= ADC12ENC+ADC12SC; // (Re)enable & trigger conversion // Poll IFG until ADC12MEM1 loaded signifying sequence is complete

while(!(ADC12IFG & BIT1));

ADC12CTL0 &= ~ADC12ENC; // Disable conversions to configure REF

REFCTL0 &= ~REFON; // Disable internal reference

temp_temp = ADC12MEM0; // Read ADC12 temperature conversion

temp_vcc = ADC12MEM1; // Read ADC12 Vcc/2 conversion // Calculate temperature in degrees Celsius & format display string accordingly

...

// Calculate temperature in degrees Fahrenheit & format display string accordingl

...

// Calculate Vcc in volts & format display string accordingly

...

/* Initialize serial communication module to send data over USB */

halUsbInit();

halUsbSendString(&USB_string[0],USB_STRING_LEN+2);

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Decoding the Alphabet Soup

voidhalADCInit(void){

ADC12CTL0 = ADC12SHT0_7 + ADC12ON + ADC12MSC; ADC12CTL1 = ADC12CONSEQ_1+ADC12SHP; ADC12MCTL0 = ADC12SREF_1 + ADC12INCH_10; ADC12MCTL1 = ADC12SREF_1 + ADC12INCH_11 + ADC12EOS; REFCTL0 |= REFMSTR + REFVSEL_1;

}

(User Guide) (msp430x54xA.h file)

51

Lab 3 Power…

CPU is ALWAYS ON (~290 uA)

Delay between ADC12 samples executed by software

__delay_cycles(2200000);

Lab 3 Power

540 uA 3 90uA Ac tive A DC = 150uA 2 90uA C u rre n t Time

2 s econds until next Sample Ac tiv e MCLK

@1MHz=290uA 1. 5V Internal Ref erenc e = 100uA 75us 80us

A ctiv e ADC = 150uA

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Lab 3: Brute-Force Temperature Sampling

Objective

The objective of the next three lab exercises (Lab 3 though Lab 6) is to gain an understanding on how the ultra-low power features of the MSP430F5438A compare in a mixed-signal application. In all three cases we will perform the same application task – measure an “analog” signal using the integrated temperature sensor, perform an analog-to-digital conversion, and send the results over a USB link to a CCS4 terminal window. Each case will show significant differences in power consumption:

• Lab 3 implements brute-force temperature sampling with the ADC12_A. This implementation had no interrupts, all CPU delays and flag polling. Current draw was about 300 uA.

• Lab 4 will use timer interrupts. We will handle the two second delay with a hardware timer interrupt. This will prove to be the most significant decrease in power

consumption.

• Lab 5 will be a fully optimized ADC12 routine. We will use the ADC12 interrupts to signify end-of-conversion. The timer will automatically handle the reference settling time as well as trigger the ADC12 sampling. This will maximize the time that the CPU spends in LPM3.

Lab 3: Using the ADC12

Use ADC12 integrated temperature sensor

Set up ADC12 to perform a single conversion

Loop continuously, converting to Degrees F and C in software

Touch the F5438A with a finger to change the temperature

Open a watch window in the debugger to see the temperature values

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Procedure

Import CCS Project

1. Import the CCS project for the next three lab exercises by clicking:

Project Æ Import Existing CCS/CCE Eclipse Project

In the Import dialog window click Browse and navigate to the C:\5xx_ODW folder and select OK. Next, in the Projects window check Lab_3, Lab_4, and Lab_5 (be sure all three labs are selected). Then check the Copy projects into workspace checkbox and click Finish.

2. Set Lab_3 as the [Active – Lab3] project by right-clicking on Lab_3 in the Project pane and selecting Set as Active Project. Click the plus sign

+

to the left of Lab_3 and notice the files are listed for the project.

Determine COM port for MSP-EXP430 Board

3. Connect the small size connector of the USB-to-miniUSB cable to the

MSP-EXP430F5438 Experimenter’s board and the other end to the USB port on your computer.

4. Determine the COM port used for the board by clicking (in Windows) Start Æ Run then

type devmgmt.msc in the box and select OK. (In Windows 7, just type into the Search programs and files box)

In the Device Manager window that opens, left-click the symbol left of Ports (COM & LPT) and record the COM port number for

MSP-EXP430F5438 USB – Serial Port (COMxx):________. Close the Device Manager.

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Examine, Download, and Run Code

5. Back in CCS, open Lab_3_soln.c for editing and notice the code used to calculate the temperature and voltage. The code that follows is used to format the data for displaying. At the bottom notice the code used to initialize the ADC12:

void halADCInit(void){

// 5.4MHz (MODOSC_max) * 30 us (t_sensor)= 162 cyc min samp time ADC12CTL0 = ADC12SHT0_7 + ADC12ON+ADC12MSC;

ADC12CTL1 = ADC12CONSEQ_1+ADC12SHP; ADC12MCTL0 = ADC12SREF_1 + ADC12INCH_10;

ADC12MCTL1 = ADC12SREF_1 + ADC12INCH_11 + ADC12EOS;

/* Initialize the shared reference module */

REFCTL0 |= REFMSTR + REFVSEL_0; // Configure internal 1.5V ref }

• ADC12SHT0_7 selects sample and hold time = 192 ADC12CLK cycles

t_sensor must be > (5.4 MHz (MODOSC_max) * 30 us (t_sensor) = 162 cycles)

• ADC12MSC selects multiple sample and conversion so multiple conversions are performed automatically (only a single trigger per SOC is required)

• ADC12SHP is the sample-and-hold signal select which selects SAMPCON to be sourced from sampling timer (~5 MHz MODOSC)

• ADC12SREF_1 selects the internal reference as the reference for ADC12MEM channels 0 and 1

• ADC12INCH_x is the input channel select (x = 10 for the temperature sensor; x = 11 for Vcc/2)

• ADC12EOS identifies channel 11 as the end-of-sequence of conversions

• REFMST disables backwards compatibility mode to leverage REF module

• REFVSEL selects 1.5V reference

To understand how the above code example works, first the bit field descriptions are found in the User’s Guide:

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And the bit fields are defined in msp430f5438a.h :

6. Turn on your multimeter and set it to a range that can measure about 300uA. Click the Debug button to assemble/compile and download the executable into the device flash memory.

7. Click the Run button to run the program.

Open a CCS4 Terminal Window

8. Make sure the code has been downloaded and running. In CCS select:

Window Æ Show View Æ Other…

In the Show View box, left-click the plus sign

+

next to Terminal. Click on Terminal and select OK. A terminal window will appear.

9. On the right side of the terminal pane ,click the Settings button. In the Terminal Settings window that appears, configure the Connection Type as Serial using the pull-down tab.

10. Make the following changes to the Terminal Settings and then click OK.

Port: COMxx as recorded in step 4 Baud Rate: 9600

Data Bits: 8 Stop Bits: 1

Parity: none Flow Control: none

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Current Measurement

12. Disconnect the 14-pin JTAG cable from the Experimenter’s board.

13. Click the Disconnect button in the Terminal pane and disconnect the USB-to-miniUSB cable from your PCs USB port.

14. Observe the current consumption. Because of the timer delay and the meters inability to read quickly changing currents, your readings will jump around

In this application the CPU is always on.

• The delay between ADC12 samples is executed by software

__delay_cycles(2200000); // Delay 2 seconds

• ADC12 is handled completely in software (i.e. reference settling, software trigger, IFG polling)

15. Turn off your multimeter and reconnect the 14-pin JTAG cable and the

USB-to-miniUSB cable.

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Introduction

This module will discuss the features of the MSP430 hardware timers. Many microprocessors incorporate timer to generate simple time intervals. The timers on the MSP430 include additional capabilities for generating PWM waveforms, controlling the ADC hardware, and even implement UART communication functions. In the lab exercise we will build on the previous exercise and use the hardware timers to conserve power.

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Module Topics

Hardware Timers ... 4-1 Module Topics... 4-2 Hardware Timers ... 4-3 Timer Architecture ... 4-3 Counting Modes ... 4-4 Interrupts ... 4-4 Timer_B vs Timer_A... 4-5 Lab 4 Details... 4-6

Lab 4: Using Hardware Timers to Conserve Power... 4-7

Objective ... 4-7 Procedure... 4-8

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Ha

rdware Timers

Timer Architecture

Asynchronous 16-bit timer/counter Continuous, up-down, up count modes Multiple capture/compare registers PWM outputs

Interrupt vector register for fast decoding Can trigger DMA

transfer

On all MSP430’s

55

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Counting Modes

Timer Counting Modes

56

Interrupts…

Interrupts

Timer_B Interrupts

TBCCR1 CCIFG

TBCCR2 CCIFG TBIV TIMER_B1_VECTOR

TBCCR1-6 and TB interrupt flags are prioritized and combined using the Timer_B Interrupt Vector Register (TBIV) into another interrupt vector

TBCCR0 CCIFG TIMERB0_VECTOR

The Timer_B Capture/Comparison Register 0 Interrupt Flag (TBCCR0) generates a single interrupt vector:

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Timer_B vs Timer_A

Default function identical to Timer_A

8, 10, 12, or 16-bit timer or counter (16-bit only for Timer_A)

Outputs double-buffered for simultaneous loading

CCRx registers can be grouped for simultaneous updates

Tri-state function from external pin

58

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Lab 4 Details

Lab 4 Temperature Measurement with Timer

Main loop Timer CCR0 ISR

59

Lab 4 Power…

Lab 4 Power

CPU is in LPM3 most of the time

Delay between ADC12 samples handled by

75us 80us 54 0uA 390u A Ac tive ADC = 150uA 290u A Cu rr en t Time

2 s ec onds until next Sampl e 1. 5V Internal Ref erenc e = 100uA

Acti ve ADC = 150uA Ac tive MCLK @1MHz=290uA 2.1uA

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Lab 4: Using Hardware Timers to Conserve Power

Objective

In this lab exercise we will perform the same application task as the previous exercise, but we will make use of Low Power Mode 3 to reduce power consumption. Timer B will be configured to count in up-mode and trigger an interrupt which will replace the two second software delay used in the previous lab exercise. Also, Timer B CCR0 interrupt service routine (ISR) will software trigger an ADC12 sample/conversion. These modifications will provide the most significant decrease in power consumption.

Lab 4: Using Hardware Timers to

Conserve Power

Perform same task as previous lab exercise, but use LPM3 to reduce power consumption

Timer B will be used to replace the 2 second software delay

FET

61

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Procedure

Set Active Project and Check COM Port Connection

1. Set Lab_4 as the [Active – Lab 4] project by right-clicking on Lab_4 in the Project pane and selecting Set as Active Project. Click the minus sign (

-

) next to Lab_3 to collapse the Lab_3 project. Click the plus sign (

+

) next to Lab_4 and notice the files are listed for the project.

2. Make sure that the small size connector of the USB-to-miniUSB cable is connected to the MSP-EXP430 board and the other end to the USB port on your computer. Also make sure your emulator cables are properly connected.

Examine, Download, and Run Code

3. Close any open editor panes. Open Lab_4_soln.c for editing and notice the code used to integrate LPM3, the Timer_ISR ( ), and initialize a Timer_B to trigger a periodic wake-up using a timer capture event:

• Integrate LPM3 into the code

// Bit-set (LPM3_bits + GIE) in SR register to enter LPM3 mode __bis_SR_register(LPM3_bits + GIE);

__no_operation();

• Timer_ISR( )

Handle the ADC12_A reference enable and software trigger

Clear the LPM3 bits in SR register on stack to exit active from the ISR

// Timer B0 CCR0 interrupt service routine #pragma vector=TIMER0_B0_VECTOR

__interrupt void TIMER0_B0_ISR(void) {

REFCTL0 |= REFON; // Enable internal 1.5V ref

__delay_cycles(85); // 1.5V REF settling time ADC12CTL0 |= ADC12ENC+ADC12SC; // (Re)enable & trig conv

__bic_SR_register_on_exit(LPM3_bits); }

• Init Timer_B to trigger a periodic wake-up using a timer capture event

void halTimerInit(void) {

TB0CCR0 = 65535;

TB0CCTL0 = CCIE; // CCR0 interrupt enabled TB0CTL = TBSSEL_1 + MC_1 + TBCLR; // ACLK, upmode, clr TBR }

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Connect the Terminal

6. Click the Terminal tab on the right of your screen, then click the Connect button. Right-click in the Terminal pane and select Clear All.

7. You should see scrolling temperature (in °C and °F) and the voltage in the Terminal pane. Verify the temperature reading changes in the terminal window by placing your finger or breathing on the MSP430 device on the board.

Current Measurement

8. Disconnect the 14-pin JTAG cable from the Experimenter’s board.

9. Click the Disconnect button in the Terminal pane and disconnect the USB-to-miniUSB cable from your PCs USB port.

10. Observe the current consumption. Because of the timer delay and the meters inability to read quickly changing currents, your readings will jump around

In this application the CPU is in LPM3 most of the time.

• The delay between ADC12 samples is handled by hardware