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Power Optimization of Linear Feedback Shift Register (LFSR) using Power Gating

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Figure

Fig. -1: Traditional n-bit LFSR
Fig. -5: Schematic of D flip-flop
Fig. -11: Schematic of D flip-flop with Coarse Grain Power Gating
Fig.15 shows the schematic for 16-bit LFSR with Fine Grain Power Gating (FGPG) technique, where the16-bit LFSR is designed using power gated D flip-flop as shown in Fig.8 and XOR gates
+2

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