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Yield Is Everyone

Yield Is Everyone

s Issue

s Issue

John Kibarian

John Kibarian

CEO, President and Founder

CEO, President and Founder

PDF Solutions

(2)

Nanometer Technologies

New Materials at Every Node

With critical-area and feature-count doubling per node, reaching the same yield requires twice the manufacturing efficiency with new materials as achieved with old materials

With critical

With critical--area and featurearea and feature--count doubling per node, reaching the same yield requires count doubling per node, reaching the same yield requires twice the manufacturing efficiency with new materials as achieve

twice the manufacturing efficiency with new materials as achieved with old materialsd with old materials

*Red shows use for mainstream CMOS

FD-SOI/UTB-SOI Ni-Si/TBD 3D SiO/SiN High-k Metal/Multigate Low-k Cu 193nm + OPC/PSM PO SOI/Strained silicon-SiGe Ni-Si SiO2/SiON

Dual Poly/SiGe Low-k Cu 193nm + OPC/PSM PO SiO2 SiON SiO2 SiO2 SiO2 )CVG&KGNGEVTKE Co-SiNi-Si Co-Si Co-Si Ti-Si 5CNKEKFG Epi/SOI P-Epi P-Epi P-Epi 5WDUVTCVG

Dual Poly/SiGe

Dual Poly Dual Poly Dual Poly )CVG'NGEVTQFG Low-k FSG FSG TEOS +PVGTEQPPGEV&KGNGEVTKE Cu 193nm + OPC/PSM PO Cu Al-Cu Al-Cu +PVGTEQPPGEV 248nm + OPC 248nm + OPC 248nm .KVJQ PO PO PO 2TQEGUU/QFWNG

(3)

New Materials and Complexity

Drive Process-Design Integration

Process-design complexity increasing at each new node

Process-design complexity increasing at each new node 3

5 7

13 (ITRS) Litho Resist

CD control (nm, 3sigma) Low-k 180M 90-nm Ni, SOI Cu none Major Material Changes

360M 90M

20M

(ITRS) Max.# ASIC

Transistors/cm2

65-nm 130-nm

0.18-µm ITRS “node”

• True SOC drives more complex IC functionalities

• New functionalities mandate more Process-Design Integration

– New process-modules for new materials create new yield loss mechanisms – Billions of design features must be modeled, optimized, controlled

– Process margins inherently low as micro-electronics t nano-electronics

• Systematic yield loss mechanisms, often not visually detectable, now dominant over visual defects

(4)

Process-Design Integration Issues

Drive a Process-Design Yield Gap

• Capability exists to reduce contamination limited yield

– Visible defects

– Random defect density – but…

• Feature limited yield now dominates functional

yield loss mechanisms

– Non-visible defects – Process-design systematics • New capabilities needed to achieve yields

Assumes data from ITRS 2001, with the following additional per-node assumptions from PDF’s client engagement history:

¾ ASIC Chip area +10%; # Metal layers increasing

¾ Metal Area +2x per layer; -55% in Fail Rate

¾ # vias +2x; -45% in Fail Rate

¾ # contacts +2.5x; -45% in Fail Rate

Assumes data from ITRS 2001, with the following additional per-node assumptions from PDF’s client engagement history:

¾ ASIC Chip area +10%; # Metal layers increasing ¾ Metal Area +2x per layer; -55% in Fail Rate ¾ # vias +2x; -45% in Fail Rate

¾ # contacts +2.5x; -45% in Fail Rate

50% 60% 70% 80% 90% 100% 0.35 0.25 0.18 0.13 0.09 0.065

ITRS Node (microns)

Lim it ed Y ie ld

Critical Area Based (Metal, Poly) Feature Based (Contacts, Vias)

Process-Design Yield Gap

– Contact fail rates must be less than 3 ppb – Via modules fail rates must be less than 2 ppb – Need a process window that spans layout

variations

– Contact fail rates must be less than 3 ppb – Via modules fail rates must be less than 2 ppb – Need a process window that spans layout

(5)

New Key Process Elements will

Increase Design-Yield Gap Issues

65nm

‰ Litho ‰ Layout, tool, OPC/PSM integration issues ‰ Front end/Transistor ‰ Layout dependent performance

‰ Product ramp issues

‰ Parametric control

65nm

‰ Litho ‰ Layout, tool, OPC/PSM integration issues ‰ Front end/Transistor ‰ Layout dependent performance

‰ Product ramp issues

‰ Parametric control

45nm

‰ Litho

‰ Layout, eqp, OPC/PSM integration issues

‰ Front end/Transistor

‰ New transistor architectures

‰ Product ramp issues

‰ Reliability control

45nm

‰ Litho

‰ Layout, eqp, OPC/PSM integration issues

‰ Front end/Transistor

‰ New transistor architectures

‰ Product ramp issues

‰ Reliability control

90nm

‰ Backend integration issues

‰ LowK: stress and rel

‰ CMP - multi-layer issues

‰ Product ramp issues

‰ Yield-performance tradeoffs

90nm

‰ Backend integration issues

‰ LowK: stress and rel

‰ CMP - multi-layer issues

‰ Product ramp issues

‰ Yield-performance tradeoffs

(6)

• Prior to 130nm

• Yield was driven primarily by Product Engineers • Implementation was done primarily by the Fab • Design Teams participation was non existent

• At 130nm and beyond, Process-Design Integration Issues require all elements to work in tandem to achieve yields necessary to hit product volumes and business profits • The industry is realizing the issue, what is needed are

solutions that:

• Are standardized to allow rapid implementation • Consider specific process- design interactions • Grounded in the reality of 2-3 ppb failure rates

• Have unique business models ensuring the provider is aligned to not only pointing out issues but helping resolve them

To Resolve This Growing Gap

Yield is Everyone’s Issue

To Resolve This Growing Gap

(7)

PDF Solutions

®

• Close the Design-to-Silicon-Yield gap

• Create more manufacturable ICs, more capable

processes

• Work side-by-side with customers to achieve

measurable results

PDF Solutions is the leading provider of

PDF Solutions is the leading provider of

Process

(8)

Major Elements

PDF Solutions Offering

• Integrated Yield Ramp (IYR) Solution

– Helps processes ramp to yield faster, historically 2X faster – Provides an infrastructure to help maintain yield

improvements throughout the life of the process

• pDfx ™ Design for Manufacturability Environment

– Provides designers with the ability to make yield trade offs

– Provides process aware DFM capability to designer

• New Solutions for the Product Engineer

– dataPOWER ™ Yield Management System

(9)

PDF Process-Design Integration

Fab and Test

Product Design

pDfx™

Layout Yield and Variability Models Circuit Surfer® Analog Digital Design Optimization Statistical Spice Models

Process-Design Integration knowledge base

CV™Infrastructure

pdCV™

CV™ test chips pdFasTest™

Yield Learning

Layout Dependant Models • Fail Rates

• Performance Variability • Module Sensitivities

YRS™ Module PrioritiesProduct Hot Spots Yield Entitlement Design Benchmarks Layout Sensitivites Process Benchmarks Failure Analysis Fab Data WAMA™ Optimized Shotmap dataPOWER™ Product Analysis Filtered Fab Data Process Optimization

(10)

Solution: Integrated Yield Ramp

Fab and Test

Product Design

pDfx™

Layout Yield and Variability Models Circuit Surfer® Analog Digital Design Optimization Statistical Spice Models

Process-Design Integration knowledge base

CV™Infrastructure

pdCV™

CV™ test chips pdFasTest™

Yield Learning

Layout Dependant Models • Fail Rates

• Performance Variability • Module Sensitivities

YRS™ Module PrioritiesProduct Hot Spots Yield Entitlement Design Benchmarks Layout Sensitivites Process Benchmarks Failure Analysis Fab Data WAMA™ Optimized Shotmap dataPOWER™ Product Analysis Filtered Fab Data Process Optimization

(11)

Integrated Yield Ramp (IYR) Solution

• Integrated Yield Ramp (IYR) Solution is the

linchpin to PDF’s ability to drive improved yields

• The IYR Solution is comprised of 3 major elements

– Technology: Integrated Technology Infrastructure – Process: Patented Process-Design Integration

Methodology

– People: PDF Team integrated with Client’s organization, measured to common goals

• IYR Solution is customized to

– Each process node

(12)

IYR Patented & Proven Methodology

Functional & Parametric Yield Modeling Product Layout Analysis CV-based Module Characterization

Product Manufacturing Data

Product Data Filtering, Modeling

Yield Gap, Yield Loss Pareto and Yield Issue Prioritization

Root Cause Hypotheses Process split and validation Process split and validation Pred Yield Poly all poly 0.99 M1 shorts 0.95 M2 shorts 0.96 M3 shorts 0.98 Contact N+AA 0.97 Contact P+AA 0.98 Contact N+Contact 0.98 V2 Borderless 0.90 V2 Border 1.00 V3 all 0.99 Parametric VthP 0.97 Total 0.70 Module Localization, Visualization

(13)

Mechanism Apr Jul Aug Sep Oct Nov Dec Jan Now Random Defect Limited Yield 48% 48% 55% 60% 62% 72% 67% 70% 71% Systematic Contact Open 96% 96% 96% 96% 96% 96% 96% 100% 100% DRAM process improvements 40% 100% 100% 100% 100% 100% 100% 100% 100% BEOL topography 95% 80% 80% 80% 89% 100% 100% 100% 100% PID Issue 90% 90% 90% 90% 100% 100% 100% 100% 100% CMP Process condition 90% 100% 100% 100% 100% DRAM systematic 82% 82% 86% 81% 85% 100% 100% DRAM wafer-edge parametric 95% 95% 95% 95% 93% 92% 90% 90% 100% Wafer bin X center fail 69% 69% 69% 100% 100% 100% 100% 100% 100% DRAM bin Y (scanner Z) 96% 100% 100% 100% 100% 100% 100% Front-half of lot yield loss (eq Q) 98% 98% 100% 100% 100%

DRAM failure (eq W) 94% 94%

Center die 100% 100% 100% 100%

Random wafer equipment

dependency 96% 98% 98% 98% Functional LY 10% 22% 20% 32% 37% 48% 48% 58% 65% Speed LY 50% 50% 80% 80% 93% 96% 96% 95% 97% Total Yield 5% 11% 16% 26% 35% 46% 46% 55% 63% P roces s Pr ob le m s E qui pmen t P roble m s Defect

Yield Pareto

Issue vs. Improvement vs. Time

PDF Yield Ramp Team

identifies and

quantifies signatures

for key yield issues

with advanced tools

and methods

PDF Yield Ramp Team

identifies and

quantifies signatures

for key yield issues

with advanced tools

and methods

0% 20% 40% 60% 80% 100% Apr Jul Aug Sep Oct Nov Dec Jan Now Functional LY

Random Defect Limited Yield Systematic Contact Open DRAM process improvements BEOL Topography PID Issue

CMP Process condition DRAM systematic DRAM wafer-edge parametric Wafer bin X center fail DRAM bin Y (scanner Z) Front-half of lot yield loss (eq Q) DRAM failure (eq W) Center die

Random wafer equipment dependency

(14)

Client Results

High Volume Game Chip

Client Results

High Volume Game Chip

¾

Data shown starts at mass

production

¾

Program started during

integration

¾

Length of integration phase

equivalent for both nodes

Yield Improv ement Time Perform ance w ith PDF Baselin e (prev ious node w ithout P DF) Mature yield 5 percentage points over baseline Mature yield 5 percentage points over baseline Estimated cost savings > US$100 million Estimated cost savings > US$100 million Product introduction 28 percentage points over baseline Product introduction 28 percentage points over baseline

Actual data – printed with permission

Customer has engaged with PDF

on all subsequent process nodes

Customer has engaged with PDF

on all subsequent process nodes

(15)

Solution: Process-Aware DFM

Fab and Test

Product Design

pDfx™

Layout Yield and Variability Models Circuit Surfer® Analog Digital Design Optimization Statistical Spice Models

Process-Design Integration knowledge base

CV™Infrastructure

pdCV™

CV™ test chips pdFasTest™

Yield Learning

Layout Dependant Models • Fail Rates

• Performance Variability • Module Sensitivities

YRS™ Module PrioritiesProduct Hot Spots Yield Entitlement Design Benchmarks Layout Sensitivites Process Benchmarks Failure Analysis Fab Data WAMA™ Optimized Shotmap dataPOWER™ Product Analysis Filtered Fab Data Process Optimization

(16)

pDfx™ Product Overview

pDfx™ Product Overview

• Optimizes to product-specific objectives within design constraints

– Die cost: best Good Die per Wafer (GDPW) – Yield variability: best process window for yield

– Performance variability: best process window for performance

– Target Manufacturing Date Range: best solution for the process maturity

Client Design Flow

Verification pDfx™ Architectural Design Logical Design Physical Design Models Yield Gap Estimator Yield Optimizer

DFM Software Technology Kit

Standard IP Platform

Extended IP

Client Design Flow

VerificationVerification pDfx™ Architectural Design Logical Design Physical Design Models Yield Gap Estimator Yield Optimizer

DFM Software Technology Kit

Standard IP Platform

(17)

Delivering DFM Results

0% 2% 4% 6% 8% 10% 12% 14% 16%

Client 1 Client 2 Client 3 Client 5 Client 4

Ch a n g e in G ood D ie p er W a fe r (% )

PDF"DBYI" SERVICES CLIENT pDfx

DBYI Service Results

Client 1 : IDM

¾ 0.13u CMOS technology Client 2 : IDM

¾ 0.15u eDRAM technology

pDfx Service Results

Client 3 : Fabless

¾ 0.13u CMOS technology

pDfx Results

Client 4 : IDM

¾ 0.13u CMOS technology Client 5 : Fabless

¾ 0.13u CMOS technology

(18)

Solution: Volume Manufacturing

Fab and Test

Product Design

pDfx™

Layout Yield and Variability Models Circuit Surfer® Analog Digital Design Optimization Statistical Spice Models

Process-Design Integration knowledge base

CV™Infrastructure

pdCV™

CV™ test chips pdFasTest™

Yield Learning

Layout Dependant Models • Fail Rates

• Performance Variability • Module Sensitivities

YRS™ Module PrioritiesProduct Hot Spots Yield Entitlement Design Benchmarks Layout Sensitivites Process Benchmarks Failure Analysis Fab Data WAMA™ Optimized Shotmap dataPOWER™ Product Analysis Filtered Fab Data Process Optimization

(19)

Worksheet Analysis Environment MES/WIP Equipment Metrology Events Defect PCM/E-test Sub-Cons Wafer Sort SFC Assembly Final Test Bitmap Financials ERP

Interactive Web Reports

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report builder External Software Prep ro ces so rs Prep ro ces so rs IFF Optional

Analyze & Report

Data Re aders Format Files ASCII Binary Defect Integrated dataBASE dataBASE SQL ASCII Batch Manager

dataPOWER™ YMS Platform

(20)

Bin Pareto by Product & Lots

Drill-down to Bin Stacks by

Wafer

dataPOWER™

Drill-down Analysis Example

dataPOWER™

Drill-down Analysis Example

Drill-down to Wafer Map

(21)

WAMA™ Wafer Level DFM

Customer’s vs.

WAMA

Placement

Actual Customer Layout Actual WAMA WAMAWAMA WAMA Layout

Good Die increase 4%

Good Die increase 4%

• Gross Die per wafer = 433 • Good Die per wafer = 327

• Gross Die per wafer = 439 • Good Die per wafer = 341

(22)

Conclusion

• Resolving Process-Design Integration issues is

critical to success in the nanometer-era

• Success requires involvement by all product

functions

• Product Functions need the proper methodologies

and tools

• Are standardized to allow rapid implementation • Consider specific process-design interactions • Grounded in the reality of 2-3 ppb failure rates

• A partner whose business model is tied to their success

References

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