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Application Note Describing Dual Edge Rails Tuning
ON Semiconductor offers a wide range of voltage regulators for Intel platforms. For multiphase dc-dc solutions dual edge rail architecture is used. This application note discusses the tuning techniques for a dual edge rail.
Dual Edge Rails
The dual edge modulator under discussion in this application note compares the compensated error signal with a number of internally generated interleaved ramps to produce the required PWM duty cycle. The number of ramps is equal to the number of phases per output voltage rail. Dual edge modulation offers advantages such as fast response to load attack and release events, fixed frequency operation allowing for predictable output voltage ripple. The following sections describe tuning of a dual edge voltage rail.
PROGRAMMING
DETECTION
MONITOR AMP
DAC
OVP COMPARATORS
MAX OVERCURRENT
OVERCURRENT CURRENT
CURRENT
COMPARATORS UVLO & EN
ERROR INTERFACE
SVID
MUX MONITOR THERMAL
PSYS 46 ICCMAX_2ph 18 VRHOT# 31
SDIO 32 ALERT# 33 SCLK 34
ICCMAX_1a 19 ROSC_SAUS 15 ROSC_COREGT 14
VRMP 12 ICCMAX_1b 20
VSP_2ph 47
_ +
SENSE
BALANCE CURRENT AMPLIFIERS
AMP
& LOGIC
STATE POWER
PWM ADC
GENERATORS DAC
OSCILLATOR
& RAMP GENERATORS LOGIC
VR READY DATA
REGISTERS
IPH2
CURRENT DAC
OVP
IPH1
OCP FORWARD
1.3V
ENABLE
GATE
AMP
COMP VSN VSP
PS# 16 PWM1_2ph
PWM2_2ph 17 IOUT_2ph
PWM2
1.3V
_
_ +
VR_RDY 38
VSN VSP
PWM1
Buffer
DIFFOUT_2ph 2
CSP2_2ph 9
CSP1_2ph 10
DRVON 35
CSREF_2ph 8
CSSUM_2ph 7
CSCOMP_2ph 6
ILIM_2ph 5
IOUT_2ph 1
FB_2ph 3
VSN_2ph 48
COMP_2ph 4
ENABLE PS#
DRVON PS#
PS#
VRMP
CSCOMP CSREF
ADDR_VBOOT 21
IOUT FEED-
ZERO OVP ENABLE
ENABLE
OVP
OCP OVP
DRVON
OCP OVP
DIFF
TSENSE_2ph 11 TSENSE_1ph 23
IOUT_1a IOUT_1b
VCC 13 EN 37
GROUND 49
Figure 1: Block Diagram of Dual Edge Architecture
Table 1: Glossary of terms and their values
Name Description Value
LL Loadline 2 mΩ
fSW Switching Frequency 600kHz VIN Maximum input voltage 20V
VOUT Output voltage 0.9V
Vov Allowed overshoot 70mV
CCM VRIPPLE Continuous conduction mode voltage ripple
±10mV
ΔI Maximum load step 70A
Ilimit Over current protection trip value
80A
IccMax Rail maximum current 70A
Np Number of Phases 3
LC Selection
The selection of output stage components is usually the first step in any VR system design. The inductor and capacitor selection directly influences the maximum output current, output voltage ripple and dynamic performance.
The minimum value for an output inductor required can be estimated by the expression below:
− ×
× ×
≥ ×
in p RIPPLE
SW V
N V V
f
LL
Lmin V0 1 0 Eq 1
V nH V mV
kHz m
L V 130
20 9 . 3 0 20 1
600 2 9 . 0
min =
− ×
× × Ω
≥ ×
Lselected =220nH
The next step is to estimate the output capacitance required. The selected output capacitance can be a
mix of multilayer ceramic capacitors (MLCCs) and electrolytic capacitors.
The value for the required minimum output capacitance can be estimated by the expression below:
) 0
( /
I V LL V
I N C L
OV P select g
OUTstartin
∆ × +
∆
= × Eq 2
mF A V
m mV
A
COUTstarting nH 1.9
9 . 0 70 ) 2 70
(
70 3 /
220 =
× +
Ω
= ×
Please note COUT may be higher or lower based on board performance. Dynamic testing needs to be completed to reach the optimum value of COUT.
Discrete Components Selection for Tuning
Differential Current Balance Amplifier Inductor DCR current sensing method is used to extract accurate per phase current information. For this purpose RCSN and CCSN is connected in parallel to the inductor as shown in Figure 2 below:
RCSN CCSN
DCR LPHASE
CSP CSN
SWN VOUT
Figure 2: DCR current Sensing
Ensure that the CCSN chosen is in the range of 20nF to 470nF, while keeping the RCSN above 2kΩ. Thus, the expression for RCSN can be written as
DCR CCSN
RCSN LPHASE
= × Eq 3
Select CCSN=0.033µF and by using above expression the value of RCSN can be calculated as follows:
Ω Ω=
= × k
m F
RCSN H 2.415
76 . 2 033 . 0
22 . 0 µ
µ
Total Current Sense Amplifier
The currents from all phases are summed together in a single temperature compensated total current signal.
The Rref resistors average the voltages at the output sides of the inductors to create a low impedance reference voltage CSREF. The RPH are use to set the gain of the current sense (CS) amplifier and influence the loadline. Figure 3 below is showing an example of a two phase current sense amplifier.
CSN1
RTH CSREF +
CSN3 CSN2
SWN1
SWN3 SWN2
CSCOMP -
RCS2 RCS1
CCS1
CCS2 RPH1
RPH2 RPH3 RREF1
RREF3 RREF2
CREF
Figure 3: A typical Total Current Sense Amplifier
The DC equation for the current sense is
) 1 (
2 1
DCR Rph Iout
Rth Rcs
Rth Rcs Rcs
VCSCOMPCSREF + ∗ Total∗
+ ∗
−
− = Eq 4
Taking Vcscomp-Vcsref divided by Iout gives the resulting load line of the rail as follows:
R DCR LL R
Ph CS ×
= Eq 5
Figure 4: Section of Block Diagram showing CS Amplifier block
It is recommended to choose Rcs = 220kΩ and then calculate RCS1, RCS2 and RTH as described in the next section and then solve for Rph(x).
DCR Temperature Compensation An NTC Thermistor (RTH) is placed in the feedback network of total current sense amplifier. The thermistor must be placed near the phase 1 inductor to sense the inductor temperature and compensate both the DC gain and the filter time constant for the DCR change with temperature. The values of RCS1
and RCS2 are set based on the effect of temperature on both the thermistor and inductor.
The following procedure and equations will give rise to the values of RCS1, RCS2 and RTH (at 25°C)
1) Select an NTC thermistor close to selected RCS. In this case an NTC value of 220kΩ is chosen.
2) The next step is to calculate the relative resistance of the selected thermistor at two temperatures. The temperatures that were chosen in this case are 50°C and 90°C. Calculate the relative resistance ratios A and B as follows:
311 . 220 0
411 . 68
) 25 (
) 50 (
0
0 = =
=
C TH
C TH
R R A
0634 . 220 0
962 . 13
) 25 (
) 90 (
0
0 = =
=
C TH
C TH
R R B
From the thermistor datasheet that is selected A and B can be calculated as 0.311 and 0.0634 respectively
3) Find the relative value of RCS required for each of these temperatures. This is based on the percentage temperature change needed, which is initially 0.39% /°C. These are called r1 and r2
respectively and can be calculated as follows:
) 25 ( 1
1
0 1
1 TC T C
r= + × −
) 25 ( 1
1
0 2
2 TC T C
r = + × −
Where T1 =50°C, T2 =90°C, TC=0.0039°C-1
Substituting above values and the values of r1 and r2 can be calculated as 0.9112 and 0.7978 respectively.
The relative values for RCS1, RCS2 and RTH are called rCS1, rCS2 and rTH respectively. These values are calculated by using the expressions below:
) ( ) 1 ( ) 1 (
) 1 ( ) 1 ( ) (
2 1
1 2
2 1
2 A Br B Ar A B
r A B r B A r r B rCS A
−
−
−
−
−
− +
−
−
= −
2 1 2 1
1 1
) 1 (
cs cs
CS
r r
A r r A
− −
−
= −
1 2
1 1
1 1
cs cs TH
r r r
− −
=
The values of rCS1, rCS2 and rTH are calculated 0.738933, 0.340444 and 1.120791
4) Calculate the required value of RTH by using the expression below:
Ω
=
×
=r R k
RTH TH CS 246.1
The closest value to 246.574kΩ is 220kΩ. Therefore, we select a NTC Thermistor of value 220kΩ.
5) Compute a scaling factor k based on the ratio of the actual thermistor used relative to the calculated ideal.
894 . 0
) (
)
( =
=
CALCULATED TH
ACTUAL TH
R k R
6) The value of RCS1 and RCS2 can be calculated by using equations below:
1
1 CS cs
CS R k r
R = × ×
)) ( ) 1
(( 2
2 CS cs
CS R k k r
R = × − + ×
The calculated values of Rcs1 & Rcs2 are 66.81kΩ and 168.3kΩ respectively. Finally we can select the closest standard resistor values for RCS1=75kΩ and RCS2=165kΩ.
Loadline Programming
The gain of the total current sense amplifier is decided by the ratio of RCS and RPH. The value of RCS
can be calculated as follows:
TH CS
TH CS CS
CS R R
R R R
R +
+ ×
=
1 1
2 Eq 6
Substituting RCS1=75kΩ, RCS2=165kΩ and Rth=220kΩ the calculated value of RCS =220.932kΩ. The corresponding value of RPH=304.88kΩ can be calculated by using the expression below:
Ω
= Ω Ω ×
= Ω
×
= m k
m DCR k LL
RPH RCS 2.76 304 2
220 Eq 7
CCS Calculation
The total current signal is proportional to the component of inductor voltage caused by DCR drop and consequently relative to inductor current.
Connecting CCS2 in parallel with CCS1 allows fine tuning of the pole frequency. It is recommended to fine tune this filter frequency during transient testing. The expression for the calculation of CCS is as follows:
CS
CS DCR R
C L
= × Eq 8
k pF m
CCS nH 362
220 76
. 2
220 =
Ω
×
= Ω
Over Current Protection
The current limit of the converter is programmed with a resistor RILIM between the ILIM and CSCOMP pins. The expression for the setting of Rilim is as follows:
A DCR R I
R R
OUT PH CS
ILIM 10µ
)
( ×
×
= Eq 9
The maximum current limit is 80A.
Ω
= Ω
× Ω×
Ω
= k
A m k A
k
RILIM 16
10
) 76 . 2 80 304 ( 220
µ RIOUT Selection
The IOUT pin sources a current equal to 10 times the ILIM sink current. A resistor to ground on the IOUT pin converts this current to a voltage. RIOUT should be scaled such that a load current equal to the rail max current generates a 2V signal.
) max
( 10
2
OUT PH
CS ILIM IOUT
I R DCR
R R R
×
×
×
= × Eq 10
RIOUT is calculated as follow for an IOUT max of 70A:
Ω
=
× Ω Ω×
× Ω
Ω
= × k
A k m
k k
RIOUT V 22.8
70 ) 76 . 304 2 (220 10
16 2
A capacitor (CIOUT) is selected to filter output ripple current information from the Iout reading but must not be so large that it significantly increases the
settling time of the IOUT reading. The CIOUTSP chosen for this case is 470pF.
RIOUT CIOUT
IOUT
Figure 5: RIOUT Network
Figure 6: Section of Block Diagram showing ILIM and IOUT block
DAC Feed Forward Programming DAC feed-forward is used to aid the output voltage in tracking the internal DAC during VID up transitions. The DAC feed-forward implementation is realized by having a filter on the VSN pin.
Programming RFF sets the gain of the DAC feed- forward and CFF provides the time constant to cancel the time constant of the system per the following equations.
RFF CFF VSN
VSS
Figure 7: DAC Feed Forward Filter 106
6 . 453 ×
∗
∗
=C LL
RFF OUT Eq 11
FF
FF R
Cout
C = LL∗ Eq 12
Using Eq 11 and Eq 12 to calculate component values:
Ω
=
×
∗ Ω
∗
= mF m k
RFF 1.9 2 453.6 106 1.72
k nF mF CFF m 2.2
72 . 1
9 . 1
2 =
Ω
∗
= Ω
Figure 8: Section of Block Diagram DAC feed forward block
Voltage Compensation
The block diagram of feedback Control Loop for a buck converter is shown below:
PWM GLC(s)
Gc(s)
Plant =Gm(s)
Compensation Network
-
+ dVout(s)
dD(s) dVc(s)
Figure 9: Block Diagram of a Control System
The PWM and output filter stages are grouped together as the plant (modulator) Gm(s). The compensation network transfer function is Gc(s).
The open loop transfer functions of the output Vout with respect to duty cycle D(s) can be written as follows:
1 ) (
1 )
( ) (
0
2 +
+ +
+
= +
ESR out
out
out ESR in
out
R DCR R C
s L LC s
C V sR
s dD
s
dV Eq 13
RESR = ESR of output capacitor C, L = Inductance of output inductor, COUT= Output capacitance, R0=output load
There will be two poles and one zero in the above transfer functions. The poles are created by the resonance of LC output filter while the zero is created by the ESR of the output caps. The double poles are located at
OUT n
p L C
f 2π
= 1 Eq 14
Where n
Ln = and n= number of phases. The zero is L located at
OUT ESRC f R
π 2
1
0 = Eq 15
Figure 10: Section of Block Diagram showing voltage compensation block
Type III compensation is used optimize the response of the VR. This network provides a pole at the origin with two poles and two zeros.
+ DIFFOUT
-
COMP
R1 FB
R2 C1 R3
C2
C3
1.3V
EA
Figure 11: Type III compensator
The open loop transfer functions of the output Vout with respect to compensation network VC(s) can be written as follows:
1 ) (
1 )
( ) (
0
2 +
+ +
+
= +
ESR OUT
out
OUT ESR M
IN C
out
R DCR R C
s L LC s
C sR V
V s dV
s
dV
Substituting VM=VIN/10
1 ) (
10 1 ) (
) (
0
2 +
+ +
+
× +
=
ESR OUT
OUT
OUT ESR C
out
R DCR R C
s L LC s
C sR s
dV s
dV Eq 16
Example: fC=120 kHz, L=220n H, Np=3, DCR=2.76mΩ, Cout=1.9m F, R0=10kΩ, RESREQ= 30µΩ, M=Desired Phase Margin=75°
The basic steps to synthesize a type III compensation network are as follows:
1) Choose a cross over frequency and determine the plant gain GM at the cross over frequency, fC
1 ) (
) 2 ( ) 2 (
1 10 2
0
2 +
+ +
×
× +
×
×
+
×
×
× ×
=
ESREQ EQ OUT n C OUT
n C
OUT ESREQ C m
R DCR R C
f L C
L f
C R G f
π π
π
Substituting the values in the above expression gives
Gm=0.128
2) Determine the LC double pole and ESR zero frequencies fP and FZ using Eq14 and Eq15 respectively.
kHz nH mF
C L f
out n
p 13.5
9 . 1 3 * 2 220
1 2
1 =
=
= π π
mF MHz C
f R
out ESREQ
z 2.79.
9 . 1 30 2
1 2
1 =
× Ω
= ×
= π π µ
3) Determine the plant Phase shift Pm in degrees at fC using the expression below:
−
= − −
P C Z
C
m f
Tan f f
Tan f
P 1 2 1 Eq 17
Substituting the values in the above expression to calculate plant phase shift gives:
0 1
1 164.7
5 . 13 2 120 79
. 2
120 =−
−
= − −
kJz Tan kHz
MHz Tan kHz
Pm
4) Determine the required compensation network gain G. The gain G is the required compensation gain at fC and must be equal to the plant attenuation. Substituting the value of Gm gives the value of required compensator gain as:
8125 . 128 7 . 0
1 =
= G
5) Choose the desired phase margin (75°) at fC. Calculate the required phase boost by using expression below:
900
−
−
=M Pm
boost
θ Eq 18
Substituting the values in the above expression gives phase boost as follows:
0 0
0
0 165 90 149.7
75 + − =
boost = θ
6) Determine the K value as follows:
+
= 2 450
tan boost4
K θ
Substituting the values in the above expression gives K as follows:
6 . 56 4 45
tan 150 0
0
2 =
+
K=
7) Choose a value of R1 between 500Ω and 1kΩ. Selecting R1=1kΩ and calculate the values of the components using the K-factor approach expressions below:
Ω
− =
= GR k
K
R K 1 1.06
2 1
Ω
− =
= 18
1
1
3 K
R R
GR nF f C K
C
44 . 2 9
1
1
1 − =
= π
GR pF C f
C
2 170 1
1
2= =
π
nF
K K GR C f
C
26 . 1 1 2 .
1
1
3= − =
π
IccMax Setting
On startup a resistor to ground on the IccMax pin programs the IccMax register value (for details regarding IccMax please consult the relevant datasheet). The value of the register is 1A per LSB.
The exact expression of IccMax can be found in the relevant datasheets
Figure 12: Section of Block showing ICCmax & Tsense block
TSENSE Network Tuning
A temperature monitoring input is provided by the Tsense pin. The voltage on the temperature sense input is sampled by the internal ADC. See the specification table for the thermal sensing voltage thresholds and source current in the corresponding datasheets.
CP
RTH
100k RP
RS
Figure 13: Tsense Network
The steps for the calculation of Tsense network is as follows:
1. Select VR_HOT and ALERT assert threshold voltages form the datasheet.
2. Convert the threshold voltages in the datasheet to resistor values using Ibias
current from the datasheet as R1 and R2. 3. Select two target temperatures T1 and T2
and calculate NTC resistance values at those temperatures as Rn1 and Rn2 using expression below:
1) (1
T0
T NTC nx
e
xR R
×
−=
β Eq 19TX= Selected temperature in Kelvin T0= Room temperature in Kelvin
4. Calculate the value of A,B and C as follows:
) (
)
(R1 R 2 R 2 R1
A= n + n − n + Eq 20
) (
)
(R2 R1 Rn1 Rn2
B= − × + Eq 21
) (
)
(R2 R1 Rn1 Rn2
C = − × × Eq 22
5. Calculate the value of RP using the expression below:
A AC B
RP B
2
2−4
±
= − Eq 23
6. Calculate the value of Rs using the expression below:
P n
P n
S R R
R R R
R = − +
1 1
1 Eq 24
Example:
For Ibias=120µA, VR_Hot threshold=468m V, Alert threshold=488m V the values of R1 and R2 can be calculated as:
R1=3.9kΩ, R2=4.066kΩ
For T1=104°C, T2=100°C, T0=25°C, RNTC=100kΩ and ß=4250 the values of Rn1 and Rn2 can be calculated as:
Rn1=5.049 kΩ, Rn2=5.698kΩ
Using Eq 23 RP can be calculated as:
RP= 5.52kΩ
Using Eq 24 RS can be calculated as:
RS= 1.26kΩ
7. The recommended value of CP is 0.1µF.
Conclusion
The equations discussed previously are given to aid the platform designer to select the compensation and configuration components for use with ON Semiconductor’s multiphase VR controller. An overall example of schematic block diagram is shown in Figure 14 below:
NTC PWM1
DRON
PWM2
PWM3
CSCOMP ILIM CSSUM CSP1
CSP2
CSP3
CSREF VSP
VSN
DIFFOUT
FB
COMP
+5V
VCC
IOUT
NTC
TSENSE
VRHOT Vpu
GND SKT_SNS+
SKT_SNS−
SDIO
ALE RT
SCLK
Vpu Vpu
NTC
TSENSE
batt chrgr PSYS
IOUT
SKT_SNS+
SKT_SNS−
VSP
VSN
DIFFOUT
FB
COMP
VRRDY EN
NTC PWM
CSP CSN ILIM
SKT_SNS+
SKT_SNS−
VSP
VSN
COMP VRMP VIN
IOUT
Vcc_Multiphase Rail1
Vcc_Enhanced RPM Rail
VDRV
VIN
ON DrMOS
VDRV
VIN
ON DrMOS
VDRV
VIN
ON DrMOS
VDRV
VIN
ON DrMOS
NTC PWM1
DRON
PWM2
PWM3
CSCOMP ILIM CSSUM CSP1
CSP2
CSP3
CSREF
Vcc_Multiphase Rail2
VDRV
VIN
ON DrMOS
VDRV
VIN
ON DrMOS
VDRV
VIN
ON DrMOS
Figure 14: Rails schematic Block Diagram
