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Optimized memory allocation and power minimization for FPGA based image processing

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Figure

Figure 1. Mapping a 3-D array into row-major and colum-major order 2-D arrays.
Figure 2. Mapping 2-D array of dimensionswidth x = Bw and y = W × H to a × b BRAMs configured for M and height N.
Figure 4. Partitioning across one BRAM horizontally. Each access consumes 1 power consumption quantum.
Table 1sizes and pixel bit widths. Several of the configurations are not power-optimised: notice that for pixelsof widths 10, 14 and 22, BRAM configuration 2and 11 BRAMs per access, respectively)
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